CN101840924A - 半导体装置及背面照射型固体摄像装置 - Google Patents

半导体装置及背面照射型固体摄像装置 Download PDF

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CN101840924A
CN101840924A CN201010127513A CN201010127513A CN101840924A CN 101840924 A CN101840924 A CN 101840924A CN 201010127513 A CN201010127513 A CN 201010127513A CN 201010127513 A CN201010127513 A CN 201010127513A CN 101840924 A CN101840924 A CN 101840924A
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interarea
semiconductor substrate
electrode
wiring
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CN101840924B (zh
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萩原健一郎
井上郁子
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Toshiba Corp
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Abstract

一种半导体装置及背面照射型固体摄像装置，该背面照射型固体摄像装置具有第一主面及与该第一主面对置的第二主面的半导体基板，在其第一区域形成像素部，在其第二区域形成模拟电路部，在其第三区域形成数字电路部。在半导体基板的至少第二区域的第一及第二主面上分别形成布线。将第二区域的第一及第二主面上分别形成的布线彼此电连接的贯通电极，以贯通第一及第二主面的两面的方式形成于半导体基板。包围贯通电极的保护环布线贯通第二区域的第一及第二主面的两面而形成于半导体基板。

Description

半导体装置及背面照射型固体摄像装置
本申请基于并享受2009年5月18日提交的在先日本专利申请No.2009-66637，其全部内容援引入本发明。
技术领域
本发明涉及以贯通半导体基板内外两面的方式设置布线的半导体装置及背面照射型固体摄像装置。
背景技术
随着各种各样的电子器材，例如便携电话等器材的小型化不断推进，对这些器材使用的半导体装置要求小型化的市场需求也不断增强。过去作为分开的半导体芯片的模拟类电路和高速信号处理类电路(主要是数字电路)正在被集成在同一个半导体芯片上。随着这样的电路的单芯片化产生了各种问题。例如，CMOS图像传感器中，模拟电路部和数字电路部混杂存在，由于半导体芯片的小型化，两个电路部之间的噪声问题变得更加显著。为此，过去通过钻研半导体基板的阱结构而寻求两电路部之间的噪声对策。即，作为半导体基板采用高浓度P型基板(P+型基板)，通过在P+型基板上的P型阱中形成模拟电路部，充分进行经由P+型基板的对模拟电路部的接地。并且，数字电路部通过在P+型基板和P型阱之间夹住N型外延层而分离的方式寻求噪声对策。
此外，CMOS图像传感器等固体摄像装置中，随着芯片尺寸的小型化，即像素的窄间距化，为了确保向光电二极管的入射光量，考虑向优选的背面照射型的类型过渡。现有的背面照射型固体摄像装置是指具有如下结构的装置，即、来自被拍摄体的入射光照射到形成有晶体管等电路元件的半导体基板的表面的相反面，也就是半导体基板的背面。背面照射型固体摄像装置中，作为光照射面的半导体基板的背面以朝上的方式安装。所以，需要在半导体基板的背面一侧形成外部端子及产品测试用端子。于是，以贯通基板内外两面的方式形成贯通电极，通过该贯通电极，形成于基板表面一侧的布线及电极电连接到背面一侧的外部端子及产品测试用端子上。这里使用的贯通电极的形成方法一般是，例如，对半导体基板(硅基板等)进行蚀刻并形成绝缘膜之后埋入导体，然后对硅进行研磨等使其薄膜化，从而形成贯通电极。使半导体基板的厚度尽量薄，才能够容易地形成贯通电极，这一点无论对于哪一种贯通电极的形成方法都是显而易见的。此外，背面照射型CMOS图像传感器中，从确保光电二级管的入射光量及防止光的混色的观点来看，也需要使半导体基板的厚度薄。如上所述，固体摄像装置通过采用P+型基板作为半导体基板，能够充分进行经由基板向模拟电路部的P型阱的接地。但是，作薄基板会增大基板电阻，使接地不充分，从而容易受到噪声的影响。
日本特开2004-146816号公报(图3(b))中，公开了在摄像芯片中设置Si贯通电极并引出到底面，并设置凸点(bump)将摄像芯片与图像处理芯片相连接的装置。此外，日本特开2008-205256号公报中公开了在拍摄区域的周围部的表面一侧，通过设置正电压被偏压的n阱，能够实现将拍摄区域周围部产生的无用电荷迅速清除的背面照射型固体摄像元件。
发明内容
根据本发明的第一观点，提供了一种背面照射型固体摄像装置，包括：半导体基板，具有第一主面及与该第一主面对置的第二主面，在上述半导体基板的第一区域形成像素部，在其第二区域形成模拟电路部，在其第三区域形成数字电路部；布线，分别形成在上述半导体基板的至少上述第二区域的上述第一及第二主面上；至少一个贯通电极，以贯通上述第一及第二主面的两面的方式形成于上述半导体基板，并与分别形成在上述第二区域的上述第一及第二主面上的上述布线彼此电连接；以及保护环布线，贯通上述第二区域的上述第一及第二主面的两面而形成于上述半导体基板，并包围上述至少一个贯通电极。
根据本发明的第二观点，提供了一种半导体装置，包括：半导体基板，具有第一主面及与该第一主面对置的第二主面，并形成有集成电路；布线及/或电极，分别形成在上述第一及第二主面上；贯通电极，贯通上述第一及第二主面的两面而形成于上述半导体基板，并将分别形成在上述第一及第二主面上的布线及/或电极彼此电连接；以及保护环布线，贯通上述第一及第二主面的两面而形成于上述半导体基板，并包围上述贯通电极。
根据本发明的第三观点，提供了一种半导体装置，包括：半导体基板，具有第一主面及与该第一主面对置的第二主面，并形成有包含多个电路块的集成电路；以及保护环布线，贯通上述第一及第二主面的两面而形成于上述半导体基板，并包围上述集成电路的任意的电路块。
附图说明
图1是表示第1实施例中的背面照射型CMOS图像传感器的概略结构的剖面图。
图2是图1所示的贯通电极及保护环布线的俯视图。
图3是表示图1所示的CMOS图像传感器的一个部分的剖面图。
图4A～图4E是表示图3所示的CMOS图像传感器的制造工序的剖面图。
图5是表示第2实施例中的半导体装置的结构的俯视图。
图6是表示第3实施例中的半导体装置的俯视图。
具体实施方式
以下，参照附图并通过各种实施例说明本发明。另外，对各附图中对应部位标注相同的符号进行说明。
(第1实施例)
图1是表示将本发明实施到背面照射型CMOS图像传感器的情况下的概略结构的剖面图。该CMOS图像传感器采用在高浓度P型基板11上形成N型外延层12的结构作为半导体基板13。在半导体基板13的第一区域中形成像素部21，在第二区域中形成模拟电路部31，在第三区域中形成数字电路部41。为确保向形成于像素部21的后述光电二极管的入射光量、防止光的混色、以及形成贯通电极，需要对半导体基板13进行薄膜化，例如直径为8英寸的硅基板的情况下，使其厚度从最初的720μm达到5μm左右。在半导体基板13的背面一侧(第2主面侧)形成有保护膜及布线、外部端子、和测试端子，在像素部21的背面形成有滤色器用颜料及保护膜、微透镜等。
像素部21中，在N型外延层12的表面区域形成N型区域，在该N型领域内形成由光电二极管及光电二极管选择用晶体管等构成的多个像素。另外，像素部21中，形成从基板表面(与第2主面对置的第1主面)到达高浓度P型基板11的深的P型阱区域22。
模拟电路部31中，全面形成从基板表面到达高浓度P型基板11的深的P型阱区域32。此外，P型阱区域32的表面区域内，互相分离地形成多个N型阱区域33。而且，P型阱区域32内形成有多个N沟道MOS晶体管，N型阱区域33内形成有多个P沟道MOS晶体管。
数字电路部41中，N型外延层12的表面区域内分别形成有多个P型阱区域42及N阱区域43。而且，各P型阱区域42内形成有多个N沟道MOS晶体管，各N阱区域43内形成有多个P沟道MOS晶体管。
背面照射型CMOS图像传感器中，来自被拍摄体的入射光，并不照射到像素部21的N型外延层12的表面(半导体基板13的表面)一侧，而是照射到高浓度P型基板11的露出面(半导体基板13的背面)一侧。因此，模拟电路部31及数字电路部41中，需要将在半导体基板13的表面一侧及背面一侧分别形成的多个布线及/或电极彼此相互连接，而在半导体基板13的背面一侧形成外部端子及产品测试用端子。为此，在模拟电路部31及数字电路部41中以贯通半导体基板13的内外两面的方式形成贯通电极34，该贯通电极34将形成于半导体基板13的表面一侧的布线及/或电极和形成于半导体基板13的背面一侧的布线及/或电极彼此之间电连接，并将模拟电路部31及数字电路部41的内部布线及基板表面一侧的产品测试用端子和形成于半导体基板13的背面一侧的布线及/或电极彼此之间电连接。该贯通电极34理所当然是将高浓度P型基板11及P型阱区域32绝缘分离的。
将半导体基板13薄膜化之前，由于高浓度P型基板11连接到接地电位，所以能够经由P型阱区域32对模拟电路部31给予接地电位。但是，为了确保向光电二极管的入射光量、防止光的混色、以及形成贯通电极34，需要将半导体基板13薄膜化，使得高浓度P型基板11的厚度比以往薄。因此，对模拟电路部31的接地状态变得不稳定，使得模拟电路部31容易受到来自贯通电极34及其他电路的噪声影响。
于是，如图2的俯视图所示，本实施例的CMOS图像传感器中，形成有贯通半导体基板13的内外两面并包围贯通电极34的保护环布线51。该保护环布线51与半导体基板13绝缘并分离，并且连接到接地电位。如图2所示，图1表示的贯通电极34被分为多个(本例为9个)贯通电极而形成。各贯通电极34的周围形成有绝缘层35，保护环布线51的周围也形成有绝缘层52。此外，也可以对每个贯通电极分别形成保护环布线。
图3是一个剖面图，将图2所示的贯通电极的剖面结构和像素部21的一部分一同作了详细的表示。像素部21中，在半导体基板13的背面上形成有反射防止膜23，在反射防止膜23上形成有用于颜色分离的滤色器24。进而在滤色器24上形成有用于光聚光的微透镜25。
模拟电路部31中，以贯通半导体基板13内外两面的方式形成有多个贯通电极34。这些贯通电极34与形成于半导体基板13的背面上的外部布线36电连接。该外部布线36例如为焊盘(外部电极)。对焊盘36连接有金属线37。在半导体基板13内，以贯通半导体基板13内外两面的方式形成有保护环布线51。保护环布线51包围多个贯通电极34。保护环布线51通过形成于半导体基板13表面一侧的层间绝缘膜14内的多层结构的布线15，连接到接地电位。另外，本例中通过布线15将保护环布线51接地，但也可以在背面一侧形成外部布线36之外的布线而接地。还有，贯通电极34通过形成于层间绝缘膜14内的多层结构的布线16，与形成于半导体基板13表面一侧的其他布线电连接。另外，由于基板13被薄膜化，所以层间绝缘膜14粘贴有保持用的支持基板17。此外，半导体基板13的第一区域的厚度、第二区域的厚度、以及第三区域的厚度全部相同。
按这种方式构成的CMOS图像传感器中，形成包围多个贯通电极34的保护环布线51，保护环布线51连接到接地电位。这样，能够降低来自贯通电极34的噪声影响。
此外，本实施例中说明了贯通电极34在半导体基板13内分为多个部分而形成的情况，但并不一定要分为多个部分而形成，也可以作为一个部分而形成。但是，在如图3所示，在与外部端子36连接的情况下，为确保足够的电流容量，分为多个部分而形成是有效的方法。另外，本例中还说明了将保护环布线51连接到接地电位的情况，但也可以连接到接地以外的任意电压，或者也可以不连接到任何电位、电压上而使之处于电浮置状态。
接下来说明图3所示的CMOS图像传感器的制造方法。首先，如图4A所示，从半导体基板13的背面开始以不到达表面的深度形成多个第1孔111和包围该多个孔111的第2孔112，然后，以不填满第1孔111及第2孔112的每个的厚度在整个面上沉积绝缘膜，例如沉积硅氧化膜113，接着，以填埋第1孔111及第2孔112的每个的厚度在整个面上形成导电体膜114，该导电体膜例如由金属及多晶硅等构成。接下来，如图4B所示，通过CMP(化学机械研磨法：Chemical Mechanical Polishing)或RIE(反应离子蚀刻：Reactive lon Etching)等方法，去除导电体膜114及硅氧化膜113，使基板13的表面露出。
接着，在半导体基板13的背面形成含有晶体管、光电二极管的像素之后，如图4C所示，通过层间绝缘膜14及导电体材料的沉积、以及导电体材料的图案形成(patterning)，形成与第1孔111内残留的导电体膜114电连接的多层结构的布线16、和与第2孔112内残留的导电体膜114电连接的多层结构的布线15。接下来，如图4D所示，对层间绝缘膜14的表面做等离子体处理后，通过利用同极键联的粘贴技术，将例如硅支持基板115粘贴到层间绝缘膜14上。
接下来，从背面开始研磨半导体基板13，到图4D中的虚线116所示的部分为止，进行半导体基板13的薄膜化。通过该研磨，如图4E所示，第1孔111内残留的导电体膜114及第2孔112内残留的导电体膜114各自的表面分别露出，通过第1孔111内残留的导电体膜114形成贯通电极34，并且，形成通过第2孔112内残留的导电体膜114包围贯通电极34的保护环布线51。之后，如图3所示，像素部21中，在半导体基板13背面上形成反射防止膜23，并在该反射防止膜23上形成用于颜色分离的滤色器24，进而在滤色器24上形成用于光聚光的微透镜25。另一方面，模拟电路部31中，在半导体基板13背面上形成焊盘36，对焊盘36连接金属线37。
(第2实施例)
图5是表示有关第2实施例的半导体装置的结构的俯视图。和第1实施例的情况相同，该半导体实施装置是将本发明实施到在半导体基板上集成了像素部21、模拟电路部31以及数字电路部41的CMOS图像传感器的装置。本实施例的CMOS图像传感器的装置中，以包围模拟电路部31的形状，并且以贯通半导体基板的内外两面的方式形成有保护环布线61。保护环布线61与半导体基板13绝缘并分离，连接到接地电位。
像这样通过用保护环布线61包围模拟电路部31整体，可以防止模拟电路部31产生的噪声漏出到外部，并且可以防止外部产生的噪声混入模拟电路部31。结果，采用保护环布线61能够降低噪声影响。
本例也是对保护环布线61连接到接地电位的情况进行了说明，但也可以把保护环布线61连接到接地以外的任意电压，或不连接到任何电位、电压上，而使之处于电浮置状态。
(第3实施例)
在形成半导体装置，特别是形成像集成电路的I/O电路(输入输出电路)等这样的尺寸相对较大的晶体管的内部电路中，随着晶体管的切换会产生大的噪声。因此，如俯视图图6所示，有关第3实施例的半导体装置中，以包围形成于半导体基板的集成电路的I/O电路71的形状，并且以贯通半导体基板的内外两面(内表两面)的方式形成保护环布线81。保护环布线81和半导体基板绝缘并分离，连接到接地电位。另外，这种情况下，电连接到I/O电路71上并进行信号输入输出的多个电极盘91也被保护环布线81所包围。
本实施例中，通过保护环布线81的包围，可以防止I/O电路71产生的噪声漏出到外部。结果，通过采用保护环布线81能够降低噪声影响。
本例也是对保护环布线81连接到接地电位的情况进行了说明，但也可以把保护环布线81连接到接地以外的任意电压，或不连接到任何电位、电压上，而使之处于电浮置状态。
本发明的其他优点及变形应为本领域技术人员容易想到的。因此，本发明不仅限于上述实施方式中记载的内容。在不脱离本发明主旨的范围内可以进行多种变形及组合。

Claims (19)

1.一种背面照射型固体摄像装置，其特征在于，包括：
半导体基板，具有第一主面及与该第一主面对置的第二主面，在上述半导体基板的第一区域形成像素部，在第二区域形成模拟电路部，在第三区域形成数字电路部；
布线，分别形成在上述半导体基板的至少上述第二区域的上述第一及第二主面上；
至少一个贯通电极，以贯通上述第一及第二主面的两面的方式形成于上述半导体基板，并将分别形成在上述第二区域的上述第一及第二主面上的上述布线彼此电连接；以及
保护环布线，贯通上述第二区域的上述第一及第二主面的两面而形成于上述半导体基板，并包围上述至少一个贯通电极。
2.如权利要求1所述的背面照射型固体摄像装置，其特征在于，在上述第一区域的上述第二主面上形成有多个微透镜。
3.如权利要求1所述的背面照射型固体摄像装置，其特征在于，上述至少一个贯通电极形成于上述半导体基板的上述第二区域。
4.如权利要求1所述的背面照射型固体摄像装置，其特征在于，上述至少一个贯通电极是多个贯通电极。
5.如权利要求1所述的背面照射型固体摄像装置，其特征在于，在上述保护环布线上施加任意的电位，该电位包括接地电位。
6.如权利要求1所述的背面照射型固体摄像装置，其特征在于，上述保护环布线处于电浮置状态。
7.如权利要求1所述的背面照射型固体摄像装置，其特征在于，上述半导体基板的上述第一区域的厚度与上述半导体基板的上述第二区域的厚度相等。
8.如权利要求1所述的背面照射型固体摄像装置，其特征在于，上述第二区域的上述第二主面上形成的上述布线是焊盘。
9.一种背面照射型固体摄像装置的制造方法，其特征在于，
在具有第一主面及与该第一主面对置的第二主面的半导体基板上，从上述第一主面以未达到上述第二主面的深度形成至少一个第一孔、及包围上述至少一个第一孔的第二孔；
以不填埋上述至少一个第一孔及上述第二孔各自的厚度在整个面上堆积第一绝缘膜；
以填埋上述至少一个第一孔及上述第二孔各自的厚度在整个面上形成导电体膜；
蚀刻上述导电体膜及上述第一绝缘膜而使上述第一主面露出；
在上述第一主面上，形成与上述至少一个第一孔内残留的上述导电体膜电连接的第一布线、及与上述第二孔内残留的上述导电体膜电连接的第二布线；
从上述第二主面研磨上述半导体基板，使上述至少一个第一孔内残留的上述导电体膜及上述第二孔内残留的上述导电体膜各自的表面露出，通过上述至少一个第一孔内残留的上述导电体膜形成至少一个贯通电极，并且，通过上述第二孔内残留的上述导电体膜形成包围上述至少一个贯通电极的保护环布线。
10.如权利要求9所述的背面照射型固体摄像装置的制造方法，其特征在于，上述至少一个第一孔为多个第一孔。
11.如权利要求10所述的背面照射型固体摄像装置的制造方法，其特征在于，在上述第二主面上形成与上述至少一个贯通电极电连接的第三布线。
12.一种半导体装置，其特征在于，包括：
半导体基板，具有第一主面及与该第一主面对置的第二主面，并形成有集成电路；
布线及/或电极，分别形成在上述第一及第二主面上；
贯通电极，贯通上述第一及第二主面的两面而形成于上述半导体基板，并将分别形成在上述第一及第二主面上的布线及/或电极彼此电连接；以及
保护环布线，贯通上述第一及第二主面的两面而形成于上述半导体基板，并包围上述贯通电极。
13.如权利要求12所述的半导体装置，其特征在于，在上述保护环布线上施加任意的电位，该电位包括接地电位。
14.如权利要求12所述的半导体装置，其特征在于，上述保护环布线处于电浮置状态。
15.一种半导体装置，其特征在于，包括：
半导体基板，具有第一主面及与该第一主面对置的第二主面，并形成有包含多个电路块的集成电路；以及
保护环布线，贯通上述第一及第二主面的两面而形成于上述半导体基板，并包围上述集成电路的任意的电路块。
16.如权利要求15所述的半导体装置，其特征在于，上述任意的电路块是模拟电路块。
17.如权利要求15所述的半导体装置，其特征在于，上述任意的电路块是I/O电路块。
18.如权利要求15所述的半导体装置，其特征在于，在上述保护环布线上施加任意的电位，上述电位包括接地电位。
19.如权利要求16所述的半导体装置，其特征在于，上述保护环布线处于电浮置状态。
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