TWI425605B - A semiconductor device and a back-illuminated solid-state imaging device - Google Patents

A semiconductor device and a back-illuminated solid-state imaging device Download PDF

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Publication number
TWI425605B
TWI425605B TW099105520A TW99105520A TWI425605B TW I425605 B TWI425605 B TW I425605B TW 099105520 A TW099105520 A TW 099105520A TW 99105520 A TW99105520 A TW 99105520A TW I425605 B TWI425605 B TW I425605B
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Taiwan
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semiconductor substrate
main surface
wiring
region
state imaging
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TW099105520A
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TW201106457A (en
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Kenichiro Hagiwara
Ikuko Inoue
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Toshiba Kk
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Publication of TW201106457A publication Critical patent/TW201106457A/zh
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Description

半導體裝置及背面照射型固體攝影裝置 相關申請案之相互參照
本申請案係根據2009年5月18日提出申請之日本專利申請案(申請案號：2009-66637)主張優先權，並併入該案所有內容。
本發明係以貫通半導體基板的表背雙面的方式設置配線之半導體裝置及背面照射型固體攝影裝置。
種種電子機器，例如行動電話等每一年都在朝向小型化的方向發展，使用於這些機器的半導體裝置在市場上也被強烈要求小型化。從前，原本是分別的半導體晶片之類比系電路與高速訊號處理系電路(主要為數位電路)，被積成於同一半導體晶片上。伴隨著這樣的電路之單一晶片化產生了種種的問題。例如，在CMOS影像感測器，混載著類比電路部與數位電路部，由於半導體晶片的小型化而使兩電路部之間的雜訊問題變得更為顯著。因此，從前，設法在半導體基板的井(well)構造下功夫以找出兩電路部之間的雜訊對策。亦即，作為半導體基板使用高濃度P型基板(P+型基板)，藉由在P+型基板上之P型井形成類比電路部，透過P+型基板充分進行通類比電路部之接地。而且，在數位電路部，於P+型基板與P型井之間夾著N型取向附生(epitaxial)層而分離以謀求雜訊對策。
此外，在CMOS影像感測器等固體攝影裝置，伴隨著晶片尺寸的小型化，亦即伴隨著畫素的窄間距化，為了確保往光電二極體之入射光量考慮轉換為較優的背面照射型之形式。現有的背面照射型固體攝影裝置，係從形成電晶體等電路元件的半導體基板的表面的相反面，亦即從半導體基板的背面照射來自被攝體之入射光的構造。在背面照射型固體攝影裝置，係以光照射面之半導體基板的背面成為朝上的方式被實裝的。因此，有必要於半導體基板的背面側形成外部端子或製品測試用端子。此處，以貫通基板的表背兩面的方式形成貫通電極，透過此貫通電極，被形成於基板的表面側的配線或電極與背面側之外部端子或製品測試用端子導電連接。此處使用的貫通電極，例如係蝕刻半導體基板(矽基板等)形成絕緣膜後埋入導體，其後，進行研磨矽等以進行薄膜化而形成的方法係屬一般。於貫通電極之任何一種形成方法，使半導體基本的厚度儘可能地薄化的方法可以容易地形成是很明顯的。此外，於背面照射型之CMOS影像感測器，由確保射往光電二極體的入射光量以及防止光的混色的觀點來看，有必要使半導體基板的厚度薄化。如先前所述，在固體攝影裝置，藉由使用P+型基板作為半導體基板，經由基板可以往類比電路部之P型井充分進行接地。但是，因為使基板薄化而基板電阻變高，接地變得不充分，而容易受到雜訊的影響。
於日本特開2004-146816號公報(圖3(b))，揭示在攝影晶片設置矽貫通電極而於底面拉出電極，設置凸塊而與影像處理晶片連接者。此外，於日本特開2008-205256號公報，揭示著藉由在攝影區域的周邊部的表面側，設置使正電壓被偏壓之n井，可以迅速掃出在攝影區域周邊部產生的不要電荷之背面照射型固體攝影元件。
根據本發明之第一觀點，提供一種背面照射型固體攝影裝置，其特徵為包含：具有第1主面及與此對向的第2主面，於第1區域形成畫素部，於第2區域形成類比電路部，於第3區域形成數位電路部之半導體基板、於前述半導體基板之至少前述第2區域之前述第1及第2主面上分別被形成之配線、以貫通前述第1及第2主面之兩面的方式被形成於前述半導體基板，電氣導通於前述第2區域之前述第1及第2之主面上分別被形成之前述配線彼此的至少一貫通電極，以及貫通前述第2區域之前述第1及第2主面兩面被形成於前述半導體基板，包圍前述至少一貫通電極的防護環配線。
根據本發明之第二觀點，提供一種半導體裝置，其特徵為包含：具有第1主面及與此對向的第2主面，被形成積體電路的半導體基板、分別被形成於前述第1及第2主面上的配線及/或電極、貫通前述第1及第2主面之兩面而被形成於前述半導體基板，導電連接於分別被形成於前述第1及第2主面上的配線及/或電極彼此之貫通電極、以及貫通前述第1及第2主面之兩面被形成於前述半導體基板，包圍前述貫通電極的防護環配線。
根據本發明之第三觀點，提供一種半導體裝置，其特徵為包含：具有第1主面及與此對向之第2主面，被形成包含複數電路區塊的積體電路之半導體基板，及貫通前述第1及第2主面之兩面被形成於前述半導體基板，包圍前述積體電路之任意電路區塊的防護環配線。
以下，參照圖面藉由種種實施例說明本發明。又，於各圖，對應之處所賦予相同符號而進行說明。
(第1實施例)
圖1係於背面照射型CMOS影像感測器實施本發明的場合的概略構成之剖面圖。此CMOS影像感測器，作為半導體基板13，使用在高濃度P型基板11上形成N型取向附生層12者。於半導體基板13之第1區域被形成畫素部21，於第2區域被形成類比電路部31，於第3區域被形成數位電路部41。為了防止被形成於畫素部21的後述之光電二極體之入射光量、防止光的混色、及形成貫通電極，半導體基板13例如為直徑8英吋的矽基板的場合，係將最初的720μm之厚度薄膜化至5μm程度。於半導體基板13之背面側(第2主面側)，被形成保護膜或配線、外部端紫、測試端子，於畫素部21之背面，被形成彩色濾光片用之顏料或保護膜、微透鏡等。
在畫素部21，於N型取向附生層12的表面區域被形成N型區域，於此N型區域內被形成由光電二極體與光電二極體選擇用之電晶體等所構成之複數之畫素。進而，在畫素部21，被形成由基板表面(與第2主面對向之第1主面)起達到高濃度P型基板11的深度之P型井區域22。
在類比電路部31，於全面形成由基板表面達到高濃度P型基板11的深度之P型井區域32。此外，於P型井區域32的表面區域內，複數之N型井區域33相互分離地被形成。接著，於P型井區域32內被形成複數之N通道MOS電晶體，N型井區域33內被形成複數之P通道MOS電晶體。
在數位電路部41，於N型取向附生層12的表面區域內分別被形成複數之P型井區域42以及N型井區域43。接著，於各P型井區域42內被形成複數之N通道MOS電晶體，於各N型井區域43內被形成複數之P通道MOS電晶體。
在背面照射型CMOS影像感測器，來自被攝體之入射光，不在畫素部21之N型取向附生層12的表面(半導體基板13的表面)側，而是被照射於高濃度P型基板11的路出面(半導體基板13之背面)側。在此，在類比電路部31或數位電路部41，有必要使在半導體基板13的表面側及背面側分別被形成的複數配線及/或電極彼此相互連接，於半導體基板13之背面側形成外部端子或製品測試用端子。因此，於類比電路部31或數位電路部41，以貫通半導體基板13的表背兩面的方式被形成，被形成於半導體基板13的表面側的配線及/或電極與被形成在半導體基板13的背面側的配線及/或電極彼此之間，被形成導電連接類比電路部31及數位電路部41的內部的配線或基板表面側的製品測試用端子與被形成於半導體基板13的背面側之配線及/或電極彼此間之貫通電極34。此貫通電極34，當然與高濃度P型基板11及P型井區域32係絕緣分離的。
要薄膜化半導體基板13之前，高濃度P型基板11被連接於接地電位，所以對於類比電路部31可以經由P型井區域32提供接地電位。但是，為了確保對光電二極體之入射光量、防止光的混色以及貫通電極34的形成而使半導體基板13薄膜化，高濃度P型基板11的厚度變得比從前更薄。因此，對類比電路部31之接地狀態變得不安定，類比電路部31變得容易受到來自貫通電極34以及其他電路的雜訊的影響。
此處，在本實施例之CMOS影像感測器，如圖2之平面圖所示，以形成貫通半導體基板13的表背兩面且包圍貫通電極34的方式形成防護環配線51。防護環配線51，與半導體基板13係絕緣分離，被連接於接地電位。如圖2所示，圖1中所示之貫通電極34係被分為複數(在本例為9個)貫通電極而被形成的。各貫通電極34的周圍被形成絕緣層35，防護環配線51的周圍也被形成絕緣層52。又，分別對1個個貫通電極形成防護環配線亦可。
圖3係與畫素部21之一部分一起詳細顯示圖2所示之貫通電極的剖面構造之剖面圖。在畫素部21，於半導體基板13的背面上被形成防止反射膜23，於防止反射膜23上被形成色分離用之彩色濾光片24。進而於彩色濾光片24上，被形成聚光用之微透鏡25。
在類比電路部31，以貫通半導體基板13的表背兩面的方式被形成複數之貫通電極34。這些複數之貫通電極34，被導電連接於形成在半導體基板13的背面上之外部配線36。此外部配線36例如係結合片(bonding pad,外部電極)。對結合片36連接金屬電線37。於半導體基板13內，以貫通半導體基板13的表背兩面的方式被形成防護環配線51。防護環配線51包圍複數之貫通電極34。防護環配線51，透過被形成於半導體基板13的表面側的層間絕緣膜14內的多層構造之配線15被連接於接地電位。又，在本例係透過配線15使防護環配線51接地，亦可除外部配線36以外地將其他配線形成於背面側而接地。進而，貫通電極34，透過被形成於層間絕緣膜14內的多層構造之配線16，與被形成於半導體基板13的表面側之其他配線導電連接。又，基板13被薄膜化，所以於層間絕緣膜14被貼附保持用之支撐基板17。此外，半導體基板13之第1區域的厚度、第2區域的厚度、及第3區域的厚度全部相等。
如此般構成的CMOS影像感測器，係以包圍複數貫通電極34的方式被形成防護環配線51，防護環配線51被連接於接地電位。因此，可以減低來自貫通電極34的雜訊的影響。
又，在本實施例，針對貫通電極34係在半導體基板13內被分為複數部分而被形成的場合加以說明，但沒有必要分為複數部分而形成，亦可形成為1個部分。但是，如圖3所示，與外部端子36連接的場合，為了確保充分的電流容量，以分為複數部分而形成是比較有效的。進而，在本例說明將防護環配線51連接於接地電位的場合，但連接於接地以外的任意電壓亦可，或者是任何電位、電壓都不接而使其處於電位浮動狀態亦可。
其次，說明圖3之CMOS影像感測器之製造方法。首先，如圖4A所示，由半導體基板13的背面，以不達到表面的深度形成複數之第1孔111以及包圍這些複數之第1孔111的第2孔112之後，於全面以不理住第1孔111以及第2孔112之各個的厚度堆積絕緣膜，例如氧化矽膜113，接著於全面以分別埋住第1孔111及第2孔112之各個的厚度形成由金屬或多晶矽等所構成之導電體膜114。接著，如圖4所示，藉由CMP(化學機械研磨)或者RIE(反應性離子蝕刻)等方法，除去導電體膜114以及氧化矽膜113而使基板13的表面露出。
接著，於半導體基板13的背面形成包含電晶體、光電二極體的畫素之後，如圖4C所示，藉由層間絕緣膜14與導電體材料的堆積，以及導電體材料的圖案化，形成包含與殘留在第1孔111內的導電體膜114導電連接的多層構造之配線16以及與殘留在第2孔112內的導電體膜114導電連接之多層構造的配線15之配線。接著，如圖4D所示，電漿處理層間絕緣膜14的表面之後，於層間絕緣膜14上，藉由利用共有結合之貼附技術貼附例如矽支撐基板115。
接著，由背面研磨半導體基板13，進行半導體基板13的薄膜化直到在圖4D中的虛線116所示的部分。藉由此研磨，如圖4E所示，殘留於第1孔111內的導電體膜114以及殘留於第2孔112內的導電體膜114露出分別的表面，藉由殘留於第1孔111內的導電體膜114形成貫通電極34，同時藉由殘留於第2孔112內的導電體膜114形成包圍貫通電極34的防護環配線51。此後，如圖3所示，在畫素部21，於半導體基板13之背面上形成防止反射膜23，於防止反射膜23上形成色分離用之彩色濾光片24，進而於彩色濾光片24上形成聚光用之微透鏡25。另一方面，在類比電路部31，於半導體基板13的背面上被形成結合片(bonding pad,外部電極)36，對結合片36連接金屬電線37。
(第2實施例)
圖5係相關於第2實施例之半導體裝置的構成之平面圖。此半導體裝置，與第1實施例的場合同樣，係於半導體基板被集積畫素部21、類比電路部31、及數位電路部41的CMOS影像感測器實施本發明者。本實施例之CMOS影像感測器，係包圍類比電路部31的形狀且以貫通半導體基板的表背兩面的方式被形成防護環配線61。防護環配線61，與半導體基板係絕緣分離，被連接於接地電位。
如此般，藉由把類比電路部31全體以防護環配線61包圍，可以防止在類比電路部31產生的雜訊往外部漏出，而且可以防止在外部產生的雜訊混入類比電路部31。結果，使用防護環配線61可以減低雜訊的影響。
在本例，說明將防護環配線61連接於接地電位的場合，但連接於接地以外的任意電壓亦可，或者是任何電位、電壓都不接而使其處於電位浮動狀態亦可。
(第3實施例)
在半導體裝置，特別是積體電路的I/O電路(輸出入電路)之類被形成尺寸比較大的電晶體的內部電路，伴隨著電晶體的切換會產生大的雜訊。此處，在相關於第3實施例之半導體裝置，如圖6之平面圖所示，以包圍被形成於半導體基板的積體電路的I/O電路71的形狀且貫通半導體基板的表背兩面的方式形成防護環配線81。防護環配線81，與半導體基板係絕緣分離，被連接於接地電位。又，在此場合，被導電連接於I/O電路71，進行訊號的輸出入的複數電極墊91也藉由防護環配線81而被包圍。
在本實施例藉由防護環配線81包圍，可以防止在I/O電路71產生的雜訊漏出至外部。結果，使用防護環配線81可以減低雜訊的影響。
在本例，說明將防護環配線81連接於接地電位的場合，但連接於接地以外的任意電壓亦可，或者是任何電位、電壓都不接而使其處於電位浮動狀態亦可。
熟悉該項技藝者將可容易想到額外的優點以及修改，因此本發明之範圍不以此處所展現及說明之具體細節與代表性的實施例為限。在不偏離本發明的概念下，所有申請專利範圍、其附屬項以及均等物所涵蓋的各種修改，也都包含於本發明之範圍。
13‧‧‧半導體基板
21‧‧‧畫素部
23‧‧‧防止反射膜
24‧‧‧彩色濾光片
25‧‧‧微透鏡
圖1係顯示根據第1實施例之背面照射型CMOS影像感測器的概略構成之剖面圖。
圖2係顯示圖1中的貫通電極及防護環配線之平面圖。
圖3係抽出圖1之CMOS影像感測器的一部份而顯示之剖面圖。
圖4A~圖4E係顯示圖3之CMOS影像感測器的製造步驟之剖面圖。
圖5係根據第2實施例之半導體裝置的構成之平面圖。
圖6係根據第3實施例之半導體裝置的平面圖。
13．．．半導體基板
14．．．層間絕緣膜
15、16．．．配線
17．．．支撐基板
21．．．畫素部
23．．．防止反射膜
24．．．彩色濾光片
25．．．微透鏡
31．．．類比電路部
34．．．貫通電極
36．．．結合片
37．．．金屬電線
51．．．防護環配線

Claims (16)

  1. 一種背面照射型固體攝影裝置，其特徵為包含：具有第1主面及與此對向的第2主面，於第1區域形成畫素部，於第2區域形成類比電路部，於第3區域形成數位電路部之半導體基板、於前述半導體基板之至少前述第2區域之前述第1及第2主面上分別被形成之配線、以貫通前述第1及第2主面之兩面的方式被形成於前述半導體基板，電氣導通於前述第2區域之前述第1及第2之主面上分別被形成之前述配線彼此的至少一個貫通電極，以及貫通前述第2區域之前述第1及第2主面兩面被形成於前述半導體基板，包圍前述至少一個貫通電極的防護環配線。
  2. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中於前述第1區域之前述第2主面上被形成複數之微透鏡。
  3. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中前述至少一個貫通電極，係被形成於前述半導體基板之前述第2區域。
  4. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中前述至少一個貫通電極，係複數之貫通電極。
  5. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中於前述防護環配線，被施加包含接地電位之任意 電位。
  6. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中前述防護環配線為電位浮動狀態。
  7. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中前述半導體基板之前述第1區域之厚度，等於前述半導體基板之前述第2區域的厚度。
  8. 如申請專利範圍第1項之背面照射型固體攝影裝置，其中被形成於前述第2區域之前述第2主面上的前述配線為結合片(bonding pad)。
  9. 一種背面照射型固體攝影裝置之製造方法，其特徵為包含：於具有第1主面及與此對向的第2主面之半導體基板上，由前述第1主面起以未到達前述第2主面的深度形成至少1個第1孔及圍繞前述至少1個之第1孔的第2孔，於全面以不分別埋住前述至少1個之第1孔及前述第2孔的厚度堆積第1絕緣膜，於全面以分別埋住前述至少1個之前述第1孔及前述第2孔的厚度形成導電體膜，蝕刻前述導電體膜及前述第1絕緣膜使前述第1主面露出，於前述第1主面上，形成與前述至少1個之第1孔內殘留的前述導電體膜導電連接的第1配線及與殘留於前述第2孔內的前述導電體膜導電連接的第2配線，由前述第2主面起研前述半導體基板，使殘留於前述 至少1個之第1孔內的前述導電體膜與殘留於前述第2孔內的前述導電體膜分別的表面露出，藉由殘留於前述至少1個之第1孔內的前述導電體膜形成至少1個貫通電極，同時藉由殘留於前述第2孔內的前述導電體膜形成包圍前述至少1個貫通電極的防護環配線。
  10. 如申請專利範圍第9項之背面照射型固體攝影裝置之製造方法，其中前述至少1個之第1孔係複數之第1孔。
  11. 如申請專利範圍第10項之背面照射型固體攝影裝置之製造方法，其中，進一步包含於前述第2主面上形成與前述至少1個之貫通電極導電連接的第3配線。
  12. 一種半導體裝置，其特徵為包含：具有第1主面及與此對向之第2主面，被形成包含複數電路區塊的積體電路之半導體基板，及貫通前述第1及第2主面之兩面被形成於前述半導體基板，包圍前述積體電路之任意電路區塊的防護環配線。
  13. 如申請專利範圍第12項之半導體裝置，其中前述任意之電路區塊為類比電路區塊。
  14. 如申請專利範圍第12項之半導體裝置，其中前述任意之電路區塊為輸出入(I/O)電路區塊。
  15. 如申請專利範圍第12項之半導體裝置，其中於前述防護環配線，被施加包含接地電位之任意電位。
  16. 如申請專利範圍第13項之半導體裝置，其中前述防護環配線為電位浮動狀態。
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