CN101656253B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101656253B
CN101656253B CN2009101654632A CN200910165463A CN101656253B CN 101656253 B CN101656253 B CN 101656253B CN 2009101654632 A CN2009101654632 A CN 2009101654632A CN 200910165463 A CN200910165463 A CN 200910165463A CN 101656253 B CN101656253 B CN 101656253B
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China
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region
wiring
semiconductor device
outer edge
pmis
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Expired - Fee Related
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CN2009101654632A
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Chinese (zh)
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CN101656253A (zh
Inventor
津田信浩
西卷秀克
大村浩史
吉福裕子
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
CN2009101654632A 2008-08-19 2009-08-18 半导体器件 Expired - Fee Related CN101656253B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2008-210332 2008-08-19
JP2008210332 2008-08-19
JP2008210332 2008-08-19
JP2009026135 2009-02-06
JP2009026135A JP5638760B2 (ja) 2008-08-19 2009-02-06 半導体装置
JP2009-026135 2009-02-06

Publications (2)

Publication Number Publication Date
CN101656253A CN101656253A (zh) 2010-02-24
CN101656253B true CN101656253B (zh) 2013-12-11

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CN2009101654632A Expired - Fee Related CN101656253B (zh) 2008-08-19 2009-08-18 半导体器件

Country Status (4)

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US (3) US8237203B2 (enExample)
JP (1) JP5638760B2 (enExample)
CN (1) CN101656253B (enExample)
TW (1) TWI446198B (enExample)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5292005B2 (ja) * 2008-07-14 2013-09-18 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5944464B2 (ja) * 2008-08-19 2016-07-05 ルネサスエレクトロニクス株式会社 半導体装置
JP5537078B2 (ja) * 2009-07-23 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
CN102124555B (zh) * 2009-10-19 2014-05-14 松下电器产业株式会社 半导体装置
JP5364015B2 (ja) * 2010-03-05 2013-12-11 パナソニック株式会社 半導体装置
JP5581795B2 (ja) * 2010-05-07 2014-09-03 ルネサスエレクトロニクス株式会社 スタンダードセル、スタンダードセルを備えた半導体装置、およびスタンダードセルの配置配線方法
JP2011242541A (ja) * 2010-05-17 2011-12-01 Panasonic Corp 半導体集積回路装置、および標準セルの端子構造
JP2012255704A (ja) * 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置
US8533641B2 (en) * 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
WO2013106799A1 (en) * 2012-01-13 2013-07-18 Tela Innovations, Inc. Circuits with linear finfet structures
JP6010308B2 (ja) * 2012-02-27 2016-10-19 ローム株式会社 半導体集積回路および電子機器
KR101913316B1 (ko) * 2012-06-04 2018-10-31 삼성전자주식회사 디커플링 커패시터 및 더미 트랜지스터를 갖는 반도체 소자
CN104517963B (zh) * 2013-09-27 2018-09-18 恩智浦美国有限公司 状态保持电源选通单元
KR102122458B1 (ko) 2013-11-19 2020-06-12 삼성전자주식회사 반도체 소자의 패턴을 디자인하는 방법
JP6449082B2 (ja) * 2014-08-18 2019-01-09 ルネサスエレクトロニクス株式会社 半導体装置
CN107112280B (zh) * 2014-10-24 2020-08-04 株式会社索思未来 半导体集成电路装置
US9646960B2 (en) 2015-02-26 2017-05-09 Samsung Electronics Co., Ltd. System-on-chip devices and methods of designing a layout therefor
US9710404B2 (en) 2015-03-23 2017-07-18 Intel Corporation Dynamic configuration and peripheral access in a processor
US9825024B2 (en) 2015-09-30 2017-11-21 Samsung Electronics Co., Ltd. Semiconductor device
US9935100B2 (en) * 2015-11-09 2018-04-03 Qualcomm Incorporated Power rail inbound middle of line (MOL) routing
US9871046B2 (en) 2016-02-24 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM circuits with aligned gate electrodes
CN107578986B (zh) * 2016-07-04 2019-11-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法和光刻偏移的测量方法
WO2018025580A1 (ja) 2016-08-01 2018-02-08 株式会社ソシオネクスト 半導体集積回路装置
US11251124B2 (en) 2016-11-29 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Power grid structures and method of forming the same
US10740531B2 (en) 2016-11-29 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system for and method of forming an integrated circuit
US10671547B2 (en) 2016-12-19 2020-06-02 Intel Corporation Lightweight trusted tasks
JP6776192B2 (ja) * 2017-06-28 2020-10-28 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US10692808B2 (en) 2017-09-18 2020-06-23 Qualcomm Incorporated High performance cell design in a technology with high density metal routing
KR102362016B1 (ko) 2017-09-19 2022-02-10 삼성전자주식회사 마스터 슬레이브 플립 플롭
US10559558B2 (en) * 2017-09-29 2020-02-11 Taiwan Semiconductor Manufacturing Co., Ltd. Pin modification for standard cells
DE102018122541A1 (de) 2017-09-29 2019-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Stiftmodifizierung für standardzellen
JP6965721B2 (ja) * 2017-12-18 2021-11-10 富士通株式会社 回路素子及び回路素子の使用方法
WO2019138546A1 (ja) * 2018-01-12 2019-07-18 株式会社ソシオネクスト 半導体集積回路装置
CN119789533A (zh) 2018-04-02 2025-04-08 台湾积体电路制造股份有限公司 半导体装置、其设计方法及包括其的系统
JP7365159B2 (ja) * 2019-08-06 2023-10-19 ローム株式会社 半導体集積回路
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
KR102823081B1 (ko) * 2019-09-09 2025-06-19 삼성전자주식회사 집적된 표준 셀 구조를 포함하는 집적 회로
US11646305B2 (en) * 2019-10-02 2023-05-09 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
CN111244064A (zh) * 2020-01-19 2020-06-05 比特大陆科技有限公司 半导体芯片、半导体装置和数据处理设备
US11342326B2 (en) * 2020-04-28 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned etch in semiconductor devices
US11606084B2 (en) * 2020-05-26 2023-03-14 Taiwan Semiconductor Manufacturing Company Ltd. Oscillation circuit, semiconductor device for oscillation circuit and method for manufacturing the same
JP7446446B2 (ja) * 2021-02-05 2024-03-08 チャンシン メモリー テクノロジーズ インコーポレイテッド スタンダードセルレイアウトテンプレート及び半導体構造
US11798809B2 (en) 2021-06-17 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing
KR20230037103A (ko) * 2021-09-08 2023-03-16 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US20230363132A1 (en) * 2022-05-03 2023-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Varying the po space in semiconductor layouts

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833595B1 (en) * 1999-02-02 2004-12-21 Nec Electronics Corporation Semiconductor device having an improved layout pattern of pair transistors

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02280353A (ja) * 1989-04-20 1990-11-16 Nec Corp 半導体集積回路
JPH0685062A (ja) * 1992-09-04 1994-03-25 Fujitsu Ltd セルベースレイアウト設計方法
JP3281234B2 (ja) * 1995-11-08 2002-05-13 富士通株式会社 半導体集積回路装置及びその製造方法
JP2991147B2 (ja) * 1997-01-30 1999-12-20 日本電気株式会社 スタンダードセルのレイアウト方式
JP2000277620A (ja) 1999-03-29 2000-10-06 Nec Ic Microcomput Syst Ltd 標準セル及びそれを用いた電源配線レイアウト方法
JP2003203993A (ja) * 2002-01-10 2003-07-18 Mitsubishi Electric Corp 半導体記憶装置及びその製造方法
US7053424B2 (en) * 2002-10-31 2006-05-30 Yamaha Corporation Semiconductor integrated circuit device and its manufacture using automatic layout
KR100532464B1 (ko) 2003-08-28 2005-12-01 삼성전자주식회사 액티브를 이용한 반도체 셀의 전원선 레이아웃
JP2005236107A (ja) * 2004-02-20 2005-09-02 Toshiba Corp 上層メタル電源スタンダードセル、面積圧縮装置および回路最適化装置
JP4827422B2 (ja) * 2005-03-10 2011-11-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置の設計方法と装置並びにプログラム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833595B1 (en) * 1999-02-02 2004-12-21 Nec Electronics Corporation Semiconductor device having an improved layout pattern of pair transistors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平6-85062A 1994.03.25

Also Published As

Publication number Publication date
US9035392B2 (en) 2015-05-19
JP2010074125A (ja) 2010-04-02
US20120261723A1 (en) 2012-10-18
US20140239406A1 (en) 2014-08-28
TW201017453A (en) 2010-05-01
US8237203B2 (en) 2012-08-07
CN101656253A (zh) 2010-02-24
TWI446198B (zh) 2014-07-21
JP5638760B2 (ja) 2014-12-10
US8710552B2 (en) 2014-04-29
US20100044755A1 (en) 2010-02-25

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Granted publication date: 20131211

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