CN101647105B - 用于制造半导体器件的方法 - Google Patents

用于制造半导体器件的方法 Download PDF

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Publication number
CN101647105B
CN101647105B CN200880010706.9A CN200880010706A CN101647105B CN 101647105 B CN101647105 B CN 101647105B CN 200880010706 A CN200880010706 A CN 200880010706A CN 101647105 B CN101647105 B CN 101647105B
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layer
dielectric
deposition
space
teos
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Chinese (zh)
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CN101647105A (zh
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奥卢邦米·O·阿德图图
克里斯托弗·B·胡恩德利
保罗·A·因格索尔
克雷格·T·斯维夫特
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6548—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by forming intermediate materials, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
    • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
CN200880010706.9A 2007-04-05 2008-03-12 用于制造半导体器件的方法 Active CN101647105B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/697,106 US8435898B2 (en) 2007-04-05 2007-04-05 First inter-layer dielectric stack for non-volatile memory
US11/697,106 2007-04-05
PCT/US2008/056562 WO2008124240A1 (en) 2007-04-05 2008-03-12 A first inter-layer dielectric stack for non-volatile memory

Publications (2)

Publication Number Publication Date
CN101647105A CN101647105A (zh) 2010-02-10
CN101647105B true CN101647105B (zh) 2012-07-04

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CN200880010706.9A Active CN101647105B (zh) 2007-04-05 2008-03-12 用于制造半导体器件的方法

Country Status (7)

Country Link
US (1) US8435898B2 (https=)
EP (1) EP2135274A4 (https=)
JP (1) JP2010524237A (https=)
KR (1) KR20100014714A (https=)
CN (1) CN101647105B (https=)
TW (1) TWI440088B (https=)
WO (1) WO2008124240A1 (https=)

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JP2010283145A (ja) * 2009-06-04 2010-12-16 Sony Corp 固体撮像素子及びその製造方法、電子機器
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
EP2617771B1 (de) * 2010-01-14 2016-04-06 Basf Se Verfahren zur Herstellung von expandierbaren Polymilchsäure-haltigen Granulaten
US9269634B2 (en) * 2011-05-16 2016-02-23 Globalfoundries Inc. Self-aligned metal gate CMOS with metal base layer and dummy gate structure
US8519482B2 (en) * 2011-09-28 2013-08-27 Globalfoundries Singapore Pte. Ltd. Reliable contacts
US8895441B2 (en) * 2012-02-24 2014-11-25 Lam Research Corporation Methods and materials for anchoring gapfill metals
US9153486B2 (en) * 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
EP2884666B1 (en) * 2013-12-10 2019-01-02 IMEC vzw FPGA device with programmable interconnect in back end of line portion of the device.
KR102125749B1 (ko) 2013-12-27 2020-07-09 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
US9202746B2 (en) * 2013-12-31 2015-12-01 Globalfoundries Singapore Pte. Ltd. Integrated circuits with improved gap fill dielectric and methods for fabricating same
US20150206803A1 (en) * 2014-01-19 2015-07-23 United Microelectronics Corp. Method of forming inter-level dielectric layer
US9378963B2 (en) * 2014-01-21 2016-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact and method of forming the same
CN105097851A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种cmos图像传感器及其制造方法和电子装置
US9378968B2 (en) * 2014-09-02 2016-06-28 United Microelectronics Corporation Method for planarizing semiconductor device
CN106684041B (zh) * 2015-11-10 2020-12-08 联华电子股份有限公司 半导体元件及其制作方法
US9773682B1 (en) 2016-07-05 2017-09-26 United Microelectronics Corp. Method of planarizing substrate surface
KR20250073535A (ko) 2017-08-14 2025-05-27 램 리써치 코포레이션 3차원 수직 nand 워드라인을 위한 금속 충진 프로세스
KR102806630B1 (ko) 2018-05-03 2025-05-12 램 리써치 코포레이션 3d nand 구조체들에 텅스텐 및 다른 금속들을 증착하는 방법
WO2020123987A1 (en) 2018-12-14 2020-06-18 Lam Research Corporation Atomic layer deposition on 3d nand structures
WO2020210260A1 (en) 2019-04-11 2020-10-15 Lam Research Corporation High step coverage tungsten deposition
US12237221B2 (en) 2019-05-22 2025-02-25 Lam Research Corporation Nucleation-free tungsten deposition
WO2021030836A1 (en) 2019-08-12 2021-02-18 Lam Research Corporation Tungsten deposition
CN111490005A (zh) * 2020-05-26 2020-08-04 上海华虹宏力半导体制造有限公司 间隙填充方法、闪存的制作方法及半导体结构

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US5611888A (en) * 1995-09-29 1997-03-18 Lam Research Corporation Plasma etching of semiconductors
US5783482A (en) * 1997-09-12 1998-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method to prevent oxide peeling induced by sog etchback on the wafer edge
US6080639A (en) * 1998-11-25 2000-06-27 Advanced Micro Devices, Inc. Semiconductor device containing P-HDP interdielectric layer
US6191050B1 (en) * 1996-12-19 2001-02-20 Intel Corporation Interlayer dielectric with a composite dielectric stack
CN1372303A (zh) * 2001-02-19 2002-10-02 应用材料有限公司 用于降低氮化物消耗的聚集体介电层

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US6191050B1 (en) * 1996-12-19 2001-02-20 Intel Corporation Interlayer dielectric with a composite dielectric stack
US5783482A (en) * 1997-09-12 1998-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method to prevent oxide peeling induced by sog etchback on the wafer edge
US6080639A (en) * 1998-11-25 2000-06-27 Advanced Micro Devices, Inc. Semiconductor device containing P-HDP interdielectric layer
CN1372303A (zh) * 2001-02-19 2002-10-02 应用材料有限公司 用于降低氮化物消耗的聚集体介电层

Also Published As

Publication number Publication date
EP2135274A1 (en) 2009-12-23
US20080248649A1 (en) 2008-10-09
JP2010524237A (ja) 2010-07-15
CN101647105A (zh) 2010-02-10
TW200849386A (en) 2008-12-16
WO2008124240A1 (en) 2008-10-16
EP2135274A4 (en) 2011-07-27
KR20100014714A (ko) 2010-02-10
TWI440088B (zh) 2014-06-01
US8435898B2 (en) 2013-05-07

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