KR20100014714A - 비휘발성 메모리를 위한 제1 층간 유전체 스택 - Google Patents

비휘발성 메모리를 위한 제1 층간 유전체 스택 Download PDF

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Publication number
KR20100014714A
KR20100014714A KR1020097020504A KR20097020504A KR20100014714A KR 20100014714 A KR20100014714 A KR 20100014714A KR 1020097020504 A KR1020097020504 A KR 1020097020504A KR 20097020504 A KR20097020504 A KR 20097020504A KR 20100014714 A KR20100014714 A KR 20100014714A
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layer
dielectric
gap fill
forming
device components
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Korean (ko)
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올루분미 오. 아데투투
크리스토퍼 비. 헌들레이
폴 에이. 인거솔
크랙 티. 스위프트
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프리스케일 세미컨덕터, 인크.
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Publication of KR20100014714A publication Critical patent/KR20100014714A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6548—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by forming intermediate materials, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
    • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020097020504A 2007-04-05 2008-03-12 비휘발성 메모리를 위한 제1 층간 유전체 스택 Withdrawn KR20100014714A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/697,106 US8435898B2 (en) 2007-04-05 2007-04-05 First inter-layer dielectric stack for non-volatile memory
US11/697,106 2007-04-05

Publications (1)

Publication Number Publication Date
KR20100014714A true KR20100014714A (ko) 2010-02-10

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KR1020097020504A Withdrawn KR20100014714A (ko) 2007-04-05 2008-03-12 비휘발성 메모리를 위한 제1 층간 유전체 스택

Country Status (7)

Country Link
US (1) US8435898B2 (https=)
EP (1) EP2135274A4 (https=)
JP (1) JP2010524237A (https=)
KR (1) KR20100014714A (https=)
CN (1) CN101647105B (https=)
TW (1) TWI440088B (https=)
WO (1) WO2008124240A1 (https=)

Cited By (8)

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Publication number Priority date Publication date Assignee Title
KR20140123456A (ko) * 2013-04-12 2014-10-22 램 리써치 코포레이션 고 체적 제조 애플리케이션들을 위한 ｃｖｄ 기반 금속/반도체 오믹 컨택트
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
US12002679B2 (en) 2019-04-11 2024-06-04 Lam Research Corporation High step coverage tungsten deposition
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition
US12237221B2 (en) 2019-05-22 2025-02-25 Lam Research Corporation Nucleation-free tungsten deposition
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition

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US7579282B2 (en) * 2006-01-13 2009-08-25 Freescale Semiconductor, Inc. Method for removing metal foot during high-k dielectric/metal gate etching
JP2010283145A (ja) * 2009-06-04 2010-12-16 Sony Corp 固体撮像素子及びその製造方法、電子機器
EP2617771B1 (de) * 2010-01-14 2016-04-06 Basf Se Verfahren zur Herstellung von expandierbaren Polymilchsäure-haltigen Granulaten
US9269634B2 (en) * 2011-05-16 2016-02-23 Globalfoundries Inc. Self-aligned metal gate CMOS with metal base layer and dummy gate structure
US8519482B2 (en) * 2011-09-28 2013-08-27 Globalfoundries Singapore Pte. Ltd. Reliable contacts
US8895441B2 (en) * 2012-02-24 2014-11-25 Lam Research Corporation Methods and materials for anchoring gapfill metals
EP2884666B1 (en) * 2013-12-10 2019-01-02 IMEC vzw FPGA device with programmable interconnect in back end of line portion of the device.
KR102125749B1 (ko) 2013-12-27 2020-07-09 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
US9202746B2 (en) * 2013-12-31 2015-12-01 Globalfoundries Singapore Pte. Ltd. Integrated circuits with improved gap fill dielectric and methods for fabricating same
US20150206803A1 (en) * 2014-01-19 2015-07-23 United Microelectronics Corp. Method of forming inter-level dielectric layer
US9378963B2 (en) * 2014-01-21 2016-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact and method of forming the same
CN105097851A (zh) * 2014-05-04 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种cmos图像传感器及其制造方法和电子装置
US9378968B2 (en) * 2014-09-02 2016-06-28 United Microelectronics Corporation Method for planarizing semiconductor device
CN106684041B (zh) * 2015-11-10 2020-12-08 联华电子股份有限公司 半导体元件及其制作方法
US9773682B1 (en) 2016-07-05 2017-09-26 United Microelectronics Corp. Method of planarizing substrate surface
CN111490005A (zh) * 2020-05-26 2020-08-04 上海华虹宏力半导体制造有限公司 间隙填充方法、闪存的制作方法及半导体结构

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR20140123456A (ko) * 2013-04-12 2014-10-22 램 리써치 코포레이션 고 체적 제조 애플리케이션들을 위한 ｃｖｄ 기반 금속/반도체 오믹 컨택트
US11348795B2 (en) 2017-08-14 2022-05-31 Lam Research Corporation Metal fill process for three-dimensional vertical NAND wordline
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
US12002679B2 (en) 2019-04-11 2024-06-04 Lam Research Corporation High step coverage tungsten deposition
US12237221B2 (en) 2019-05-22 2025-02-25 Lam Research Corporation Nucleation-free tungsten deposition
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition

Also Published As

Publication number Publication date
EP2135274A1 (en) 2009-12-23
CN101647105B (zh) 2012-07-04
US20080248649A1 (en) 2008-10-09
JP2010524237A (ja) 2010-07-15
CN101647105A (zh) 2010-02-10
TW200849386A (en) 2008-12-16
WO2008124240A1 (en) 2008-10-16
EP2135274A4 (en) 2011-07-27
TWI440088B (zh) 2014-06-01
US8435898B2 (en) 2013-05-07

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