CN101604682A - 电子器件及其制造方法 - Google Patents

电子器件及其制造方法 Download PDF

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Publication number
CN101604682A
CN101604682A CNA2009101518110A CN200910151811A CN101604682A CN 101604682 A CN101604682 A CN 101604682A CN A2009101518110 A CNA2009101518110 A CN A2009101518110A CN 200910151811 A CN200910151811 A CN 200910151811A CN 101604682 A CN101604682 A CN 101604682A
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China
Prior art keywords
interconnection layer
interconnection
electronic device
resin
layer
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CNA2009101518110A
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CN101604682B (zh
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栗田洋一郎
副岛康志
川野连也
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Renesas Electronics Corp
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NEC Corp
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Abstract

本发明涉及一种电子器件。该电子器件包括第一互连层和第二互连层。该第二互连层配备在该第一互连层的下表面上。该第一互连层包括通路插塞(第一导电插塞)。该第二互连层一侧上的通路插塞的端面小于相对端面。该通路插塞暴露在与该第二互连层相对的第一互连层的表面上。形成该第一互连层的绝缘树脂的热分解温度高于形成该第二互连层的绝缘树脂的热分解温度。

Description

电子器件及其制造方法
本申请是于2007年10月8日提交的、申请人为“恩益禧电子股份有限公司”、名称为“电子器件及其制造方法”且申请号为200710149971.2的专利申请的分案申请。
本申请基于日本专利申请No.2006-271164，其内容通过参考被并入本文。
技术领域
本发明涉及一种电子器件，以及制造该电子器件的方法。
背景技术
迄今为止已经开发出的制造电子器件的方法包括，例如，JP-A-2003-309215中披露的方法。根据其中披露的制造方法，多个互连层顺序地堆叠在支撑衬底上，从而形成多层互连结构，并接着去除该支撑衬底。在通过去除该支撑衬底而暴露出来的多层互连结构的一个表面上形成焊球，以便于起到外部电极端子的作用。在该多层互连结构的另一表面倒装安装电子元件。因此能够得到包括多层互连结构的电子器件，其中该多层互连结构上安装有电子元件。
除了JP-A-2003-309215以外，与本发明相关的现有技术还包括JP-A-S57-7147，JP-A-H09-321408，JP-A-H1 1-126978，以及JP-A-2001-53413。
本发明者已经意识到如下问题。在上面的电子器件中，为了在互连层与电子元件之间实现精细的连接，在构成该多层互连结构的互连层中，采用适于微处理的树脂必须被用于电子元件侧上的互连层。另一方面，对于焊球侧上的互连层，通常不需要采用适于微处理的树脂。因此，从电子器件的制造成本角度来看，期望采用相对便宜的树脂来用于焊球侧上的互连层。
但是，根据JP-A-2003-309215中披露的制造方法，如已经描述的，在支撑衬底上顺序地形成多个互连层，用于形成多层互连结构。这就意味着，在电子元件侧上的互连层之前形成焊球侧的互连层。因此，比用于电子元件侧上的互连层热分解温度更低的树脂不能被用于焊球侧上的互连层。这一限制对于选择要被用于焊球侧上的互连层的树脂来说施加了限制，从而妨碍了降低该电子器件的制造成本。
发明内容
在根据本发明的一个方面中，提供了一种制造电子器件的方法，包括：在支撑衬底上形成第一互连层；去除该支撑衬底；以及在去除该支撑衬底之后，在第一互连层的表面上形成第二互连层，而在该第一互连层上初始地配备了支撑衬底；其中形成该第二互连层的步骤包括在第一互连层中形成第一导电插塞。
根据这样安排的制造方法，在支撑衬底上形成第一互连层，其中将要在该第一互连层上安装电子元件，并且接着在形成该第二互连层之前去除该支撑衬底。这种结构消除了如下限制：无法采用比形成第一互连层更低热分解温度的树脂来形成第二互连层。因此，该方法允许采用适于微处理的树脂来用于第一互连层，同时采用相对较便宜的树脂用于第二互连层。
在根据本发明的第二个方面中，提供了一种电子器件，包括：第一互连层；第二互连层，其配备在该第一互连层上并具有外部电极端子；以及第一导电插塞，其配备在该第一互连层上并且暴露在该第二互连层一侧的第一互连层的表面上；其中形成该第一互连层的树脂的热分解温度高于形成该第二互连层的树脂的热分解温度；以及该第二互连层一侧上的第一导电插塞的端面的面积大于与相对端面的面积。
这样构建的电子器件允许采用比形成第一互连层具有更低热分解温度的树脂来形成第二互连层。因此，可以采用相对便宜的树脂用于该第二互连层，同时采用适于微处理的树脂用于该第一互连层。
这样，本发明提供了一种器件以及制造该电子器件的方法，其中该器件能够在互连层与电子元件之间形成精确连接，尽管成本很低。
附图说明
本发明的上述和其他目标，优点和特征将会通过下面参照附图对某些优选实施例的说明而变得更加清晰，其中：
图1为根据本发明第一实施例的电子器件的剖面图；
图2为用于说明第一互连层与第二互连层之间分界面周围结构的剖面图；
图3A-3E为顺序地显示根据第一实施例的电子器件的制造方法的剖面图；
图4A和4B为顺序地显示根据第一实施例的电子器件的制造方法的剖面图；
图5A和5B为顺序地显示根据第一实施例的电子器件的制造方法的剖面图；
图6A和6B为顺序地显示根据第一实施例的电子器件的制造方法的剖面图；
图7A和7B为顺序地显示根据第一实施例的电子器件的制造方法的剖面图；
图8为根据本发明第二实施例的电子器件的剖面图；
图9A和9B为顺序地显示根据第二实施例的电子器件的制造方法的剖面图；
图10A和10B为顺序地显示根据第二实施例的电子器件的制造方法的剖面图；
图11A和11C为顺序地显示根据第二实施例的电子器件的制造方法的剖面图；
图12A和12B为顺序地显示根据第二实施例的电子器件的制造方法的剖面图；
图13为根据本发明第三实施例的电子器件的剖面图；
图14A和14B为顺序地显示根据第三实施例的电子器件的制造方法的剖面图；
图15为用于说明实施例的变化的剖面图；以及
图16为用于说明实施例的另一个变化的剖面图。
具体实施方式
下面将参照说明性实施例来描述本发明。本领域内的技术人员可以认识到，通过使用本发明的教导可以实现许多替换实施例，并且本发明并不限于仅用于说明目的的实施例。
在下文中，将参照附图来详细地描述根据本发明的电子器件及其制造方法的实施例。在全部附图中，相同的数字来表示相同的部件，并且不会重复对它们的描述。
第一实施例
图1为根据本发明第一实施例的电子器件的剖面图。该电子器件1包括互连层10(第一互连层)以及互连层20(第二互连层)。
该互连层10包括通路插塞12a(第一导电插塞)，通路插塞12b，绝缘树脂14以及导体互连16(第一互连)。在该绝缘树脂14中配备有通路插塞12a，12b。如图1中可以清晰的看到，该通路插塞12a为锥形，它的直径朝着互连层20的方向逐渐增加。因此，该互连层20一侧上的通路插塞12a的端面的面积大于相对端面的面积，即将在后面描述的IC芯片32，36一侧上的端面。相反，该通路插塞12b为锥形，它的直径朝着互连层20的方向逐渐减小。因此，该互连层20一侧上通路插塞12a的端面的面积小于相对端面的面积。该通路插塞12a，12b暴露在与该互连层20相对的互连层10的表面上。
该通路插塞12a的导体可以为例如铜(Cu)，镍(Ni)，金(Au)或银(Ag)。该绝缘树脂14可以由聚酰亚胺树脂、聚苯并噁唑(polybenzoxazole，下文称PBO)树脂，苯并环丁烯(benzocyclobutene，BCB)树脂，芴环树脂(cardo resin，芴环聚合物，cardo polymer)或环氧树脂构成。该聚酰亚胺树脂可以为感光的或者非感光的。在该绝缘树脂14上配备有导体互连16，以便于与通路插塞12a，12b相连。
在该互连层10的上表面(第一表面)上安装有IC芯片32，36(电子元件)。该IC芯片32，36分别通过凸块33，37倒装连接至导体互连16。在该IC芯片32与互连层10之间的间隙中装载有下填充树脂34。同样地，在IC芯片36与互连层10之间的间隙中填充有下填充树脂38。多个IC芯片36被配置为彼此堆叠在一块。该IC芯片32和IC芯片36可以分别为例如CPU和堆叠的存储器。该堆叠的存储器由彼此电连接的三维堆叠的IC芯片(存储器)构成。
该IC芯片32，36上覆盖有互连层10上配备的封装树脂52。更详细地，IC芯片32的侧面以及IC芯片36的侧面和上表面覆盖有封装树脂52。
该互连层10的下表面(第二表面)上配备有互连层20。在平面图中，该互连层20的面积大于互连层10，并且延伸至互连层10的外部区域。换句话说，该互连层20从互连层10向外伸出。
该互连层20包括通路插塞22a(第二导电插塞)，通路插塞22b，以及绝缘树脂24。该通路插塞22a，22b配备在绝缘树脂24中。该通路插塞22a，22b分别与通路插塞12a，12b相连。该通路插塞22a与通路插塞12a整体地形成在一块，使得该通路插塞12a，22a构成了通路插塞12(中间层通路插塞)。换句话说，互连层10中配备的部分通路插塞12对应于通路插塞12a，并且互连层20中配备的部分对应于通路插塞22a。
如图1中可以清晰的看到，该通路插塞22a，22b为锥形，它的直径朝着互连层10的方向逐渐减小。因此，该互连层10一侧上通路插塞22a，22b的端面的面积小于相对的端面上的面积，即将在随后描述的焊球60一侧上的端面的面积。此外，由于如上所述地整体地形成了该通路插塞12a，22a，因此彼此相互接触的通路插塞12a，22a的端面的面积与通路插塞22a，12a的面积相同。如同通路插塞12a，12b，该通路插塞22a，22b的导体可以为例如铜(Cu)，镍(Ni)，金(Au)或银(Ag)。该绝缘树脂24可以由例如环氧树脂构成。由互连层10和互连层20构成的互连结构在电子器件1中起到插入物的作用。
形成该互连层10的绝缘树脂14的热分解温度高于形成互连层20的绝缘树脂24的热分解温度。在采用PBO树脂作为绝缘树脂14的情况下，该热分解温度为例如540℃。在采用环氧树脂作为绝缘树脂24的情况下，该热分解温度为例如310℃。这里的热分解温度是指在该温度下，以每分钟10℃的加热速率用热天平(thermo balance)测得该树脂的重量降低5％。这里，在采用相同类型的树脂(例如环氧树脂)作为绝缘树脂14，24的情况下，前者应该具有比后者更高的热分解温度。
在延伸出该互连层10的互连层20的区域上安装有IC芯片42和无源元件44，作为第二电子元件。该无源元件44可以为电容器，例如去耦电容器。该IC芯片42被封装树脂54覆盖。该无源元件44被树脂56覆盖，其中该树脂56配备在互连层20向外延伸的区域上。该树脂56可以是与封装树脂54相同的树脂，或者不同的树脂。
该互连层20具有多层互连结构，包括在多个层中形成的导体互连26，以及与不同层的导体互连26相连的通路插塞28。该互连层20还配备有与最低层的导体互连26相连的焊球60。该焊球60部分地埋置在阻焊剂62中。该焊球60起到电子器件1的外部连接端的作用。
参看图2，下面将描述互连层10与互连层20之间的分界面周围结构的例子。在该例中，配备有粘接金属层72(第二粘接金属层)，用以覆盖该通路插塞12。换句话说，该粘接金属层72共同地覆盖该通路插塞12a，22a。此外，在与通路插塞12a接触的导体互连16的表面上配备有粘接金属层74(第一粘接金属层)。该粘接金属层72与通路插塞12a上的粘接金属层74接触。因此，该粘接金属层72的一部分被配置为与绝缘树脂14接触，而另一部分与粘接金属层74接触。另外，配备有粘接金属层75，以便于覆盖通路插塞28。在通路插塞28上，该粘接金属层75与导体互连26接触。
优选地，该粘接金属层72，74由含有Ti(例如，Ti，TiN或TiW膜)的膜，或者Cr膜构成。
参看图3A-7B，下面将描述制造该电子器件1的方法，作为根据本发明制造电子器件的方法的第一实施例。在开始详细描述之前，参照图3A-3E来描述该制造方法的概要。首先，如图3A所示，在支撑衬底90上形成互连层10(形成第一互连层的步骤)。该支撑衬底90可以为硅衬底，陶瓷衬底，玻璃衬底或者金属衬底。
接着如图3B所示，将IC芯片32，36安装在互连层10上(安装电子元件的步骤)。如图3C所示，进一步在互连层10上形成封装树脂52，以便于覆盖该IC芯片32，36(形成封装树脂的步骤)。接着，如图3D中所示，去除该支撑衬底90(去除支撑衬底的步骤)。之后，如图3E所示，在互连层10的下表面上形成互连层20(形成第二互连层的步骤)。最后，虽然图中未示出，形成焊球60，从而获得了如图1中所示电子器件1。
现在参看图4A-7B来更详细地描述该制造方法。首先，在支撑衬底90上配备绝缘树脂14，并在该绝缘树脂14中形成通路插塞12b。接着，在该绝缘树脂14上形成导体互连16(图4A)。接着，在该导体互连16上倒装安装IC芯片32，36(图4B)。之后，在该互连层10上配备有封装树脂52，以便覆盖该IC芯片32，36。可以通过例如模塑、印刷或者罐封(potting)来形成封装树脂52(图5A)。接着，去除该支撑衬底90，以便暴露出该通路插塞12b(图5B)。
在该互连层10上初始配备有支撑衬底，而在互连层10的下表面上形成了绝缘树脂24，以便延伸至该互连层10的外部区域。该绝缘树脂24可以由绝缘膜构成。接着，在从该互连层10向外延伸的绝缘树脂24的区域上实现IC芯片42和无源元件44。接着，形成封装树脂54，以便覆盖该IC芯片42(图6A)。另外，还配备了树脂56，用于填充在从该互连层10向外延伸的绝缘树脂24的区域上剩余的间隙。这样，该无源元件44就被树脂56覆盖(图6B)。
接着，形成用于通路插塞12的通孔68a以及用于通路插塞22b的通孔68b。形成该通孔68a，以便不仅穿透该绝缘树脂24而且还穿透该绝缘树脂14(图7A)。接着形成通路插塞12和通路插塞22b，以便填充该通孔68a，68b。这样，在该实施例中，在形成互连层20的过程中，通路插塞12a，22a被形成一体结构的通路插塞12为。
接着，在该绝缘树脂24上形成内嵌(build-up)互连层。该内嵌互连的形成过程的例子包括在例如环氧树脂的绝缘树脂层中通过半加成工艺形成导体互连26以及通过激光工艺形成通路插塞28。通过该工艺，就得到了互连层20(图7B)。之后，通过形成阻焊剂62和焊球60，就能够得到如图1中所示的电子器件1。
从上面的描述中可以理解的是，在每个图中，在从上方形成的通孔中形成通路插塞12b的同时，也在从下方形成的通孔中形成通路插塞12a，22a，22b。因此，如上所述，通路插塞12b在IC芯片32，36一侧具有比相对的一侧更大的端面，以及通路插塞12a，22a，22b在焊球60一侧上具有比相对的一侧更大的端面。
该实施例具备如下有益效果。通过上面的制造方法，在支撑衬底90上形成其上安装有IC芯片32，36的互连层10，并且接着在形成互连层20之前去除该支撑衬底90。这种结构消除了如下限制，即无法采用热分解温度比绝缘树脂14的热分解温度更低的树脂来作为绝缘树脂24。因此，该方法允许采用适于微处理的树脂来作为绝缘树脂14，同时采用相对较便宜的树脂来作为绝缘树脂24。这样，上述实施例提供了一种制造电子器件1的方法，该方法能够实现互连层10与IC芯片32、36之间的精确连接，而成本很低。
除此之外，在形成互连层20而不是互连层10的工艺期间形成将被配置在互连层10中的通路插塞12a。这种结构允许在形成配备在互连层中的导电材料(该实施例中的通路插塞22a，22b)的同时形成通路插塞12a，从而有利于减少了制造步骤的数量。上面的过程还促进了形成通孔。对于该方面，参看图7A以获取更多细节，以很高的位置精度来形成该通孔68b，这是因为该通孔68b必须指向已经配备的通路插塞12b。另一方面，该通孔68a将与导体互连16相连，其中该导体互连的面积大于通路插塞12b，并且因此不需要与通孔68b相同的精确程度。由于上述原因，同时形成通路插塞12a和通路插塞22a有利于形成通孔。
此外，在去除该支撑衬底90时会暴露出该通路插塞12b(参看图5B)。因此，在去除该支撑衬底90之后进行电检查时该通路插塞12b可以被用作端子，其能够在较早的阶段检测到加工中的电子器件中的故障，如果存在的话。这里，并不必须按照这种方式形成通路插塞12b。作为选择，可以在互连层20的形成过程期间形成互连层10中的全部通路插塞。
该互连层20延伸至互连层10的外部区域。该结构允许确保用于配备焊球60(即，互连层20的下表面)的足够的区域，同时保持该互连层10尽可能的小。因此，可以很容易地将该电子器件1安装在另一个电子器件或母板上，而不会导致成本增加。相反，在互连层10和互连层20面积相同的情况下，延伸该互连层20促进安装过程会不可避免地导致互连层10面积的增加。由于采用了适于微处理的相对昂贵的树脂来构成互连层10，因此这就很自然地导致增加电子器件1的制造成本。另一方面，在试图降低成本时降低互连层10的面积就会迫使该互连层20的面积更小，这样就降低了安装便利性。这样，上面实施例就消除了这个矛盾并且同时实现了低成本和安装的便利性。
由于在其上形成有导体互连16的图案的支撑衬底90的刚性结构，因此能够以足够精致的图案形成导体互连16。此外，由于在刚性的支撑衬底90上连接了该互连层10和IC芯片32，36，因此能够通过凸块以精确的间距将互连层10和IC芯片32，36连接在一块。这有助于降低互连层的数量，以及减小IC芯片32，36的尺寸。
进一步，由于在去除该支撑衬底90之后形成互连层20，因此可以形成比绝缘树脂14更厚的绝缘树脂24，用于形成互连层20。因此，该绝缘树脂24获得了更高的应力消除性能，而这导致了该电子器件1更高的可靠性。
在形成第二互连层的步骤中，采用热分解温度比在形成第一互连层10的步骤中采用的、用于形成互连层10的绝缘树脂14的热分解温度更低的树脂作为用于形成互连层20的绝缘树脂24。这种结构允许在互连层10上适当地形成互连层20。
在该电子器件1中，可以采用热分解温度比用于形成互连层10的绝缘树脂14的热分解温度更低的树脂作为用于形成互连层20的绝缘树脂24。因此，可以采用适于微处理的树脂作为绝缘树脂14，同时采用相对便宜的树脂作为绝缘树脂24。这样，该电子器件1能够实现互连层10和IC芯片32，36之间的精确连接，而成本很低。
在该电子器件1中，互连层10和互连层20彼此直接接触，而在它们之间没有配备芯层。一般地，芯层中形成的通路插塞比普通互连层中形成的通路插塞更难微型化(micronize)，因此，配备该芯层就从整体上妨碍了该电子器件的微型化。没有包括该芯层的电子器件1不受这些缺点的影响。
配备了该封装树脂52，以便覆盖该IC芯片32，36。该结构允许在去除支撑衬底90之后保持该互连层的形状。因此，焊球60能够获得很高的共面性。特别是在该实施例中，还在从互连层10向外延伸的互连层20的区域上配备有树脂56，而这就增强了上述效果。
与绝缘衬底相比，采用硅衬底作为支撑衬底90使得热膨胀的效果最小化。因此，该结构进一步促进了互连层10与IC芯片32，36之间连接的微型化。
采用聚酰亚胺树脂，PBO树脂，，BCB树脂，芴环树脂作为绝缘树脂14允许该绝缘树脂14具有适于微处理的属性。采用环氧树脂作为绝缘树脂24允许以很低成本形成绝缘树脂24。
配备了粘接金属层72，以便于覆盖该通路插塞12(参看图2)。该粘接金属层72用于确保通路插塞12与绝缘树脂14，24之间的牢固粘接。此外，在与通路插塞12接触的导体互连16的表面上配备了粘接金属层74(参看图2)。该粘接金属层74也确保了导体互连16与绝缘树脂14之间的牢固粘接。进一步，配备了粘接金属层75，以便于覆盖该通路插塞28(参看图2)。该粘接金属层75确保了通路插塞28与绝缘树脂24之间的牢固粘接。该牢固粘接很自然地导致了提高电子器件1的可靠性。当该粘接金属层72，74，75含有Ti，或者由Cr构成时，该粘接金属层72，74，75能够实现与树脂的显著牢固粘接。
该IC芯片42和无源元件44被安装在从该互连层10向外延伸的互连层20的区域上。该结构能够进一步增强该电子器件1的功能和性能。
第二实施例
图8为根据本发明第二实施例的电子器件的剖面图。该电子器件2包括互连层10(第一互连层)，以及互连层80(第二互连层)。该互连层10具有与参照图1中所述类似的结构，除了不包括通路插塞12b以外。
该互连层80配备在互连层10的下表面上，以便于延伸至该互连层10的外部区域。该互连层80包括阻焊剂84，以及在该阻焊剂84中形成的导体互连86(第二互连)。该导体互连层86与通路插塞12a相连。该导体互连层86与通路插塞12a整体地形成。该阻焊剂84由热分解温度比绝缘树脂14的热分解温度更低的树脂构成。该互连层80包括通路插塞82(第二导电插塞)，其与导体互连层86相连。该通路插塞82对应于部分焊球60，更具体地为埋置在阻焊剂84中的一部分。如图8中可以清晰看到的，该通路插塞82为锥形，并且它的直径朝着互连层10逐步减小。因此，该互连层10一侧上的通路插塞82的端面的面积小于相对的端面的面积。
此外，IC芯片92倒装安装在该互连层10的下表面上。换句话说，该IC芯片92通过凸块93与下表面相连，并且用下填充树脂94来填充该互连层10与IC芯片92之间的间隙。在从互连层10向外延伸的互连层80的区域上配备有树脂56。在该实施例中，该树脂56同时覆盖了该封装树脂52的侧面和顶面。
参看图9A-12B，下面将描述制造该电子器件2的方法，作为根据本发明的制造电子器件的方法的第二实施例。首先，在支撑衬底90上形成绝缘树脂14和导体互连16(图9A)。接着，在导体互连16上倒装安装IC芯片32，36(图9B)。
之后，在互连层10上形成封装树脂52，以便于覆盖该IC芯片32，36(图10A)。接着，去除该支撑衬底90。在该互连层10的下表面上配备有支撑片91，以便于从该互连层10向外延伸(图10B)。
接着，在该互连层10外部的支撑片91的区域上，配备有树脂56以便于覆盖该封装树脂52(图11A)。之后，该支撑片91被剥去(图11B)。接着，形成用于通路插塞12a的通孔69(图11C)，并且形成通路插塞12a和导体互连86，以便于填充该通孔69。这样，在该实施例中，在该互连层80的形成过程中，同时形成了作为一体的导电材料的通路插塞12a和导体互连86。
之后，配备了阻焊剂84，以便于覆盖该导体互连86。对该阻焊剂84进行图案化，以便于形成开口，其中在该开口处将配备焊球60并且将要安装IC芯片92(图12A)。在这一阶段，获得了互连层80。接着，将IC芯片92倒装安装在该互连层10的下表面上(图12B)。之后通过形成焊球60，就能够获得如图8中所示的电子器件2。
除了第一实施例提供的有益效果以外，该实施例还具备如下有益效果。由于该阻焊剂84被用作形成互连层的树脂，因此能够进一步降低该电子器件2的成本。此外，该电子元件(IC芯片92)不仅实现在互连层10的上表面上，而且还实现在它的下表面上。该结构进一步增强了该电子器件2的功能和性能。这里，如图8所示，虽然该凸块93通过导体互连86与通路插塞12a相连，但是该凸块93也可以直接与通路插塞12a相连。
第三实施例
图13为根据本发明第三实施例的电子器件的剖面图。该电子器件3包括互连层10，以及互连层80。该电子器件3与图8中所示的电子器件2的不同之处在于该互连层80具有多层互连结构。在该实施例中，该互连层80包括在互连层10的下表面上配备的绝缘树脂84a，以及在该绝缘树脂84a上配备的阻焊剂84b。
根据该实施例的互连层80包括在多层中配备的导体互连86，以及与该导体互连86相连的通路插塞83(第二导电插塞)。从图13中可以清晰的看到，该通路插塞83为锥形，并且它的直径朝着互连层10逐步减小。因此，该互连层10一侧上的通路插塞83的端面的面积小于相对的端面的面积。该电子器件3其余部分的结构与电子器件2类似。
参看图14A和14B，下面将描述制造该电子器件3的方法，作为根据本发明的制造电子器件的方法的第三实施例。首先，通过参照图9A-11B描述的过程来形成如图11B中所示的结构。
接着，同时形成通路插塞12a和导体互连86的第一层。接着，配备了绝缘树脂84a，以便于覆盖该导体互连86。进一步，在该绝缘树脂84a中形成通路插塞83，以便于与该导体互连86相连。接着，在该绝缘树脂84a中形成导体互连86的第二层，以便于与该通路插塞83相连。之后，配备了阻焊剂84b，以便于覆盖该导体互连86的第二层。
接着，对该阻焊剂84b进行图案化，从而在将要形成焊球60以及要实现IC芯片92的位置上形成开口(图14A)。在该阶段，得到了互连层80。之后，将IC芯片92倒装安装在绝缘树脂84a上(图14B)。之后，通过形成焊球60，就能够得到如图13中所示的电子器件3。该实施例提供了与第二实施例相同的有益效果。这里，如图13所示，虽然该凸块93通过导体互连86与通路插塞83相连，但是该凸块93也可以直接与通路插塞83相连。
根据本发明的电子器件及其制造方法并不仅限于上面的实施例，但是可以进行各种修改。虽然上面的实施例中，为了引用一些例子，采用了IC芯片作为将要安装在互连结构的上表面或下表面上的电子元件的例子，其中该互连结构包括第一和第二互连层，但是该电子元件也可以为无源元件，例如电容器。此外，该电子器件并不是必须包括电子元件。
虽然在根据实施例的电子器件中配备了焊球，但是配备焊球并不是强制性的。在没有配备焊球的情况下，该导体互连的岛部分起到外部电极端的作用。以参看图1中所示的电子器件1为例，该与焊球60接触的部分导体互连26相当于岛部分。
在上面的实施例中，该第二互连层延伸至第一互连层的外部区域。但是该结构不是强制性的，而是该第一和第二互连层可以在平面图上具有相同的面积。
也可以按照各种方式来修改第一和第二互连层之间的分界面周围的结构，而不仅限于图2中所示的结构。例如，在实施例中，该导电材料被载入到整个通孔中，用以形成该通路插塞。但是，该通孔可以部分地填入导电材料。图15描述了如图2中所示的结构，但是其中通过部分地填充相关的通孔来形成通路插塞12，28。这里，虽然用导电材料部分地填充了该通孔，但是该通路插塞端面的面积被规定为被该端面的外部圆周所包围的区域的面积。因此，只要通孔的大小相同，那么端面的面积就是相同的，而与该导电材料是全部还是部分填充该通孔无关。
进一步，如图16所示，可以配备粘接金属层76(第二粘接金属层)，以便于共同地覆盖该通路插塞12a和导体互连86。该粘接金属层76与通路插塞12a上的粘接金属层74接触。这样，该粘接金属层76的整体就与绝缘树脂14或粘接金属层74接触。这样，配备了粘接金属层76就可以确保通路插塞12a与绝缘树脂14之间的牢固粘接。此外，在图16中，配备了粘接金属层73，以便于覆盖该通路插塞83(参看图13)。该粘接金属层73与通路插塞83上的导体互连86接触。这样，配备了粘接金属层76就可以确保通路插塞83与绝缘树脂84a之间的牢固粘接。该粘接金属层73，76可以由与粘接金属层72，74，75中采用的膜类似的膜构成。
很清楚的是，本发明不仅限于上面的实施例，并且可以在不脱离本发明的精神和范畴的情况下进行修改和改变。

Claims (17)

1.一种电子器件，包括：
第一互连层；
第二互连层，其配备在所述第一互连层上并具有外部电极端子；以及
第一导电插塞，其配备在所述第一互连层中，并且暴露在所述第二互连层侧上的所述第一互连层的表面上；
其中形成所述第一互连层的树脂的热分解温度高于形成所述第二互连层的树脂；以及
所述第二互连层侧上的所述第一导电插塞的端面的面积大于相对端面的面积。
2.根据权利要求1的电子器件，还包括：
安装在与所述第二互连层相对的所述第一互连层的表面上的电子元件。
3.根据权利要求2的电子器件，
其中所述电子元件为IC芯片和无源元件中的一个。
4.根据权利要求2的电子器件，还包括：
封装树脂，其配备在所述第一互连层上，以便于覆盖所述电子元件的侧面。
5.根据权利要求1的电子器件，还包括：
第二互连，其配备在所述第二互连层中，并与所述第一导电插塞相连。
6.根据权利要求5的电子器件，还包括：
第二导电插塞，其配备在所述第二互连层中，并与所述第二互连相连。
7.根据权利要求6的电子器件，
其中在所述第一互连层侧上的所述第二导电插塞的端面的面积小于相对端面的面积。
8.根据权利要求1的电子器件，还包括：
第二导电插塞，其配备在所述第二互连层中，并与所述第一导电插塞相连。
9.根据权利要求8的电子器件，
其中所述第一互连层侧上的所述第二导电插塞的端面的面积小于相对端面的面积；以及
彼此接触的所述第一导电插塞的端面和所述第二导电插塞的端面的面积相同。
10.根据权利要求5的电子器件，还包括：
第二粘接金属层，其共同地覆盖所述第一导电插塞以及所述第二互连。
11.根据权利要求10的电子器件，还包括：
第一互连，其配备在所述第一互连层中，并与所述第一导电插塞相连；以及
第一粘接金属层，其配备在与所述第一导电插塞接触的所述第一互连的表面上。
12.根据权利要求11的电子器件，
其中所述第二粘接金属层的整体与形成所述第一互连层的所述树脂以及所述第一粘接金属层的其中之一接触。
13.根据权利要求8的电子器件，还包括：
第二粘接金属层，其共同地覆盖了所述第一以及所述第二导电插塞。
14.根据权利要求13的电子器件，还包括：
第一互连，其配备在所述第一互连层中，并与所述第一导电插塞相连；以及
第一粘接金属层，其配备在与所述第一导电插塞接触的所述第一互连的表面上。
15.根据权利要求14的电子器件，
其中部分所述第二粘接金属层与形成所述第一互连层的树脂以及所述第一粘接金属层中的一个接触。
16.根据权利要求10的电子器件，
其中所述粘接金属层由含有Ti的金属膜以及由Cr构成的金属膜中的一个构成。
17.根据权利要求1的电子器件，
其中形成所述第一互连层的所述树脂是从如下组中选出的一种，其中该组由聚酰亚胺树脂，PBO树脂，，BCB树脂，以及芴环树脂构成；
形成所述第二互连层的所述树脂为环氧树脂。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7579215B2 (en) * 2007-03-30 2009-08-25 Motorola, Inc. Method for fabricating a low cost integrated circuit (IC) package
KR101660430B1 (ko) 2009-08-14 2016-09-27 삼성전자 주식회사 반도체 패키지
JP5372579B2 (ja) * 2009-04-10 2013-12-18 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
WO2011125380A1 (ja) * 2010-04-08 2011-10-13 日本電気株式会社 半導体素子内蔵配線基板
TWI517226B (zh) * 2011-03-31 2016-01-11 索泰克公司 形成包含由一共同底材承載之兩個或以上已處理半導體構造之黏附半導體構造之方法及應用此等方法所形成之半導體構造
US20120248621A1 (en) * 2011-03-31 2012-10-04 S.O.I.Tec Silicon On Insulator Technologies Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US8338294B2 (en) 2011-03-31 2012-12-25 Soitec Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
JP5968736B2 (ja) 2012-09-14 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置
US10418298B2 (en) * 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
KR20150104467A (ko) 2014-03-05 2015-09-15 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI581388B (zh) * 2015-01-30 2017-05-01 力成科技股份有限公司 半導體封裝結構
CN105931997B (zh) * 2015-02-27 2019-02-05 胡迪群 暂时性复合式载板
KR101685849B1 (ko) * 2015-11-04 2016-12-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 모듈 제조 방법 및 이를 이용한 반도체 패키지 모듈
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11139260B2 (en) * 2019-09-17 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Plurality of stacked pillar portions on a semiconductor structure

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577147A (en) 1980-06-17 1982-01-14 Citizen Watch Co Ltd Mounting construction of semiconductor device
JP2842378B2 (ja) 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JPH11126978A (ja) 1997-10-24 1999-05-11 Kyocera Corp 多層配線基板
JP2001053413A (ja) 1999-08-16 2001-02-23 Sony Corp 電子部品内蔵基板および多層電子部品内蔵基板ならびにそれらの製造方法
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
JP2001185653A (ja) * 1999-10-12 2001-07-06 Fujitsu Ltd 半導体装置及び基板の製造方法
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
JP2003051569A (ja) * 2001-08-03 2003-02-21 Seiko Epson Corp 半導体装置及びその製造方法
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
JP3773896B2 (ja) 2002-02-15 2006-05-10 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7579251B2 (en) * 2003-05-15 2009-08-25 Fujitsu Limited Aerosol deposition process
JP2005063987A (ja) * 2003-08-08 2005-03-10 Ngk Spark Plug Co Ltd 配線基板の製造方法、及び配線基板
US6838332B1 (en) * 2003-08-15 2005-01-04 Freescale Semiconductor, Inc. Method for forming a semiconductor device having electrical contact from opposite sides
WO2005029578A1 (en) 2003-09-24 2005-03-31 Koninklijke Philips Electronics N.V. Semiconductor device, method of manufacturing same, identification label and information carrier
JP2005340655A (ja) * 2004-05-28 2005-12-08 Shinko Electric Ind Co Ltd 半導体装置の製造方法および半導体基板の支持構造体
JP2005353837A (ja) * 2004-06-10 2005-12-22 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008532307A (ja) * 2005-03-02 2008-08-14 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体パッケージ及び作成パッケージを製造する方法

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