CN101578694B - 导电性凸块及其形成方法和半导体装置及其制造方法 - Google Patents
导电性凸块及其形成方法和半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN101578694B CN101578694B CN2007800424492A CN200780042449A CN101578694B CN 101578694 B CN101578694 B CN 101578694B CN 2007800424492 A CN2007800424492 A CN 2007800424492A CN 200780042449 A CN200780042449 A CN 200780042449A CN 101578694 B CN101578694 B CN 101578694B
- Authority
- CN
- China
- Prior art keywords
- conductivity
- solidified portion
- projection
- electrode terminal
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 89
- 238000000034 method Methods 0.000 title claims description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 45
- 230000015572 biosynthetic process Effects 0.000 claims description 30
- 239000004973 liquid crystal related substance Substances 0.000 claims description 19
- 238000007639 printing Methods 0.000 claims description 13
- 238000001723 curing Methods 0.000 claims description 11
- 238000000016 photochemical curing Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 238000001029 thermal curing Methods 0.000 claims description 4
- 239000011342 resin composition Substances 0.000 claims 2
- 239000011231 conductive filler Substances 0.000 abstract 1
- 238000009434 installation Methods 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000007787 solid Substances 0.000 description 7
- 239000000178 monomer Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 125000000524 functional group Chemical group 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 125000004386 diacrylate group Chemical group 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- LGPAKRMZNPYPMG-UHFFFAOYSA-N (3-hydroxy-2-prop-2-enoyloxypropyl) prop-2-enoate Chemical compound C=CC(=O)OC(CO)COC(=O)C=C LGPAKRMZNPYPMG-UHFFFAOYSA-N 0.000 description 2
- LEJBBGNFPAFPKQ-UHFFFAOYSA-N 2-(2-prop-2-enoyloxyethoxy)ethyl prop-2-enoate Chemical compound C=CC(=O)OCCOCCOC(=O)C=C LEJBBGNFPAFPKQ-UHFFFAOYSA-N 0.000 description 2
- INQDDHNZXOAFFD-UHFFFAOYSA-N 2-[2-(2-prop-2-enoyloxyethoxy)ethoxy]ethyl prop-2-enoate Chemical compound C=CC(=O)OCCOCCOCCOC(=O)C=C INQDDHNZXOAFFD-UHFFFAOYSA-N 0.000 description 2
- TXBCBTDQIULDIA-UHFFFAOYSA-N 2-[[3-hydroxy-2,2-bis(hydroxymethyl)propoxy]methyl]-2-(hydroxymethyl)propane-1,3-diol Chemical compound OCC(CO)(CO)COCC(CO)(CO)CO TXBCBTDQIULDIA-UHFFFAOYSA-N 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- GZBSIABKXVPBFY-UHFFFAOYSA-N 2,2-bis(hydroxymethyl)propane-1,3-diol;prop-2-enoic acid Chemical compound OC(=O)C=C.OC(=O)C=C.OC(=O)C=C.OC(=O)C=C.OCC(CO)(CO)CO GZBSIABKXVPBFY-UHFFFAOYSA-N 0.000 description 1
- IQQVCMQJDJSRFU-UHFFFAOYSA-N 2-ethyl-2-(hydroxymethyl)propane-1,3-diol;prop-2-enoic acid Chemical compound OC(=O)C=C.OC(=O)C=C.OC(=O)C=C.OC(=O)C=C.CCC(CO)(CO)CO IQQVCMQJDJSRFU-UHFFFAOYSA-N 0.000 description 1
- VFZKVQVQOMDJEG-UHFFFAOYSA-N 2-prop-2-enoyloxypropyl prop-2-enoate Chemical compound C=CC(=O)OC(C)COC(=O)C=C VFZKVQVQOMDJEG-UHFFFAOYSA-N 0.000 description 1
- VNGLVZLEUDIDQH-UHFFFAOYSA-N 4-[2-(4-hydroxyphenyl)propan-2-yl]phenol;2-methyloxirane Chemical compound CC1CO1.C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 VNGLVZLEUDIDQH-UHFFFAOYSA-N 0.000 description 1
- WPSWDCBWMRJJED-UHFFFAOYSA-N 4-[2-(4-hydroxyphenyl)propan-2-yl]phenol;oxirane Chemical compound C1CO1.C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 WPSWDCBWMRJJED-UHFFFAOYSA-N 0.000 description 1
- FIHBHSQYSYVZQE-UHFFFAOYSA-N 6-prop-2-enoyloxyhexyl prop-2-enoate Chemical compound C=CC(=O)OCCCCCCOC(=O)C=C FIHBHSQYSYVZQE-UHFFFAOYSA-N 0.000 description 1
- 208000019901 Anxiety disease Diseases 0.000 description 1
- 239000002202 Polyethylene glycol Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- TUOBEAZXHLTYLF-UHFFFAOYSA-N [2-(hydroxymethyl)-2-(prop-2-enoyloxymethyl)butyl] prop-2-enoate Chemical compound C=CC(=O)OCC(CO)(CC)COC(=O)C=C TUOBEAZXHLTYLF-UHFFFAOYSA-N 0.000 description 1
- HVVWZTWDBSEWIH-UHFFFAOYSA-N [2-(hydroxymethyl)-3-prop-2-enoyloxy-2-(prop-2-enoyloxymethyl)propyl] prop-2-enoate Chemical compound C=CC(=O)OCC(CO)(COC(=O)C=C)COC(=O)C=C HVVWZTWDBSEWIH-UHFFFAOYSA-N 0.000 description 1
- SSOONFBDIYMPEU-UHFFFAOYSA-N [3-hydroxy-2-[[3-hydroxy-2,2-bis(hydroxymethyl)propoxy]methyl]-2-(hydroxymethyl)propyl] prop-2-enoate Chemical compound OCC(CO)(CO)COCC(CO)(CO)COC(=O)C=C SSOONFBDIYMPEU-UHFFFAOYSA-N 0.000 description 1
- FHLPGTXWCFQMIU-UHFFFAOYSA-N [4-[2-(4-prop-2-enoyloxyphenyl)propan-2-yl]phenyl] prop-2-enoate Chemical compound C=1C=C(OC(=O)C=C)C=CC=1C(C)(C)C1=CC=C(OC(=O)C=C)C=C1 FHLPGTXWCFQMIU-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- -1 acrylic ester Chemical class 0.000 description 1
- 238000005937 allylation reaction Methods 0.000 description 1
- 230000036506 anxiety Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- LYCAIKOWRPUZTN-UHFFFAOYSA-N ethylene glycol Natural products OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- WGCNASOHLSPBMP-UHFFFAOYSA-N hydroxyacetaldehyde Natural products OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000009766 low-temperature sintering Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 125000005641 methacryl group Chemical group 0.000 description 1
- 238000006198 methoxylation reaction Methods 0.000 description 1
- YDKNBNOOCSNPNS-UHFFFAOYSA-N methyl 1,3-benzoxazole-2-carboxylate Chemical compound C1=CC=C2OC(C(=O)OC)=NC2=C1 YDKNBNOOCSNPNS-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007540 photo-reduction reaction Methods 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001223 polyethylene glycol Polymers 0.000 description 1
- 229920005650 polypropylene glycol diacrylate Polymers 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
- H01L2224/1132—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/1155—Selective modification
- H01L2224/11552—Selective modification using a laser or a focussed ion beam [FIB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
本发明提供一种导电性凸块及其形成方法和半导体装置及其制造方法,导电性凸块(17)形成在电子元件的电极端子(11)面上,导电性凸块(17)至少由导电性填料的密度不同的多种树脂固化物构成。从而能够防止由于安装时导电性凸块(17)的压溃而造成的短路和连接不良等现象的发生。
Description
技术领域
本发明涉及在半导体元件的电极端子或电路基板的电极端子上形成的导电性凸块,尤其涉及能够将窄间距化的半导体元件可靠地安装在电路基板上的电极端子的半导体装置。
背景技术
近年来,以手机、笔记本电脑、PDA、数码摄像机等为代表的移动电子设备迅速普及,用于实现其小型/薄型/轻量化的技术开发也正在快速推进。
妨碍该技术开发的主要电子部件是半导体元件,随着半导体元件的高密度化,电极端子的间距和面积变小。从而对将半导体元件倒装式安装到安装基板上时所使用的导电性凸块也有严格的要求。
在这种情况下,随着电极端子的窄间距化,存在着容易在安装基板的邻接的连接端子之间产生短路、以及由于半导体元件和安装基板的热膨胀系数的差而产生的应力使导电性凸块和电极端子之间的连接不良这样的问题。
特别是,由于上述手机等移动电子设备存在受到因落下而产生的冲击等可能性,所以如果电极端子之间的连接可靠性不充分,则存在移动电子设备连接不良之虞。
另外,随着半导体元件的布线规则的微细化,在半导体元件中形成的绝缘层的低介电常数化推进了绝缘层的多孔化。因此,在现有的倒装式安装的Au凸块等安装步骤中,存在施加到Au凸块下的绝缘层上的应力使绝缘层中产生裂纹等损坏现象等问题。
另一方面,为了避免窄间距化而用半导体元件的电路形成面整体形成导电性凸块的区域凸块方式,要求在安装区域整体安装基板具有高的平面度。通常,在区域凸块方式中,首先,在半导体元件上形成多个电极端子,在该电极端子上由焊料或Au等形成凸块。其次,使该半导体元件的凸块与在电路基板上形成的连接端子相对,将上述电极端子上的凸块与分别对应的连接端子电接合。而且,为了提高半导体元件与电路基板的电结合和机械接合,通过向半导体元件与电路基板之间填充(未充满(アンダ一フイル))树脂材料的步骤来制作。
但是,为了向电路基板安装如电极端子数超过5000个那样的下一代LSI,需要形成与100μm以下的窄间距相对应的凸块,但是现在的焊料凸块形成技术难以与之相对应。
另外,由于需要与电极端子数对应地形成多个凸块,所以为了实现低成本化,还要求通过每个半导体元件的安装间隙的缩短来实现高生产率。
以往,用电镀法或网板印刷法等作为凸块的形成技术,虽然电镀法适用于窄间距,但是由于步骤复杂,所以存在生产率方面的问题。
另外,网板印刷法生产率高,但是由于使用掩模所以难以与窄间距化相对应。
在这种状况下,近年来多次提出了在LSI元件的电极端子和电路基板的连接端子上,选择性地形成焊料凸块的技术。这些技术不仅适用于微细凸块的形成,还由于能够一并形成凸块所以生产率高,作为适于向下一代LSI的电路基板安装的技术逐渐受到瞩目。
上述技术,首先向形成了连接端子的电路基板的整个面涂敷由表面形成了氧化被膜的焊料粉末和钎剂的混合物所形成的焊膏。并且,在该状态下加热电路基板,使焊料粉末熔融,在邻接的连接端子之间不引起短路的情况下,在连接端子上选择性地形成焊料层(例如,参照专利文献1)。
另外,还有向形成了连接端子的电路基板的整个面上涂敷以有机酸铅盐和金属锡为主要成分的膏状组成物,通过加热电路基板使Pb与Sn发生置换反应,从而使Pb/Sn的合金在电路基板的连接端子上选择性地析出的技术(例如,参照专利文献2或非专利文献1)。
还有,将表面上形成了电极的电路基板浸入药剂中,仅在连接端子的表面上形成粘结性被膜,然后使焊料粉末粘结在该粘结性被膜上,之后对其进行加热熔融在连接端子上选择性地形成凸块的技术(例如,参照专利文献3)。
但是,上述技术中的任何一个都示出了在半导体元件的电极端子上或电路基板的连接端子上形成凸块的方法。在通常的倒装式安装中,在形成了凸块之后,将半导体元件搭载到电路基板上。并且,需要利用焊料回流经由凸块进行连接端子和电极端子之间的接合的步骤、及向电路基板与半导体元件之间注入未充满材料从而将半导体元件固定在电路基板上的步骤。因此,造成成本上升。
为了解决这样的问题,通常采用通过印刷网板的贯通孔在半导体元件的电极形成面上印刷导电性膏剂,从而低成本地一并形成凸块电极的方法(例如,参照专利文献4)。
但是,在专利文献4中示出的导电性凸块中,如用表示通过导电性膏剂形成导电性凸块的方法的图7A~图7E的剖面图所说明的那样,存在如下所述的问题。
首先,如图7A所示,在设置了多个电极端子101的半导体元件102的上表面配置印刷网板104,所述印刷网板104与多个电极端子101对应的位置上具有开口部103。并且,向印刷网板104上表面放置导电性膏剂105,在导电性膏剂105上推压刮浆板106的同时,从开口部103向电极端子101的面上印刷并填充。
接着,如图7B所示,取下印刷网板104,从而在电极端子101上以印刷时的低粘度状态形成导电性凸块105a。此时,如图7C所示,随着印刷后时间的经过,由于其粘性低,电极端子101上的导电性凸块105a在电极端子101的周边发生坍塌现象,从而存在着使电极端子的窄间距化受限制这样的问题。
接着,如图7D所示,使半导体元件102翻转,使其与在电路基板107的表面上设置的电极端子108位置相对应地进行倒装式安装。此时,如图7E所示,安装时在半导体元件102和电路基板107之间产生倾斜时,由于不均匀的加压压力的差异导致导电性凸块压溃,使在邻接的电极端子101之间产生短路109与连接不良部110而导致产生不均匀的连接电阻,从而存在着不能抑制这些现象发生的问题。
专利文献1:日本特开2000-94179号公报;
专利文献2:日本特开平1-157796号公报;
专利文献3:日本特开平7-74459号公报;
专利文献4:日本特开平11-274209号公报;
非专利文献1:日本电子设备(electronics)安装技术,2000年9月号,pp38-45。
发明内容
本发明的导电性凸块形成在电子部件的电极端子面上,该导电性凸块至少由导电性填料的密度不同的多种树脂固化物构成。
由此能够保持印刷掩模分离时的凸块形状的微细性。而且,在安装多个电子部件彼此时,由导电性填料的密度等不同的树脂固化物将电子部件之间的间隔保持为一定,能够有效地抑制导电性凸块的压溃、电极端子间彼此的短路和连接不良等现象。
另外,本发明的导电性凸块的形成方法包括:使印刷掩模的开口部对位于电子部件的电极端子上,经由开口部向电极端子上涂敷导电性膏剂的步骤;取下印刷掩模之后,经由曝光掩模向电极端子上的导电性膏剂的一部分照射紫外光或可见光,使所述导电性膏剂的一部分固化从而形成第一固化部的步骤;加热所述电子部件,在所述第一固化部以外的部分形成第二固化部的步骤。
另外,本发明的导电性凸块的形成方法包括:使印刷掩模的开口部对位于电子部件的电极端子上,经由开口部向电极端子上印刷导电性膏剂的步骤;在印刷掩模的上表面配置曝光掩模,经由液晶掩模向被印刷的导电性膏剂的一部分照射紫外光或可见光,使导电性膏剂的一部分固化从而形成第一固化部的步骤;加热电子部件,在第一固化部以外的部分形成第二固化部的步骤;取下曝光掩模及印刷掩模的步骤。
由此能够很容易地以窄的间距制作机械连接和电连接稳定性优良的导电性凸块。
另外,本发明的半导体装置具有用上述导电性凸块来电连接电路基板的电极端子和半导体元件的电极端子的结构。由此能够实现在连接强度及电连接性方面可靠性高的半导体装置。
另外,本发明的半导体装置的制造方法包括:将利用导电性凸块的形成方法形成了导电性凸块的半导体晶片切断为一个一个的半导体元件的步骤;翻转半导体元件,使导电性凸块对位于电路基板上的电极端子上并进行安装的步骤;通过对半导体元件和电路基板进行加压、加热,至少使导电性凸块的第二固化部固化从而接合半导体元件和电路基板的步骤;向半导体元件和电路基板的间隙注入密封树脂并使其固化的步骤。
由此能够以高安装密度高生产率地制作机械连接和电连接稳定性优良的半导体装置。
附图说明
图1A是概括地说明本发明实施方式1的导电性凸块的构造的立体图。
图1B是图1A的1B-1B线剖面图。
图2A是说明本发明实施方式1的导电性凸块的形成方法的剖面图。
图2B是说明本发明实施方式1的导电性凸块的形成方法的剖面图。
图2C是说明本发明实施方式1的导电性凸块的形成方法的剖面图。
图2D是说明本发明实施方式1的导电性凸块的形成方法的剖面图。
图2E是说明本发明实施方式1的导电性凸块的形成方法的剖面图。
图3A是说明本发明实施方式1的导电性凸块的其他例子的立体图及俯视图。
图3B是说明本发明实施方式1的导电性凸块的其他例子的立体图及俯视图。
图3C是说明本发明实施方式1的导电性凸块的其他例子的立体图及俯视图。
图3D是说明本发明实施方式1的导电性凸块的其他例子的立体图及俯视图。
图3E是说明本发明实施方式1的导电性凸块的其他例子的立体图及俯视图。
图4A是说明本发明实施方式2的导电性凸块的构造的剖面图。
图4B是说明本发明实施方式2的导电性凸块的构造的其他例子的剖面图。
图4C是说明本发明实施方式2的导电性凸块的构造的又一其他例子的剖面图。
图5A是说明本发明实施方式3的导电性凸块的形成方法的剖面图。
图5B是说明本发明实施方式3的导电性凸块的形成方法的剖面图。
图5C是说明本发明实施方式3的导电性凸块的形成方法的剖面图。
图5D是说明本发明实施方式3的导电性凸块的形成方法的剖面图。
图5E是说明本发明实施方式3的导电性凸块的形成方法的剖面图。
图6A是说明本发明实施方式4的半导体装置的制造方法的剖面图。
图6B是说明本发明实施方式4的半导体装置的制造方法的剖面图。
图6C是说明本发明实施方式4的半导体装置的制造方法的剖面图。
图7A是说明现有的由导电性膏剂形成导电性凸块的方法的剖面图。
图7B是说明现有的由导电性膏剂形成导电性凸块的方法的剖面图。
图7C是说明现有的由导电性膏剂形成导电性凸块的方法的剖面图。
图7D是说明现有的由导电性膏剂形成导电性凸块的方法的剖面图。
图7E是说明现有的由导电性膏剂形成导电性凸块的方法的剖面图。
符号说明
11,31,41,51,61 电极端子
12,32,42 半导体晶片(电子部件)
13,43 开口部
14,44 印刷掩模
15,45 导电性膏剂
16,46 刮浆板
17,37,47,57 导电性凸块
17a,37a,47a,57a 第一固化部
17b,37b,47b,57b 第二固化部
17c,47c 导电性凸块前驱体
18,48 液晶掩模(曝光掩模)
19,49 光透过部
52 半导体元件
60 电路基板
62 密封树脂
具体实施方式
下面参照附图说明本发明的实施方式,在各个图中相同的结构要素用相同的符号表示。
(实施方式1)
图1A是概括地说明本发明实施方式1的导电性凸块的构造的立体图,图1B是图1A的1B-1B线剖面图。此外,在图1A和图1B中省略了形成导电性凸块的电子部件。
如图1A和图1B所示,在例如由半导体元件和电路基板等构成的电子部件(未图示)的电极端子11上设置的导电性凸块17例如由第一固化部17a和第二固化部17b构成,所述第一固化部17a位于导电性凸块17的中心部,是通过光固化法和热固化法固化的,第二固化部17b以包围所述第一固化部17a的形状形成在电极端子11的外周,并利用热固化法以预成型(prepreg)状态半固化。并且,由第一固化部17a和第二固化部17b构成的导电性凸块17例如由含Ag粒子等导电性填料的树脂固化物构成。因此,在例如通过导电性凸块,与其他的电路基板连接并固化的情况下,构成第一固化部17a的树脂固化物的导电性填料的密度值比构成第二固化部17b的树脂固化物的导电性填料的密度值小。例如,第一固化部17a的导电性填料的密度是10%~50%,第二固化部17b的导电性填料的密度是50%以上~90%。此外,上述数值严格地说不是密度,而是从导电性凸块的截面中每单位面积的导电性填料的占有率求得的值。
其原因是,第一固化部17a至少通过光固化和热固化两阶段固化,第二固化部17b仅通过热固化而固化。即,由于第一固化部17a的树脂固化物的树脂成分在热固化之前通过光固化发生固化,所以热固化时挥发的成分少。因此,第二固化部17b的树脂固化物的树脂成分热固化时的挥发成分量大,所以相对而言,导电性填料的密度比第一固化部17a的导电性填料的密度大。
其中,作为树脂固化物,优选同时含有具有多个光聚合基的多官能团单体和仅具有一个光聚合基的单官能团单体。
作为具有多个光聚合基的多官能团单体,例如使用在一个分子中具有两个以上的如碳-碳双键多键那样的可聚合的官能团的化合物。多官能团单体中含有的可聚合的官能团的数量优选为3个~10个,但是不限定于上述范围。此外,在可聚合的官能团的数量少于3个的情况下,有固化性降低的倾向。其官能团的数量多于10个时,分子尺寸变大,有粘度变大的倾向。
作为具有多个光聚合基的多官能团单体的具体的例子,例如可以列举烯丙基化环己基二丙烯酸酯、1,4-丁二醇二丙烯酸酯、1,3-丁二醇二丙烯酸酯、1,6-己二醇二丙烯酸酯、乙二醇二丙烯酸酯、二甘醇二丙烯酸酯、三甘醇二丙烯酸酯、聚乙二醇二丙烯酸酯、季戊四醇三丙烯酸酯、季戊四醇四丙烯酸酯、二季戊四醇五丙烯酸酯、二季戊四醇六丙烯酸酯、二季戊四醇单羟基五丙烯酸酯、双三羟甲基丙烷四丙烯酸酯、丙三醇二丙烯酸酯、甲氧基化环己二丙烯酸酯、新戊二醇二丙烯酸酯、丙二醇二丙烯酸酯、聚丙二醇二丙烯酸酯、三丙三醇二丙烯酸酯、三羟甲基丙烷二丙烯酸酯、双酚A二丙烯酸酯、双酚A-环氧乙烷加成物的二丙烯酸酯、双酚A-环氧丙烷加成物的二丙烯酸酯。另外,还可以使用例如将上述化合物中含有的丙烯基的一部分或全部置换为甲基丙烯酰基的化合物。此外,还可以根据需要添加光还原性的色素和还原剂等光聚合引发剂。
另外,作为导电性填料,除了上述Ag以外,还采用例如Au、Pt、Ni、Cu、Pd、Mo、W等平均粒径为0.1μm~10μm左右的金属微粒。这些金属微粒可以单数使用,也可以两种以上混合使用。另外,也可以用由含有上述元素的合金构成的合金粉作为导电性填料使用。此外,从通过低温烧结形成低电阻的导体的目的出发,适于用熔点比较低、比电阻值低的金属材料作为导电粒子。作为这样的金属材料,例如优选Au、Ag、Cu。此外,由于Au非常昂贵,Cu容易氧化,不能在空气中烧结等原因,Ag是最合适的金属材料。并且,导电性填料的形状可以是块状、鳞片状、微结晶状、球状、粒状、片状等各种形状,也可以是不定形的。其中,导电粒子的形状优选是球状或粒状。原因是曝光时的光透过性好,曝光效率高。
根据上述结构,由第一固化部防止导电性凸块的坍塌,并且,由半固化状态的第二固化部防止在低的加压力下与其他电子部件等出现安装和位置偏差等。由此与窄间距化相对应,形成连接可靠性优良的导电性凸块。
以下,用图2A~图2E说明本实施方式的导电性凸块的形成方法。图2A~图2E是说明本发明实施方式1的导电性凸块的形成方法的剖面图。此外,以用形成了多个半导体元件的半导体晶片作为形成导电性凸块的电子部件的例子进行说明。另外,以用液晶掩模作为曝光掩模的例子进行说明,但是也可以使用金属掩模等。在液晶掩模的情况下,取得了能够通过电的方式任意改变光透过部的形状的显著效果。
首先,如图2A所示,在具有多个形成了多个电极端子11的半导体元件的半导体晶片12的上表面配置印刷掩模14,在印刷掩模14中设置了与电极端子11的位置相对应的形成导电性凸块用的开口部13。
接着,如图2B所示,在印刷掩模14上载置例如配合了60重量份~90重量份的Ag填料(平均粒径0.2μm~3μm)和5重量份~40重量份的光固化树脂(丙烯酸酯系)的导电性膏剂15,使刮浆板16在导电性膏剂15推压的同时向箭头方向移动,将导电性膏剂15填充到开口部13。
接着,如图2C所示,将印刷掩模14从半导体晶片12分离,从而在电极端子11上印刷形成导电性凸块前驱体17c。
接着,如图2D所示,配置曝光掩模(下面称为“液晶掩模”)18,在液晶掩模18中设置用来向导电性凸块前驱体17c的需要部位照射光的光透过部19。并且,经由其照射例如15mW/mm2的可见光或紫外光5秒钟,使构成导电性凸块前驱体17c中的导电性膏剂15的光固化树脂固化,从而形成第一固化部17a。
此外,由于光透过部19的面积、形状即使在光照射中也可以通过液晶掩模18的控制电路自由地改变,所以可以自由地设计第一固化部17a的形状和形成位置等。
接着,如图2E所示,以例如比导电性膏剂的树脂成分的热固化温度低的温度(例如120℃左右)加热,从而使第一固化部17a以外的导电性膏剂半固化而成预成型状态,形成第二固化部17b。由此制作了具有导电性填料的密度不同的第一固化部17a及第二固化部17b的导电性凸块17。
此外,第二固化部17b在后述的半导体装置的制造步骤中,通过由导电性凸块17倒装式安装半导体元件和电路基板时的加热而完全固化。由此形成导电性填料的密度具有比第一固化部17a大的值的第二固化部17b。此时,第一固化部17a的导电性填料的密度是10%~50%,第二固化部17b的导电性填料的密度是50%以上~90%。此外,上述数值严格地说不是密度,而是从导电性凸块的截面中每单位面积的导电性填料的占有率求得的值。
其原因是,如上所述,第一固化部17a是通过光固化和热固化而固化的,而第二固化部17b仅通过热固化而固化的,从而产生差别。
以下说明本实施方式的导电性凸块17的结构的其他例子。
图3A~图3E的左图是说明本发明实施方式1的导电性凸块17的其他例子的立体图,图3A~图3E的右图是其平面图。此外,在图3A~图3E中省略了形成导电性凸块17的电子部件,仅示出了在电极端子11上形成的由第一固化部17a和第二固化部17b构成的导电性凸块17的形状。另外,在图3中示出的第一固化部17a的形状可以通过控制液晶掩模的光透过部而自由地设定为图3A~图3E中示出的例子以外的形状。
首先,图3A是在导电性凸块17的外周部上具有第一固化部17a,在中心部设置了第二固化部17b,与实施方式1的导电性凸块的结构相反。这可以通过在液晶掩模设置的环状的光透过部而很容易地形成。由此能够通过预先光固化了的第一固化部防止例如在连接半导体元件和电路基板进行加热时发生的第二固化部的坍塌于未然。
接着,图3B是将第一固化部17a设计成环状,配置在导电性凸块17的内部,在导电性凸块17的中心部及第一固化部17a的外周部配置第二固化部17b,从而形成从两侧夹着第一固化部17a的形状。
另外,在图1以及图3A和图3B中,均以将第一固化部17a形成为圆形或环状为例进行了说明,但是不限于此。例如图3C所示,使第一固化部17a为方柱状形成在导电性凸块17的中央位置,还可以在其外周部设置第二固化部17b。在附图中以第一固化部17a的形状为方形柱为例进行图示,但不限于此,也可以是五角柱、六角柱等,使其平面形状为多边形。
另外,在图3A~图3C中,都以在电极端子11上形成了一个第一固化部17a为例进行了说明,但是不限于此。例如,如图3D和图3E所示,也可以在电极端子11上形成多个第一固化部17a。即,在图3D中,在电极端子11上形成两个矩形的第一固化部17a,在图3E中示出了形成四个的例子。当然这些矩形的第一固化部17a的形状也可以是圆柱状或其他任意的形状,第一固化部17a的数量也可以是五个以上。而且,在图3D中,也可以将矩形的第一固化部17a的形状分别形成为半圆形,此外,也可以使图3E中的方形柱的第一固化部17a例如以扇形等形状配置四个。
此外,第一固化部17a的形状可以根据形成导电性凸块17的半导体元件和在半导体晶片的上表面形成的电极端子的大小、形状和电极端子间的间距而设计为合适的。而且,考虑到倒装式安装时加压的负荷和加热温度,例如可以根据对树脂固化物的树脂成分的挥发量的控制等,预先任意地设计形成导电性凸块时第一固化部和第二固化部的导电性填料的密度。
另外,第一固化部17a的形状和形成数量不限于上述实施方式1中说明的各个例子,可以任意地选择为上述设计因素所涉及的最佳形状或最佳形成数量。
另外,在本实施方式中,以在圆形的电极端子上形成圆形的导电性凸块为例进行了说明,但不限于此。例如电极端子11的形状也可以为四角形,与其形状相对应地设计并形成导电性凸块17和第一固化部17a的形状。
(实施方式2)
以下参照图4A~图4C说明本发明实施方式2的导电性凸块的构造。
图4A是说明本发明实施方式2的导电性凸块的构造的剖面图,图4B是说明本发明实施方式2的导电性凸块的结构的其他例子的剖面图,图4C是说明本发明实施方式2的导电性凸块的结构的其他例子的剖面图。
如图4A~图4C所示,基本构造是在导电性凸块37的厚度(高度)方向上,例如叠层在半导体晶片32上而形成构成导电性凸块的导电性填料的密度不同的第一固化部37a和第二固化部37b。此外,与实施方式1相同,以用液晶掩模作为曝光掩模为例进行说明,但是也可以用金属掩模等。
即,在电极端子31上的导电性凸块37的下部形成第一固化部37a,在其上部具有第二固化部37b。此外,即使在本实施方式中,第二固化部37b也是在控制液晶掩模(未图示)的光透过部并通过照射可见光或紫外光而形成了第一固化部37a后,例如用印刷掩模印刷第二固化部37b以覆盖第一固化部37a,通过低温加热形成预成型状态的半固化的第二固化部37b。
具体而言,首先,如图4A所示,例示了按照与电极端子31的面积相同的面积、形状形成了第一固化部37a,以及如图4B所示,与实施方式1相同地在电极端子31的中心部形成第一固化部37a,在其周围形成了第二固化部37b。但是,以第一固化部37a埋没在第二固化部37b的内部的状态构成导电性凸块37。
而且,如图4C所示,与实施方式1中的图3D和图3E中示出的情况相同,还能够形成将多个第一固化部37a埋没设置在第二固化部37b的内部的结构。
根据本实施方式,由于可以在半固化状态的第二固化部的整个面与其他电子部件等的电极端子连接,所以能够实现通过更低负荷的安装。而且,由于能够在半固化状态下连接,所以能够进一步提高连接的可靠性。
(实施方式3)
以下用图5A~图5E说明本发明实施方式3的导电性凸块的形成方法。图5A~图5E是说明本发明实施方式3的导电性凸块的形成方法的剖面图。此外,与实施方式1的情况相同,以用形成了多个半导体元件的半导体晶片作为形成导电性凸块的电子部件为例进行说明。此外,以用液晶掩模作为曝光掩模为例进行说明,但是也可以用金属掩模等。
首先,如图5A所示,在具有多个形成了多个电极端子41的半导体元件的半导体晶片42的上表面配置印刷掩模44,在印刷掩模44中设置了与电极端子41的位置相对应的形成导电性凸块用的开口部43。接着,在印刷掩模44上载置导电性膏剂45,使刮浆板46推压导电性膏剂45的同时向箭头方向移动。由此将导电性膏剂45填充到开口部43中,如图5B所示,形成导电性凸块前驱体47c。
接着,如图5C所示,在印刷掩模44的上表面配置液晶掩模48,在所述液晶掩模48设置了光透过部49。
此时,按照使该光透过部49与导电性凸块前驱体47c的需要进行光照射的部位相对应的方式来配置液晶掩模48。并且,如图5D所示,经由光透过部49照射可见光或紫外光,使构成导电性凸块前驱体47c中的导电性膏剂45的光固化树脂固化,从而形成第一固化部47a。
此外,与实施方式1相同,光透过部49的面积、形状可以利用液晶掩模48的控制电路自由地改变,与图3A~图3E中所示的情况相同,能够自由地控制第一固化部47a的形状及形成部分等。
接着,如图5E所示,通过用例如比导电性膏剂的树脂成分的热固化温度低的温度(例如120℃左右)加热,从而使第一固化部47a以外的导电性膏剂半固化而成为预成型状态,形成第二固化部47b。然后,从半导体晶片42上沿箭头所示的方向依次或者同时取下印刷掩模44及液晶掩模48。
由此在半导体晶片42的电极端子41上制作了由第一固化部47a和导电性填料的密度具有比第一固化部47a大的值的第二固化部47b构成的导电性凸块47。
根据本实施方式,在加热第二固化部时,由于使其在被印刷掩模包围其外周的状态下固化,所以能够将第二固化部的导电性膏剂的坍塌等防患于未然。而且,由于在第二固化部处于半固化的状态下取下印刷掩模和液晶掩模,所以不易发生由于印刷掩模等带走导电性膏剂而造成的导电性凸块的形状变化。
(实施方式4)
以下,用图6A~图6C说明本发明实施方式4的半导体装置的制造方法。图6A~图6C是说明本发明实施方式4的半导体装置的制造方法的剖面图。此外,半导体装置具有将包括上述各实施方式所形成的导电性凸块的半导体元件倒装式安装在电路基板上的结构。
首先,作为前置步骤,用切割机将上述各个实施方式中示出的形成了导电性凸块的半导体晶片切断,分割为可倒装式安装到电路基板60上的多个半导体元件52。
接着,如图6A所示,与电路基板60上的电极端子61对置地配置半导体元件52的电极端子51面,并向箭头表示的方向加压,其中电极端子51面形成了由半导体元件52的第一固化部57a和第二固化部57b构成的导电性凸块57。
接着,如图6B所示,用已经通过半固化法固化的第一固化部57a限制并保持半导体元件52和电路基板60的间隔。并且,与此同时,例如在150℃左右进行加热,使导电性凸块57的处于预成型状态的第二固化部57b完全固化,电连接并机械连接电路基板60和半导体元件52。
接着,如图6C所示,向半导体元件52和电路基板60的间隙中填充绝缘性的密封树脂62,通过加热固化制作半导体装置。
根据本实施方式,即使局部地改变向半导体元件52施加的压力,也能够由构成导电性凸块57的第一固化部57a限制半导体元件52和电路基板60的间隔,所以能够不倾斜地安装半导体元件52。由此,能够防止发生由于间隔改变引起的导电性凸块的不均匀压溃和挤出所造成的电极端子间的短路或连接不良等,而这是现有的倒装式安装法中存在的问题。而且,由于不容易产生导电性凸块的不均匀压溃,所以窄间距的导电性凸块的形成成为可能,能够高密度地安装半导体装置。另外,利用导电性凸块57的半固化的第二固化部57b能够防止半导体元件和电路基板的电极端子的台阶上的位置偏差等。
如上述所说明的,利用由导电性填料的密度不同的、至少包括第一固化部和第二固化部的树脂固化物所构成的导电性凸块,能够抑制倒装式安装时导电性凸块的压溃等,实现可靠性优异的半导体装置。
产业上的利用可能性
根据本发明,由于能够防止加压造成的安装时导电性凸块的不均匀压溃,所以电极端子间的短路和连接不良不易发生,在希望按照窄间距高密度安装的安装区域和半导体装置等中有用。
Claims (10)
1.一种导电性凸块,其形成在电子部件的电极端子面上,其特征在于,
所述导电性凸块至少由导电性填料的密度不同的多种树脂固化物构成,
所述导电性凸块的至少在中心部形成的所述树脂固化物的所述导电性填料的密度比在外周部形成的所述树脂固化物的所述导电性填料的密度小或大。
2.根据权利要求1所述的导电性凸块,其特征在于,
所述电子部件是半导体元件或电路基板。
3.根据权利要求1所述的导电性凸块,其特征在于,
包括所述导电性填料的所述多种树脂固化物至少由第一固化部及第二固化部构成,所述第一固化部利用光固化法和热固化法固化,所述第二固化部利用所述热固化法固化。
4.根据权利要求1所述的导电性凸块,其特征在于,
作为所述导电性凸块的所述树脂固化物的树脂成分,至少包括光固化树脂成分及热固化树脂成分。
5.一种权利要求1所述的导电性凸块的形成方法,其特征在于,包括:
使印刷掩模的开口部对位于电子部件的电极端子上,经由所述开口部在所述电极端子上涂敷导电性膏剂的步骤;
取下所述印刷掩模之后,经由曝光掩模向所述电极端子上的导电性膏剂的一部分照射紫外光或可见光,使所述导电性膏剂的一部分固化从而形成第一固化部的步骤;
加热所述电子部件,在所述第一固化部以外的部分形成第二固化部的步骤。
6.一种权利要求1所述的导电性凸块的形成方法,其特征在于,包括:
使印刷掩模的开口部对位于电子部件的电极端子上,经由所述开口部在所述电极端子上印刷导电性膏剂的步骤;
在所述印刷掩模的上表面配置曝光掩模,经由所述曝光掩模向被印刷的所述导电性膏剂的一部分照射紫外光或可见光,使所述导电性膏剂的一部分固化从而形成第一固化部的步骤;
加热所述电子部件,在所述第一固化部以外的部分形成第二固化部的步骤;
取下所述曝光掩模及印刷掩模的步骤。
7.根据权利要求5或6所述的导电性凸块的形成方法,其特征在于,
所述曝光掩模是液晶掩模。
8.根据权利要求5或6所述的导电性凸块的形成方法,其特征在于,
所述导电性膏剂包括光固化树脂及热固化树脂。
9.一种半导体装置,其特征在于,使用权利要求1所述的导电性凸块来电连接电路基板的电极端子和半导体元件的电极端子。
10.一种半导体装置的制造方法,其特征在于,包括:
将利用权利要求5或6所述的导电性凸块的形成方法形成了导电性凸块的半导体晶片切断为一个一个的半导体元件的步骤;
翻转所述半导体元件,使所述导电性凸块对位于电路基板上的电极端子上并进行安装的步骤;
通过对所述半导体元件和所述电路基板进行加压、加热,至少使所述导电性凸块的第二固化部固化从而接合所述半导体元件和所述电路基板的步骤;
向所述半导体元件和所述电路基板的间隙注入密封树脂并使其固化的步骤。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006351242 | 2006-12-27 | ||
JP351242/2006 | 2006-12-27 | ||
PCT/JP2007/072423 WO2008078478A1 (ja) | 2006-12-27 | 2007-11-20 | 導電性バンプとその形成方法および半導体装置とその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101578694A CN101578694A (zh) | 2009-11-11 |
CN101578694B true CN101578694B (zh) | 2011-07-13 |
Family
ID=39562271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800424492A Expired - Fee Related CN101578694B (zh) | 2006-12-27 | 2007-11-20 | 导电性凸块及其形成方法和半导体装置及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7928566B2 (zh) |
JP (1) | JP5003689B2 (zh) |
KR (1) | KR101155709B1 (zh) |
CN (1) | CN101578694B (zh) |
TW (1) | TWI469232B (zh) |
WO (1) | WO2008078478A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4396754B2 (ja) * | 2007-07-11 | 2010-01-13 | ソニー株式会社 | 配線への素子の電気的接続方法及び発光素子組立体の製造方法 |
US7838410B2 (en) | 2007-07-11 | 2010-11-23 | Sony Corporation | Method of electrically connecting element to wiring, method of producing light-emitting element assembly, and light-emitting element assembly |
DE102008042382A1 (de) * | 2008-09-26 | 2010-04-01 | Robert Bosch Gmbh | Kontaktanordnung zur Herstellung einer beabstandeten, elektrisch leitfähigen Verbindung zwischen mikrostrukturierten Bauteilen |
KR101677739B1 (ko) | 2010-09-29 | 2016-11-21 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조방법 |
WO2012081144A1 (ja) * | 2010-12-15 | 2012-06-21 | パナソニック株式会社 | 半導体装置及びその製造方法 |
KR101479811B1 (ko) * | 2011-12-02 | 2015-01-08 | 광 석 서 | 투명 전극 필름 제조용 기재 필름 |
EP2960930A4 (en) * | 2013-02-22 | 2017-07-12 | Furukawa Electric Co., Ltd. | Connecting structure, and semiconductor device |
CN113556882B (zh) * | 2020-04-23 | 2022-08-16 | 鹏鼎控股(深圳)股份有限公司 | 透明电路板的制作方法以及透明电路板 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1186340A (zh) * | 1996-12-24 | 1998-07-01 | 松下电子工业株式会社 | 引线框架及其制造方法、半导体装置及其制造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0747233B2 (ja) | 1987-09-14 | 1995-05-24 | 古河電気工業株式会社 | 半田析出用組成物および半田析出方法 |
JPH02280334A (ja) | 1989-04-21 | 1990-11-16 | Citizen Watch Co Ltd | 半導体装置及びその製造方法 |
JPH06151438A (ja) | 1992-11-12 | 1994-05-31 | Tanaka Kikinzoku Kogyo Kk | 感光性導電ペーストによるバンプ形成方法 |
JP3537871B2 (ja) | 1993-07-05 | 2004-06-14 | 昭和電工株式会社 | はんだコートおよびその形成方法 |
US6297559B1 (en) * | 1997-07-10 | 2001-10-02 | International Business Machines Corporation | Structure, materials, and applications of ball grid array interconnections |
JP3423239B2 (ja) | 1998-01-22 | 2003-07-07 | リコーマイクロエレクトロニクス株式会社 | バンプ電極形成方法 |
US6225205B1 (en) * | 1998-01-22 | 2001-05-01 | Ricoh Microelectronics Company, Ltd. | Method of forming bump electrodes |
JPH11274199A (ja) | 1998-03-19 | 1999-10-08 | Ricoh Microelectronics Co Ltd | バンプ電極形成方法及びその装置 |
JP3996276B2 (ja) | 1998-09-22 | 2007-10-24 | ハリマ化成株式会社 | ソルダペースト及びその製造方法並びにはんだプリコート方法 |
JP3822040B2 (ja) * | 2000-08-31 | 2006-09-13 | 株式会社ルネサステクノロジ | 電子装置及びその製造方法 |
TWI230425B (en) * | 2004-02-06 | 2005-04-01 | South Epitaxy Corp | Bumping process for light emitting diode |
JP4385794B2 (ja) * | 2004-02-26 | 2009-12-16 | ソニーケミカル&インフォメーションデバイス株式会社 | 異方性導電接続方法 |
JP4761164B2 (ja) * | 2006-03-31 | 2011-08-31 | ブラザー工業株式会社 | 接続構造、および部品搭載基板 |
WO2008117513A1 (ja) * | 2007-03-23 | 2008-10-02 | Panasonic Corporation | 導電性バンプとその製造方法および電子部品実装構造体 |
WO2008136419A1 (ja) * | 2007-04-27 | 2008-11-13 | Nec Corporation | 半導体装置及び製造方法並びにリペア方法 |
US8080884B2 (en) * | 2008-06-27 | 2011-12-20 | Panasonic Corporation | Mounting structure and mounting method |
JP5542470B2 (ja) * | 2009-02-20 | 2014-07-09 | パナソニック株式会社 | はんだバンプ、半導体チップ、半導体チップの製造方法、導電接続構造体、および導電接続構造体の製造方法 |
JP2010263014A (ja) * | 2009-04-30 | 2010-11-18 | Panasonic Corp | 半導体装置 |
-
2007
- 2007-11-20 JP JP2008550997A patent/JP5003689B2/ja not_active Expired - Fee Related
- 2007-11-20 WO PCT/JP2007/072423 patent/WO2008078478A1/ja active Application Filing
- 2007-11-20 US US12/514,649 patent/US7928566B2/en not_active Expired - Fee Related
- 2007-11-20 KR KR1020097009613A patent/KR101155709B1/ko not_active IP Right Cessation
- 2007-11-20 CN CN2007800424492A patent/CN101578694B/zh not_active Expired - Fee Related
- 2007-11-28 TW TW96145169A patent/TWI469232B/zh not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1186340A (zh) * | 1996-12-24 | 1998-07-01 | 松下电子工业株式会社 | 引线框架及其制造方法、半导体装置及其制造方法 |
Non-Patent Citations (2)
Title |
---|
JP特开6-151438A 1994.05.31 |
JP特开平11-274199A 1999.10.08 |
Also Published As
Publication number | Publication date |
---|---|
CN101578694A (zh) | 2009-11-11 |
KR101155709B1 (ko) | 2012-06-12 |
TW200834771A (en) | 2008-08-16 |
US7928566B2 (en) | 2011-04-19 |
US20100029044A1 (en) | 2010-02-04 |
TWI469232B (zh) | 2015-01-11 |
WO2008078478A1 (ja) | 2008-07-03 |
JPWO2008078478A1 (ja) | 2010-04-15 |
KR20090067202A (ko) | 2009-06-24 |
JP5003689B2 (ja) | 2012-08-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101578694B (zh) | 导电性凸块及其形成方法和半导体装置及其制造方法 | |
CN101601127B (zh) | 导电性凸起及其制造方法以及电子部件安装结构体 | |
US7875496B2 (en) | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body | |
US7919357B2 (en) | Method for mutually connecting substrates, flip chip mounting body, and mutual connection structure between substrates | |
US20170162550A1 (en) | Interconnect Structures For Assembly Of Semiconductor Structures Including At Least One Integrated Circuit Structure | |
WO2009110095A1 (ja) | 導電材料、導電ペースト、回路基板、及び半導体装置 | |
US7649267B2 (en) | Package equipped with semiconductor chip and method for producing same | |
WO2018043162A1 (ja) | 回路モジュールおよび電子機器 | |
JP2011023574A (ja) | 半導体装置およびその製造方法 | |
CN102612274A (zh) | 配线基板及其制造方法 | |
JP4134878B2 (ja) | 導体組成物および導体組成物を用いた実装基板ならびに実装構造 | |
CN101523594A (zh) | 半导体封装和用于制造半导体封装的方法 | |
US7911064B2 (en) | Mounted body and method for manufacturing the same | |
JP4835406B2 (ja) | 実装構造体とその製造方法および半導体装置とその製造方法 | |
JP7425704B2 (ja) | 半導体装置の製造方法および半導体装置 | |
JP4725373B2 (ja) | 電子部品実装構造体の製造方法 | |
JP2010212616A (ja) | 電極パッド及びその製造方法、回路配線体及びその製造方法、並びに、はんだ継手構造及びその方法 | |
JP2007115676A (ja) | 導電性粒子及び導電接続構造体 | |
JP2008117828A (ja) | 半導体装置 | |
JP2009283918A (ja) | 配線基板と配線基板の接続方法 | |
JP4591715B2 (ja) | 半導体装置の製造方法 | |
WO2018043388A1 (ja) | 回路モジュールおよび電子機器 | |
JP2005340451A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
CN116779729A (zh) | Led芯片转移结构及其转移方法、显示装置 | |
JP2008235392A (ja) | 半導体装置のリペア方法および半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110713 Termination date: 20171120 |
|
CF01 | Termination of patent right due to non-payment of annual fee |