CN101548377B - 具有增强散热功能的封装集成电路 - Google Patents

具有增强散热功能的封装集成电路 Download PDF

Info

Publication number
CN101548377B
CN101548377B CN2006800277751A CN200680027775A CN101548377B CN 101548377 B CN101548377 B CN 101548377B CN 2006800277751 A CN2006800277751 A CN 2006800277751A CN 200680027775 A CN200680027775 A CN 200680027775A CN 101548377 B CN101548377 B CN 101548377B
Authority
CN
China
Prior art keywords
thermal bond
semiconductor element
heat
integrated circuit
bond pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2006800277751A
Other languages
English (en)
Other versions
CN101548377A (zh
Inventor
K·J·海斯
李楚诚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101548377A publication Critical patent/CN101548377A/zh
Application granted granted Critical
Publication of CN101548377B publication Critical patent/CN101548377B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905Shape
    • H01L2224/49051Connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73207Bump and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体封装(10),使用了多个在密封体(16)内从管芯(14)上的一个或多个热结合焊盘(22,24,26)向上延伸的热导体(56-64)进行散热。热导体可以是结合引线或导热柱形凸起,并且不延伸出管芯的侧边。热导体中的一个或多个可以在密封体中接成环路并暴露在密封体的上表面。一种形式中,散热器(68)叠置在密封体上以进一步的移除热量。在另外一种形式中,散热器作为电源或接地端直接通过热导体与管芯内部节点相接。有源结合焊盘可以专门沿着管芯边缘放置或者还包含在管芯内部。

Description

具有增强散热功能的封装集成电路
技术领域
本发明大体上涉及集成电路的封装,尤其是能够增强散热能力的封装。
背景技术
由于在单位面积上不断增加的晶体管的数量,集成电路的密度越来越大,会有更多的晶体管开关导致产生更多的热量。因此,为了散发更多的热量,多种封装类型都处于持续的压力下。一种常用的衡量特定封装效率的度量标准称为结到管壳热阻(theta-JC)。theta-JC通常用摄氏度每瓦特表示,代表封装的散热能力。封装的选择基于例如:散热、电气特性、尺寸和成本等若干因素。其它因素可以折衷,但是散热通常是必须满足的要求。实际上,一个给定的集成电路管芯具有功率耗散要求时,其它电气特性、尺寸和成本问题必须按照功率耗散要求来考虑。因此,功率耗散上的改进可以导致尺寸的减小和成本的降低的一个或多个性能的提升。从成本角度讲,通常比较理想的封装是塑料封装。已经研发出来具有不同电气特性的多种塑料封装。在塑料封装中,通常具有塑模工艺,其利用塑料来密封集成电路。由于塑料通常是绝热体,使得封装中的集成电路产生的热量很难散发出去。因此,任何对塑料封装散热的改进都可以降低成本和/或改进性能。
所以需要可耗散集成电路热量的封装,尤其是塑料封装。
附图说明
通过附图中的实例说明本发明,而非限制本发明,附图中相同的参考标记表示相似的元件,且其中:
图1是根据本发明的实施例的封装集成电路的截面图;
图2是具有附加特征的图1中的封装集成电路的截面图;
图3是图1中封装集成电路的顶视图;
图4是根据本发明的另一实施例的封装集成电路的截面图;以及
图5是根据本发明的又一实施例的封装集成电路的截面图。
本领域的技术人员应理解,附图中的元件是说明性的,为了简化和清楚,并无需按比例示出。例如,在附图中可以相对于另一些元件放大某些元件的尺寸以帮助增进对本发明实施例的理解。
具体实施方式
一方面,封装集成电路具有从集成电路表面垂直向上延伸至封装表面的结合引线,其优选为塑料。这些垂直结合引线暴露在外界环境下以有效散热。结合引线可以连接至集成电路表面无功能的一部分。这种情况下,垂直结合引线电浮置。为了进一步增强散热,热传导金属板可以连接至垂直结合引线的暴露端。上述板也可以用作电源板,这种情况下,垂直结合引线连接至例如VDD或地的特定的电源端。参考附图和下面的描述可以更好的理解本发明。
图1中示出的封装集成电路10包括封装基板12,位于封装基板12上的集成电路14,和塑料密封体16,该塑料密封体16模塑成覆盖集成电路14的顶面和侧面部分以及封装基板12顶面的一部分。基板12的一小边缘部分没有被塑料密封体16所覆盖。集成电路14典型为矩形半导体,其已经制造成包括执行电功能的晶体管和其他可能的电路元件。集成电路也可以通称为管芯或芯片。封装结合焊盘18和30位于基板12上。有源结合焊盘20和28位于集成电路14的边缘部分上,球焊34和50分别依次位于有源结合焊盘20和28上。有源结合引线54的一端通过自动点焊连接至封装结合焊盘18,且另一端通过球焊34连接至有源结合焊盘20。同样,有源结合引线66的一端通过自动点焊连接至封装结合焊盘30,且另一端通过球焊50连接至有源结合焊盘28。结合引线54和66的结合通过传统方式实现。
封装集成电路10还包括额外的球焊、结合引线和结合焊盘。热结合焊盘22位于集成电路14上。热结合引线56通过球焊36连接至热结合焊盘22。热结合引线56从集成电路14的表面垂直延伸到塑料密封体16的顶面。在集成电路14上的热结合焊盘24上具有球焊38和钉柱形凸起40。热结合引线58从球焊38垂直延伸至塑料封装体16的表面,被弯曲以具有沿塑料密封体16表面的一部分,并向下弯曲以自动点焊至柱形凸起40。这样就形成了两端都连接至热结合焊盘24并且中间部分暴露在塑料密封体16的表面的环路引线。作为替换,球焊38和柱形凸起40可以设置在两个分离的热结合焊盘上而不是设置在一个热结合焊盘24上。在集成电路14上的热结合焊盘26上具有球焊42、球焊44和球焊46。热结合引线60、热结合引线62和热结合引线64分别通过球焊42、44和46连接至热结合焊盘26。热结合引线60、62和64也从热结合焊盘26垂直延伸至塑料密封体16的表面并在那里被暴露。这些热结合引线的优点是它们可以通过传统的引线结合设备设置成如图1所示的那样。这些热结合引线的优点是,当需要从集成电路要求更强散热的部分消去热量时,它们可以配置在集成电路14的表面。
球焊36连接至热结合焊盘22。在塑料密封体16成型前,形成热结合引线56并截成理想的高度。球焊42连接至热结合焊盘26。在塑料密封体16成型前,形成热结合引线60并截成理想的高度。球焊44连接至热结合焊盘26。在塑料密封体16成型前,形成热结合引线62并截成理想的高度。球焊46连接至热结合焊盘26。在塑料密封体16成型前,形成热结合引线64并截成理想的高度。
柱形凸起40形成在热结合焊盘24上。球焊38形成在热结合焊盘24上。热结合引线58弯曲成型并且通过自动点焊终结于柱形凸起40。安装在基板12上的集成电路14被随后插入熔化了塑料的模具中,以形成塑料密封体16。使用传统引线结合设备精确将热结合引线56、60、62和64的高度切割至模具的高度。同样,热结合引线58的环路可以通过传统引线结合设备精确成型。由于向模具中注入塑料导致了热结合引线56、58、60、62和64的一些移动而出现一定的线偏移(sweep)。可以延长热结合引线56、58、60、62和64的长度以补偿这些偏移或任何其他变化以确保在密封体形成后暴露出它们。
热结合引线56、58、60、62和64具有暴露端,由此存在从集成电路管芯14到塑料密封体16表面的稳定热传导。由于热结合引线56、58、60、62和64具有高导热性,尤其是与例如密封体16的塑料材料相比,因此热量可以通过传导到外界环境中而散失。这样,由于热结合引线56、58、60、62和64的存在,theta-JC有了显著的改善。热结合引线56、58、60、62和64没有连接到有源电路,因此它们是电浮置的。在这种情况下,即使由于偏移或其他原因使得它们彼此接触,也不会对电信号处理产生危害。不连接至任何的有源电路的热引线56、58、60、62和64能够起作用是一个显著的优点。当结合引线扩展至集成电路边缘区域内时,偏移是一个值得注意的问题。
在典型的塑料密封工艺中,在表面上存在薄树脂层。如果热结合引线56、58、60、62和64的希望被暴露的表面被树脂覆盖,那么仍然保持了很多有益的散热效果。因此,仍需要考虑仅使用树脂覆层。即使存在几百条垂直结合引线,所述垂直结合引线的附加成本也很低。热结合引线非常短小。集成电路14上方的塑料密封体16的高度大约只有0.8毫米,并且热结合引线的直径为,例如大约只有0.02毫米。这样,尽管结合引线一般为金线,即使对于上百条结合引线,使用的总量也很小。虽然,由于引脚引出的限制,用于传输信号和电源的结合引线理想地具有较小的直径,但是热结合引线可以比较粗以改善散热性能。使用不同直径引线的缺点是需要更换引线结合器的线或移动到不同的引线结合器。
图2中示出的封装集成电路10具有位于塑料密封体16的顶面上散热器68。散热器68与热结合引线56、58、60、62和64暴露的部分接触以增强散热。如果薄层密封树脂形成在热引线56、58、60、62和64的垂直端,它可以优选通过抛光塑料密封体16顶面的方法移除,但也可以通过例如化学清除的其他方法移除。即使在存在树脂的情况下,由于散热器68也可以具有良好的热传导性,因此可以不移除树脂。移除树脂达到的改善程度与移除树脂所需成本不匹配,因此不值得移除树脂。
图3中示出了封装集成电路10的顶视图。除图1示出的特征外,封装集成电路10还包括热区域96、热区域98和热区域99以及附加的有源结合引线82、84和67,以及相关的有源结合焊盘78、80和49,以及封装结合焊盘74、76和31。图3中还示出了由热结合焊盘22、热结合引线56和球焊36组成的热区域90。同样,热区域92包含热结合焊盘24、球焊38,以及具有反向针脚40的球焊以及热结合引线58。热区域94包含热结合焊盘26、球焊42、44和46,以及热结合引线60、62和64。热区域99包含热结合焊盘27、球焊47和结合引线65。热区域99描绘了位于边缘区域70而不必须位于管芯电路区域72内的热区域。热区域96和98没有详细示出,但它们可以与热区域90、92、94和99的其中之一相同的方式形成。整个集成电路不需要具有热区域,但是热区域可以简单的设置在需要的位置。将热区域只设置在需要额外散热的那些位置可以节省时间和材料。延伸入管芯电路区域72的结合引线67优选为绝缘线以避免接触到其他引线。为了便于理解而简化了封装的集成电路10,应该理解可以存在比图中更多得的结合引线的连接。
图4中示出的封装集成电路100包括封装基板112、位于封装基板112上的集成电路114、集成电路114上的塑料密封体116、与集成电路204相邻的基板112的一部分以及位于塑料密封体116上的散热器139。有源结合引线124通过球焊122连接至有源结合焊盘120并且通过点焊结合连接至封装结合焊盘118。有源结合引线132通过球焊130连接至有源结合焊盘128并且通过点焊结合连接至封装结合焊盘126。热区域包括位于集成电路114上的热结合焊盘134,多个位于热结合焊盘134上的球焊136,以及多个热结合引线138。电源线142通过点焊结合连接在散热器139和位于封装基板112上的封装结合焊盘140之间。同样,电源线146通过点焊结合连接在散热器139和位于封装基板112上的封装结合焊盘144之间。这种情况下,散热器139不仅用作散热器也用作电源,它可以是地连接或连接至VDD。例如,散热器139可以用作地线屏蔽。在任何情况下,集成电路114的整个中心部分可以被热区域覆盖,这是因为所有位置都有电源,而且他们可施加到集成电路114的表面。设置完散热器139之后将设置电源线142和146,可以使用比密封的结合引线的直径大很多的引线来用于连接。
图5中示出的封装集成电路200包括封装基板202、半导体管芯204、散热器226和塑料密封体224以及结合焊盘、结合引线、球焊和柱形凸起。封装结合引线212通过球焊210连接在集成电路204上的有源结合焊盘208和封装基板202上的封装结合焊盘206之间。同样,封装结合引线220通过球焊216连接在集成电路204上的有源结合焊盘216和封装基板202上的封装结合焊盘214之间。多个热结合焊盘223位于集成电路204上。多个柱形凸起222位于热结合焊盘223上。散热器226位于多个柱形凸起222上。柱形凸起222被制作为传统的柱形凸起。在引线结合之后以及形成塑料密封体224之前,散热器226被设置在多个柱形凸起222上。
这样,通过使引线或柱形凸起垂直向上,可以得到一个简便的降低theta-JC的方法。其被暴露或连接至散热器。它们不需要延伸到集成电路边缘外并且可以很短以避免偏移带来的问题。垂直方向的热传导器比侧向热传导器或引线提供了从集成电路表面到密封封装外部的更有效的更短的导热路径。
以上参照特定实施例介绍了好处、其他优点和对问题的解决方案。但是,好处、优点、对问题的解决方案以及可以引起任何好处、优点或解决方案发生或使其变得突出的任何因素不构成任何或所有权利要求的关键、所需或必要特征或因素。如这里所使用的,术语“包括”、“包含”或任何其变型意指涵盖非排他性的包括,因此,包括一系列元素的工艺、方法、产品或设备不仅包括那些元素,而且还包括没有明显列出或这些工艺、方法、产品或设备所固有的其他元素。

Claims (16)

1.一种封装集电路,包括:
位于基板上的半导体管芯,该半导体管芯包括多个位于有源电路上的热结合焊盘;
多个热结合引线,所述热结合引线包括金,该多个热结合引线中的每一个都连接至所述多个热结合焊盘中的至少一个,所述多个热结合引线中的每一个都从半导体管芯向上延伸,并且以不会延伸超出半导体管芯的周界的方式终结;
包围所述半导体管芯、所述多个热结合焊盘和所述多个热结合引线的密封体,所述多个热结合引线将热量从所述半导体管芯传导到所述密封体的上表面,每个所述热结合引线都有一端暴露在所述密封体的上表面;以及
散热器,与所述热结合引线的暴露端接触。
2.如权利要求1所述的封装集成电路,其中所述多个热结合引线中的至少一个通过从两个热结合焊盘中的第一个远离半导体管芯表面地延伸并且朝半导体管芯表面返回以连接至所述两个热结合焊盘中的第二个,从而连接至所述两个热结合焊盘。
3.如权利要求1所述的封装集成电路,还包括:
位于所述多个热结合引线中的至少一个上的至少一个传导散热器,用于从所述多个热结合引线中的所述至少一个传导热量,以及散发来自该封装集成电路的热量。
4.如权利要求1所述的封装集成电路,其中所述多个热结合焊盘中的一部分没有连接至半导体管芯内的任何有源电路。
5.如权利要求4所述的封装集成电路,其中所述部分基本上是所述多个热结合焊盘的全部。
6.如权利要求1所述的封装集成电路,其中所述多个热结合焊盘连接至有源电路内的电源或接地端。
7.如权利要求1所述的封装集成电路,还包括:
多个有源结合焊盘,被放置在焊盘环区域内的半导体管芯的边缘附近,并且电连接至半导体管芯周界外的各个封装结合焊盘。
8.一种封装集成电路,包括:
位于基板上的半导体管芯;
位于半导体管芯上的多个具有相关电气功能的有源结合焊盘和多个不具有相关电气功能的热结合焊盘;
连接至多个热结合焊盘中的每一个的一个或多个热传导器,所述多个热传导器中的每一个都从半导体管芯向上延伸,并且包括多个导电柱形凸起或多个热结合引线;
包围半导体管芯、多个热结合焊盘、多个有源结合焊盘和一个或多个热传导器的密封体,所述热传导器将热量从半导体管芯传导到密封体的上表面,每个所述热传导器都有一部分暴露在所述上表面;以及
散热器,与所述热传导器的暴露端接触。
9.如权利要求8所述的封装集成电路,其中所述一个或多个热传导器中的至少一个包括热结合引线,该热结合引线从所述多个热结合焊盘中的第一个远离半导体管芯地延伸并且朝半导体管芯返回,由此连接至所述多个热结合焊盘中的第二个。
10.如权利要求8所述的封装集成电路,还包括:
位于所述一个或多个热传导器中的至少一个上的至少一个传导散热器,用于从所述一个或多个热传导器传导热。
11.如权利要求8所述的封装集成电路,其中传导散热器是传导电源电压或地参考电位的信号导体。
12.如权利要求8所述的封装集成电路,其中所述多个有源结合焊盘设置在该封装集成电路的边缘区域内,并且所述多个热结合焊盘设置于该封装集成电路的中心区域内,所述一个或多个热传导器不延伸超出半导体管芯的边缘。
13.一种封装集成电路的方法,包括:
提供半导体管芯,该半导体管芯包含多个具有相关电气功能的有源结合焊盘并包含多个热结合焊盘;
将所述多个热结合焊盘置于半导体管芯的内部区域内;
将半导体管芯置于基板上;
连接一个或多个热传导器至所述多个热结合焊盘中的每一个,所述一个或多个热传导器中的每一个从半导体管芯向上延伸,所述一个或多个热传导器中的每一个不延伸超出半导体管芯的边缘;
用密封体包围所述半导体管芯、所述多个热结合焊盘、所述多个有源结合焊盘和所述一个或多个热传导器,从而允许热传导器将热量从半导体管芯传导到密封体的上表面;以及
在包围所述半导体管芯的步骤之后,使传导散热器与所述一个或多个热传导器接触,以从所述一个或多个热传导器传导热量。
14.如权利要求13所述方法,其中:
使传导散热器与所述一个或多个热传导器中的至少一个接触是为了用作信号导体,以用于通过所述一个或多个热传导器中的至少一个将电源电压传导至半导体管芯或将地参考电位提供至半导体管芯。
15.如权利要求13所述方法,还包括:
将所述多个有源结合焊盘中的至少一个设置于半导体管芯的中心区域内,并将所述多个有源结合焊盘中的剩余部分设置于半导体管芯的边缘区域内。
16.如权利要求13所述方法,其中所述连接一个或多个热传导器至所述多个热结合焊盘中的每一个的步骤包括:
提供所述一个或多个热传导器中的至少一个作为热结合引线,该热结合引线在密封体内形成环路并且与所述多个热结合焊盘中的一个或多个接触,该环路到达到密封体的上表面。
CN2006800277751A 2005-07-29 2006-07-25 具有增强散热功能的封装集成电路 Active CN101548377B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/192,525 2005-07-29
US11/192,525 US7355289B2 (en) 2005-07-29 2005-07-29 Packaged integrated circuit with enhanced thermal dissipation
PCT/US2006/028837 WO2007016088A2 (en) 2005-07-29 2006-07-25 Packaged integrated circuit with enhanced thermal dissipation

Publications (2)

Publication Number Publication Date
CN101548377A CN101548377A (zh) 2009-09-30
CN101548377B true CN101548377B (zh) 2011-03-09

Family

ID=37693411

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800277751A Active CN101548377B (zh) 2005-07-29 2006-07-25 具有增强散热功能的封装集成电路

Country Status (7)

Country Link
US (2) US7355289B2 (zh)
EP (1) EP1913633B1 (zh)
JP (1) JP5149178B2 (zh)
KR (1) KR20080044235A (zh)
CN (1) CN101548377B (zh)
TW (1) TWI441290B (zh)
WO (1) WO2007016088A2 (zh)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061096B2 (en) * 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
US9299634B2 (en) * 2006-05-16 2016-03-29 Broadcom Corporation Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages
US7967062B2 (en) * 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
US9013035B2 (en) * 2006-06-20 2015-04-21 Broadcom Corporation Thermal improvement for hotspots on dies in integrated circuit packages
KR100761861B1 (ko) * 2006-10-11 2007-09-28 삼성전자주식회사 정전기를 방지하는 반도체 패키지
US20080122122A1 (en) * 2006-11-08 2008-05-29 Weng Fei Wong Semiconductor package with encapsulant delamination-reducing structure and method of making the package
US7719122B2 (en) * 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR101030990B1 (ko) * 2008-12-31 2011-04-22 삼성에스디아이 주식회사 반도체 패키지 및 이를 구비하는 플라즈마 디스플레이 장치
KR101030991B1 (ko) * 2008-12-31 2011-04-22 삼성에스디아이 주식회사 반도체 패키지의 장착구조 및 이를 적용한 플라즈마 디스플레이 장치
US8314483B2 (en) 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
US8222722B2 (en) * 2009-09-11 2012-07-17 St-Ericsson Sa Integrated circuit package and device
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US20120032350A1 (en) * 2010-08-06 2012-02-09 Conexant Systems, Inc. Systems and Methods for Heat Dissipation Using Thermal Conduits
US8791015B2 (en) * 2011-04-30 2014-07-29 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over active surface of semiconductor die
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9082633B2 (en) * 2011-10-13 2015-07-14 Xilinx, Inc. Multi-die integrated circuit structure with heat sink
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
US9768137B2 (en) 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8927345B2 (en) 2012-07-09 2015-01-06 Freescale Semiconductor, Inc. Device package with rigid interconnect structure connecting die and substrate and method thereof
US8669655B2 (en) * 2012-08-02 2014-03-11 Infineon Technologies Ag Chip package and a method for manufacturing a chip package
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9070653B2 (en) 2013-01-15 2015-06-30 Freescale Semiconductor, Inc. Microelectronic assembly having a heat spreader for a plurality of die
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9287227B2 (en) * 2013-11-29 2016-03-15 STMicroelectronics (Shenzhen) R&D Co. Ltd Electronic device with first and second contact pads and related methods
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9735084B2 (en) * 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9831150B2 (en) 2015-03-11 2017-11-28 Toshiba Memory Corporation Semiconductor device and electronic device
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
JP2017092212A (ja) * 2015-11-09 2017-05-25 株式会社東芝 半導体装置およびその製造方法
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9984992B2 (en) * 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10804185B2 (en) * 2015-12-31 2020-10-13 Texas Instruments Incorporated Integrated circuit chip with a vertical connector
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10153224B2 (en) 2016-09-14 2018-12-11 Globalfoundries Inc. Backside spacer structures for improved thermal performance
US10811334B2 (en) 2016-11-26 2020-10-20 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure in interconnect region
US10256188B2 (en) 2016-11-26 2019-04-09 Texas Instruments Incorporated Interconnect via with grown graphitic material
US11676880B2 (en) 2016-11-26 2023-06-13 Texas Instruments Incorporated High thermal conductivity vias by additive processing
US10861763B2 (en) 2016-11-26 2020-12-08 Texas Instruments Incorporated Thermal routing trench by additive processing
US11004680B2 (en) 2016-11-26 2021-05-11 Texas Instruments Incorporated Semiconductor device package thermal conduit
US10529641B2 (en) 2016-11-26 2020-01-07 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure over interconnect region
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN108091620B (zh) * 2017-12-20 2020-08-25 联想(北京)有限公司 一种芯片结构及电子设备
US20190214327A1 (en) * 2018-01-10 2019-07-11 Sonja Koller Thermal conduction devices and methods for embedded electronic devices
US10580715B2 (en) * 2018-06-14 2020-03-03 Texas Instruments Incorporated Stress buffer layer in embedded package
US10892229B2 (en) 2019-04-05 2021-01-12 Nxp Usa, Inc. Media shield with EMI capability for pressure sensor
US11127645B2 (en) * 2019-06-19 2021-09-21 Nxp Usa, Inc. Grounding lids in integrated circuit devices
US11742253B2 (en) * 2020-05-08 2023-08-29 Qualcomm Incorporated Selective mold placement on integrated circuit (IC) packages and methods of fabricating
US11545411B2 (en) * 2020-07-28 2023-01-03 Qualcomm Incorporated Package comprising wire bonds configured as a heat spreader
US11973010B2 (en) 2020-12-04 2024-04-30 Richtek Technology Corporation Chip packaging method and chip package unit
US11817366B2 (en) 2020-12-07 2023-11-14 Nxp Usa, Inc. Semiconductor device package having thermal dissipation feature and method therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6707140B1 (en) * 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265321A (en) * 1992-09-22 1993-11-30 Microelectronics And Computer Technology Corporation Integrated circuit structure with heat exchanger elements secured thereto and method of making
KR100386061B1 (ko) * 1995-10-24 2003-08-21 오끼 덴끼 고오교 가부시끼가이샤 크랙을방지하기위한개량된구조를가지는반도체장치및리이드프레임
EP0786806A1 (en) * 1996-01-23 1997-07-30 Montpellier Technologies High I/O density package for high power wire-bonded IC chips and method for making the same
JPH11204679A (ja) * 1998-01-08 1999-07-30 Mitsubishi Electric Corp 半導体装置
US6597065B1 (en) * 2000-11-03 2003-07-22 Texas Instruments Incorporated Thermally enhanced semiconductor chip having integrated bonds over active circuits
US6396699B1 (en) * 2001-01-19 2002-05-28 Lsi Logic Corporation Heat sink with chip die EMC ground interconnect
JP3632960B2 (ja) * 2001-11-27 2005-03-30 京セラ株式会社 半導体装置
JP2004200316A (ja) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd 半導体装置
TW578282B (en) * 2002-12-30 2004-03-01 Advanced Semiconductor Eng Thermal- enhance MCM package
US20050010989A1 (en) * 2003-07-15 2005-01-20 Hankins Gerald Wayne Dress shirt without sleeve portions
TWI376756B (en) 2003-07-30 2012-11-11 Taiwan Semiconductor Mfg Ground arch for wirebond ball grid arrays
US7088009B2 (en) 2003-08-20 2006-08-08 Freescale Semiconductor, Inc. Wirebonded assemblage method and apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6707140B1 (en) * 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration

Also Published As

Publication number Publication date
US7572680B2 (en) 2009-08-11
US7355289B2 (en) 2008-04-08
EP1913633A4 (en) 2010-04-14
US20080136016A1 (en) 2008-06-12
US20070023880A1 (en) 2007-02-01
EP1913633B1 (en) 2018-11-14
WO2007016088A3 (en) 2009-04-30
KR20080044235A (ko) 2008-05-20
JP5149178B2 (ja) 2013-02-20
TWI441290B (zh) 2014-06-11
EP1913633A2 (en) 2008-04-23
JP2009503865A (ja) 2009-01-29
WO2007016088A2 (en) 2007-02-08
TW200707682A (en) 2007-02-16
CN101548377A (zh) 2009-09-30

Similar Documents

Publication Publication Date Title
CN101548377B (zh) 具有增强散热功能的封装集成电路
US6432750B2 (en) Power module package having insulator type heat sink attached to rear surface of lead frame and manufacturing method thereof
US8018072B1 (en) Semiconductor package having a heat spreader with an exposed exterion surface and a top mold gate
US20030011054A1 (en) Power module package having improved heat dissipating capability
US20080061413A1 (en) Semiconductor component having a semiconductor die and a leadframe
CN101971332A (zh) 包括嵌入倒装芯片的半导体管芯封装
US20100252918A1 (en) Multi-die package with improved heat dissipation
JP4075204B2 (ja) 積層型半導体装置
US8643172B2 (en) Heat spreader for center gate molding
US7573141B2 (en) Semiconductor package with a chip on a support plate
US4012768A (en) Semiconductor package
WO2006074312A2 (en) Dual flat non-leaded semiconductor package
CN108417499A (zh) 空腔封装结构及其制造方法
US6160311A (en) Enhanced heat dissipating chip scale package method and devices
JP2845488B2 (ja) 半導体集積回路装置
CN113451244A (zh) 双面散热的mosfet封装结构及其制造方法
CN108735614B (zh) 半导体装置及半导体装置的制造方法
KR20140074202A (ko) 반도체 장치 및 그 제조 방법
CN219286398U (zh) 功率半导体封装结构
CN213242543U (zh) 一种增加芯片面积的引线框架封装结构
KR100763966B1 (ko) 반도체 패키지 및 이의 제조에 사용되는 리드프레임
KR100444170B1 (ko) 반도체패키지
TWI253731B (en) Semiconductor package
KR100250148B1 (ko) 비지에이 반도체 패키지
KR200167587Y1 (ko) 반도체 패캐이지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP America Co Ltd

Address before: Texas in the United States

Patentee before: Fisical Semiconductor Inc.

CP01 Change in the name or title of a patent holder