TWI253731B - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
TWI253731B
TWI253731B TW093133649A TW93133649A TWI253731B TW I253731 B TWI253731 B TW I253731B TW 093133649 A TW093133649 A TW 093133649A TW 93133649 A TW93133649 A TW 93133649A TW I253731 B TWI253731 B TW I253731B
Authority
TW
Taiwan
Prior art keywords
heat dissipating
semiconductor package
substrate
dissipating component
heat
Prior art date
Application number
TW093133649A
Other languages
Chinese (zh)
Other versions
TW200616187A (en
Inventor
Yi-Shao Lai
Jun-Cheng Liu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093133649A priority Critical patent/TWI253731B/en
Application granted granted Critical
Publication of TWI253731B publication Critical patent/TWI253731B/en
Publication of TW200616187A publication Critical patent/TW200616187A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package includes a substrate, a die mounted on the substrate, a heat slug, and an encapsulation. The heat slug has a top cover portion having a cavity, and a structure-fixing device positioned in the cavity for fixing the structure of the heat slug, wherein the structure-fixing device is formed with pluralities of crossed grooves.

Description

^3731 九、發明說明： 【發明所屬之技術領土或 本發明提供一種丰篆_ 土 a 種具有結構強化 千蛤體封裝件，尤指 件之散熱元件的半導體封裝件。 【先前技術】 在現代資訊社會中，積體電路以 及輕巧的體積’早已成為數位時代不的貧料處理功能 訊家電、個人電腦到處理繁雜訊號的中:缺的產品。從資 等，無不可見積體電路的縱跡。—邊據交換系統等 裝於一個封裝件中，苴又來說，積體電路都封 具犯保護積體電敗士 路，同時也提供積體電路電連至外邙卞中脆弱的電子電 電路能由外部電路取得带 卩包路的途徑，使積體 甩你供應，鱼 並將接地的電流傳導至外部電路。>、卜°卩電路交換資訊， 體電路一個散熱的介面。尤其對今=外，封裝件也提供積 内部電晶體、邏輯閘的個數都非常夕的積體電路來說’其 脈頻率也很高，如何消散積體電=’積體電路運作的時 量，也是封裝件設計時的重要考量作時產生的大量熱 1253731 在多種封裝方式中，球格陣列(ball grid array, BGA)封裝 技術已被廣泛應用於積體斷路的封裝製程中，其能大幅增 加半導體封裝件的封袭腳數(_ e_)。然而—般騰封 裝件的散熱途徑較長，因此t晶片上的電子元件增加而隨 之產生n4 ’其散熱效率便不敷所需。目前業界之 因應方式祕金屬製的散熱4設於賴件巾，讀高散熱 效率。 一立月 > 考第1圖’第i圖為習知—BGA封裝體、。的剖面 θ白头BGA封裝體10包含有一基板12,其具有-:面以及-下表面。在基板12之上表面設有一晶粒Μ， _ 3著層黏貼在基板12上。腸封裝件1〇另包 有後數條導線18，以鍟 塾（圖未视絲12，* 祕L 12上的銲 下# 土 並經由基板12而與設於基板12之 板數個辉球20電連接。為了提高散熱效率，在基 上方 :面先疋位一散熱片22，設於晶粒14之周圍及 24，费_進仃㈣作業，於基板上表面形成—封裝膠體 22 ^日粒14以及部分散熱片22，並使部分散熱片 卜路’以將晶粒Η的熱量快速逸散至大氣中。 1253731 請參考第2圖，第2圖為第1圖所示之散熱片22的俯 視示意圖。習知散熱片22包含有一支撐部26以及一上蓋 部28，而上蓋部28具有一凹穴30，當散熱片22設置於 BGA封裝件10之中時，凹穴30會較接近於晶粒14之表 面，藉以提高散熱效果。此外，散熱片22另包含有複數個 切槽32，因此在進行灌模時，膠體得經由切槽32流入上 蓋部28之下側，以覆蓋保護晶粒14以及導線18。然而， 在習知BGA封裝件10進行模壓作業時，常發生因合模壓 力而壓迫到散熱片22，使得凹穴30向上凸起，如第3圖 所示之圓圈標示處。在此情況下，凸起之散熱片22不僅會 影響到BGA封裝件10的外觀，亦會影響到其散熱功能。 此外，在習知半導體封裝件中，亦有將散熱片22之凹 穴3 0設計成極接近晶粒14或與晶粒14之頂表面相接觸’ 以提高晶粒14的散熱效果。然而，與晶粒14相接觸的散 熱片22仍然會因為合模壓力而變形，不僅無法達到預期散 熱效果，更進一步導致散熱片22可能擠壓晶粒14而使晶 粒14細壞。 【發明内容】 1253731 因此本發明之主要目的在於提供一種半導體封裝件，其 所包含之散熱元件具有結構強化件，以解決上述習知半導 體封裝件在封膠製程中造成散熱片變形的問題。 根據本發明之申請專利範圍，係揭露一種半導體封裝 件’其包含有一基板、^設於基板上表面之晶粒、一設於 基板以及晶粒之上的散熱元件(heat slug)以及一封裝膠 體。散熱元件係具有一凹穴(cavity)，位於散熱元件之一上 蓋部，且散熱元件另包含有一由複數條交錯之溝槽所構成 的結構強化件，設於凹穴之中，用以強化散熱元件之結構。 而封裝膠體係包覆晶粒、基板之至少一部份上表面以及部 分散熱元件，並顯露部分上蓋部於半導體封裝件表面。 由於本發明之散熱元件包含有由複數條交錯之溝槽所構 成的結構強化件，因此能使上蓋部之凹穴具有較堅固之結 構，在灌模時不致因為合模壓力而變形，可以確保散熱元 件之散熱效果。 【實施方式】 請參考第4圖與第5圖，第4圖為本發明半導體封裝件 1253731 5〇的剖面示意圖，第5圖則 #、目—立θ 勺弟4圖所不散熱兀件60的 俯視不思圖。半導體封裝件 ^^^ ςο 係為一 bga封裝件，包含 ^ ^ m 58、一散熱元件60 以及一封裝膠體62。基板52复右一 .^ a , 、有一上表面52a以及一下 =;广4則係藉由，％而固定於基板Μ = 上。各導線58係電性連接於晶粒54之銲墊（圖 未示）以及基板52。散熱元 干！1口 …、 係设於基板52以及晶粒 .·且具有一較接近晶教54之上表面的凹穴64，豆 係由導熱_佳之材料所製成，例如金屬銅，以提供半導 體封裝件5G &佳之散熱效能。封裝㈣62係設於基板52 之上表面52&上’覆蓋住晶粒54、導線58以及部分之散 熱兀件6〇 ’其材料一般為環氧樹脂(glass epoxy)。半導體 子衣件另包含有複數個銲球66設於基板52的下表面 ⑽，分別藉由基板兄電連接於晶粒54，以提供晶粒54 與外邛元件電連接以及交換資訊之路徑。 第5圖所示之散熱元件60係為一散熱片結構，包含有 有上| °卩％、複數個支撐部68以及一連結部72，其係 為一體成型之結構體。上蓋部7G係為散熱元件6〇之頂表 面其形狀為圓形，設於散熱元件60之中央，且上蓋部 7〇之中心部分具有碟形之凹穴64 ;連結部72係連結於上 1253731 蓋部70之週緣，並與上蓋部70形成一容置空間76，用以 容置設於基板52上的晶粗54，且連結部72之底部為一片 狀物，設於散熱元件60之外緣部分，並約略平行於上蓋部 00 ;各支撐部68則係設於連詰部72的底部，分別為向下 突出於連結部72之底部下表面的突點，當散熱元件6〇設 於基板52上時，支撐部68會與基板52相接觸。在本實施 例中，散熱元件60具有四支撐部68 ’以平衡支撐散熱元 件60於基板52之上。散熱元件糾另包含有複數個形成開 口的切槽74，設於連結部72上，以使灌模製程時，部分 膠體得以經由切槽74流入容置空間76中以覆蓋晶粒54和 導線58，而未流入容置空間76之部分膠體則覆蓋住散熱 元件60的連結部72，暴露出上蓋部70。再者，散熱元件 60包含有一結構強化件76，設於凹穴64中。結構強化件 76係由複數條交錯的溝槽所構成，本實施例所示之結構強 化件76係由二垂直溝槽交錯形成一十字形圖案。結構強化 件76係藉由彼此不平行而交錯的溝槽，使得凹穴料具有 較堅固的結構，以強化散熱元件6〇。此外，由於凹穴料 係為上蓋部70中央一下凹之碟形結構，而結構強化件76 係為凹六64底部下凹之溝槽，因此結構強化件％、凹穴 76以及散熱元件可為一體衝壓所形成。 1253731 & 構強化件76的圖案也可由三條以上的溝槽所形成。 月’考第6圖’第6圖為本發明其他實施例之結構強化件 76 Hit的不意®。！)圈⑻顯示本發明另—實施例中結構 強化件的圖案’在此實關巾，結構強化件係由三溝槽 _ 78b、78(；所組成，溝槽78a、78b、78c係相交於一相 交點A ’且相交點A係設置於結構強化件所在的凹穴之中 2。圓剛顯示結構強化件的圖案係由四溝槽80相交 ;心點㈣形成，且中心點B亦位於凹穴之中 _顯示本發明又-實施例之結構強化件的圖案，： 於凹穴中。 構強化件係由複數條溝槽82、84所組成，且部〜、中結 係沿-第-直線方向平行排列，而另—部分之二/冓糟82 一第二直線方向平行排列，由於第一直線方内曰84係沿 直線方向，因此溝槽82、84*有複數個相°不平行第二 本發明之散熱元件所具有之結構強化件亦，廇 晶（flip_chip)球格陣列封裝件中，或其他具有_〜用於覆 之半導體封裝件中。相較於習知技術，本發明散熱气件 件之散熱元件具有一結構強化件， 設於散熱U Μ、 的凹穴中，能使散熱元件之凹穴具有較堅固之社文項喪命 本發明散熱元件之凹穴在半導體封裝件的灌槔:攝，闳此 、灸％申 11 1253731 以抵抗合模壓力而不致變形，以使散熱元件對於晶粒具有 較佳之散熱效果，進而確保半導體封裝件能有較佳之運 作。再者，本發明散熱元件的結構強化件亦可應用於習知 散熱片之凹穴極接近晶粒或與晶粒頂表面接觸的設計中， 以確保散熱片不會因合模壓力造成變形，而不會有損壞晶 片之疑慮。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 · 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知一 BGA封裝體的剖面示意圖。 第2圖為第1圖所示之散熱片的俯視示意圖。 第3圖為第1圖所示散熱片因合模壓力造成變形的剖面示 · 意圖。 第4圖為本發明半導體封裝件的剖面示意圖。 第5圖為第4圖所示散熱元件的俯視示意圖。 第6圖為本發明其他實施例之結構強化件之圖案的示意 圖。 12 1253731 【主要元件符號說明】 10 BGA封裝體 12 基板 14 晶粒 16 黏著層 18 導線 20 鲜球 22 散熱片 24 封裝膠體 26 支撐部 28 上蓋部 30 凹穴 32 切槽 50 半導體封裝件 52 基板 52a 基板之上表面 52b 基板之下表面 54 晶粒 56 黏著層 58 導線 60 散熱元件 62 封裝膠體 64 凹穴 66 鲜球 68 支撐部 70 上蓋部 72 連結部 74 切槽 76 容置空間 78a、 78b、78c、80 、82、84 溝槽^3731 IX. Description of the Invention: [Technical Territory to which the Invention pertains or the present invention provides a semiconductor package having a structurally strengthened Millennium body package, particularly a heat dissipating component. [Prior Art] In the modern information society, the integrated circuit and the light volume have long been the poor material processing functions of the digital age. The home appliances and personal computers are used to deal with complicated signals: the lack of products. From the capital, etc., there is no invisible trace of the integrated circuit. - According to the exchange system, etc., it is installed in a package. In other words, the integrated circuit is sealed with a protective integrated circuit, and the integrated circuit is electrically connected to the vulnerable electronic electric power in the outer casing. The road can be obtained by an external circuit with a bypass path, so that the product is supplied to you, and the fish conducts the ground current to the external circuit. >, 卩 卩 circuit exchange information, a thermal interface of the body circuit. Especially for the current = outside, the package also provides the integrated circuit of the internal transistor and the number of logic gates. The pulse frequency is also very high. How to dissipate the integrated body = 'the operation of the integrated circuit? The quantity is also an important consideration in the design of the package. A large amount of heat generated during the manufacture of 1253731. In a variety of packaging methods, ball grid array (BGA) packaging technology has been widely used in the assembly process of integrated circuit breaking, which can Significantly increase the number of footprints (_e_) in semiconductor packages. However, the heat dissipation path of the package is longer, so the number of electronic components on the t-chip increases and the resulting heat dissipation efficiency is insufficient. At present, the heat dissipation method of the metal in the industry is set in the towel, and the heat dissipation efficiency is high.一立月 > 考第1图' The i-th picture is a conventional-BGA package. The section θ whitehead BGA package 10 includes a substrate 12 having a -: face and a lower face. A die is provided on the upper surface of the substrate 12, and the layer is adhered to the substrate 12. The intestine package 1 〇 is additionally provided with a plurality of wires 18 to be 鍟塾 (the wire is not visible on the wire 12, * the secret on the L 12 and passes through the substrate 12 and the plate provided on the substrate 12 20 electrical connection. In order to improve the heat dissipation efficiency, above the base: a heat sink 22 is placed on the surface, and is placed around the die 14 and 24, and the operation is performed on the upper surface of the substrate - encapsulation 22 ^ The pellets 14 and a portion of the fins 22, and a portion of the fins are arranged to quickly dissipate the heat of the fins into the atmosphere. 1253731 Please refer to FIG. 2, and FIG. 2 is the fins 22 shown in FIG. The conventional heat sink 22 includes a support portion 26 and an upper cover portion 28, and the upper cover portion 28 has a recess 30. When the heat sink 22 is disposed in the BGA package 10, the recess 30 is closer. The surface of the die 14 is used to improve the heat dissipation effect. In addition, the heat sink 22 further includes a plurality of slots 32. Therefore, when the die is poured, the glue flows into the lower side of the upper cover portion 28 through the slot 32 to cover the protection. The die 14 and the wire 18. However, when the conventional BGA package 10 is molded, it is often The heat is forced to the heat sink 22 by the mold clamping pressure, so that the pocket 30 is convex upward, as indicated by the circle shown in Fig. 3. In this case, the raised heat sink 22 not only affects the BGA package 10 The appearance of the heat sink can also affect the heat dissipation function. In addition, in the conventional semiconductor package, the recess 30 of the heat sink 22 is also designed to be in close proximity to or in contact with the top surface of the die 14. In order to improve the heat dissipation effect of the die 14. However, the heat sink 22 in contact with the die 14 is still deformed by the clamping pressure, which not only fails to achieve the desired heat dissipation effect, but further causes the heat sink 22 to squeeze the die 14 Therefore, the main purpose of the present invention is to provide a semiconductor package having a heat dissipating member having a structural reinforcement member to solve the above-mentioned conventional semiconductor package in the encapsulation process. The problem of the deformation of the heat sink. According to the patent application of the present invention, a semiconductor package is disclosed which includes a substrate, a die disposed on the upper surface of the substrate, a substrate, and a crystal a heat slug on the particle and a package colloid. The heat dissipating component has a cavity, and is disposed on one of the heat dissipating components, and the heat dissipating component further comprises a plurality of interlaced grooves. The structural reinforcement member is disposed in the recess for reinforcing the structure of the heat dissipating component. The encapsulant system covers the die, at least a portion of the upper surface of the substrate, and a portion of the heat dissipating component, and exposes a portion of the upper cap portion to the semiconductor package Since the heat dissipating member of the present invention comprises a structural reinforcing member composed of a plurality of interlaced grooves, the recess of the upper cover portion can have a relatively strong structure, and is not deformed by the clamping pressure during the filling. It can ensure the heat dissipation effect of the heat dissipating component. [Embodiment] Please refer to FIG. 4 and FIG. 5, FIG. 4 is a schematic cross-sectional view of a semiconductor package of 1253331 according to the present invention, and FIG. 5 is a schematic diagram of the fifth embodiment of the semiconductor package. I don’t think about it. The semiconductor package ^^^ ςο is a bga package comprising ^ ^ m 58, a heat dissipating component 60 and an encapsulant 62. The substrate 52 has a right upper side, a top surface 52a and a lower side; and a wide area 4 is fixed on the substrate Μ = by %. Each of the wires 58 is electrically connected to a pad (not shown) of the die 54 and a substrate 52. Cooling element Dry! a port... is disposed on the substrate 52 and the die. and has a recess 64 closer to the upper surface of the crystal teacher 54. The bean is made of a thermally conductive material such as metallic copper to provide a semiconductor package. 5G & good heat dissipation performance. The package (4) 62 is disposed on the upper surface 52& of the substrate 52 to cover the die 54, the wire 58 and a portion of the heat dissipation member 6''. The material is generally glass epoxy. The semiconductor sub-assembly further includes a plurality of solder balls 66 disposed on the lower surface (10) of the substrate 52, and electrically connected to the die 54 by the substrate, respectively, to provide a path for the die 54 to be electrically connected to the external germanium component and to exchange information. The heat dissipating member 60 shown in Fig. 5 is a heat sink structure comprising upper | ° 卩 %, a plurality of support portions 68 and a joint portion 72 which are integrally formed structures. The top cover portion 7G is a top surface of the heat dissipating member 6 is circular in shape, and is disposed at the center of the heat dissipating member 60. The central portion of the upper cover portion 7 has a dish-shaped recess 64. The connecting portion 72 is coupled to the upper 1253731. The periphery of the cover portion 70 and the upper cover portion 70 form an accommodating space 76 for accommodating the crystal coarse 54 disposed on the substrate 52, and the bottom portion of the connecting portion 72 is a single piece disposed on the heat dissipating component 60. The outer edge portion is approximately parallel to the upper cover portion 00; each of the support portions 68 is disposed at the bottom of the flail portion 72, respectively, a protrusion projecting downwardly from the bottom lower surface of the joint portion 72, and the heat dissipating member 6 is disposed On the substrate 52, the support portion 68 is in contact with the substrate 52. In the present embodiment, the heat dissipating component 60 has four support portions 68' to balance the heat dissipating component 60 over the substrate 52. The heat dissipating component further includes a plurality of slits 74 forming openings, which are disposed on the joint portion 72 so that part of the colloid can flow into the accommodating space 76 via the slit 74 to cover the die 54 and the wire 58 during the molding process. A part of the gel that has not flowed into the accommodating space 76 covers the joint portion 72 of the heat dissipating member 60 to expose the upper lid portion 70. Furthermore, the heat dissipating member 60 includes a structural reinforcement member 76 disposed in the recess 64. The structural reinforcement member 76 is composed of a plurality of interlaced grooves. The structural reinforcement member 76 shown in this embodiment is formed by staggering two vertical grooves to form a cross-shaped pattern. The structural reinforcement 76 is a groove that is staggered by being non-parallel to each other, so that the pocket material has a relatively strong structure to reinforce the heat dissipating member 6''. In addition, since the pocket material is a dish-shaped structure in which the center of the upper cover portion 70 is concave, and the structural reinforcement member 76 is a groove recessed at the bottom of the recessed portion 64, the structural reinforcement member %, the recess 76, and the heat dissipating member may be Formed by one stamping. 1253731 & The pattern of the structural reinforcement 76 can also be formed by three or more grooves. Fig. 6 is a structural reinforcement member 76 Hit's Unintentional® according to another embodiment of the present invention. ! The circle (8) shows that the pattern of the structural reinforcement member in the other embodiment of the present invention is in this case, the structural reinforcement member is composed of three grooves _78b, 78 (; the grooves 78a, 78b, 78c intersect each other) The intersection point A ' and the intersection point A are disposed in the recess in which the structural reinforcement is located. 2. The pattern of the circular reinforcement structural reinforcement is intersected by the four grooves 80; the core point (4) is formed, and the center point B is also located in the concave Between the holes _ shows the pattern of the structural reinforcement of the further embodiment of the invention, in the recess. The structural reinforcement is composed of a plurality of grooves 82, 84, and the portion ~, the middle knot along the - first - The linear directions are arranged in parallel, and the other portions are arranged in parallel with each other in a second straight line direction. Since the first straight inner square 84 is in a straight line direction, the grooves 82 and 84* have a plurality of phases which are not parallel. The structural reinforcement of the heat dissipating component of the present invention is also used in a flip-chip ball grid array package or other semiconductor package for covering. Compared with the prior art, the present invention dissipates heat. The heat dissipating component of the pneumatic component has a structural reinforcement member disposed on the heat dissipation U In the recess, the recess of the heat dissipating component can be made stronger. The recess of the heat dissipating component of the invention is filled in the semiconductor package: photo, photo, moxibustion, 11 1253731, to resist the clamping The pressure is not deformed, so that the heat dissipating component has a better heat dissipation effect on the die, thereby ensuring better operation of the semiconductor package. Furthermore, the structural reinforcement of the heat dissipating component of the present invention can also be applied to the concave of the conventional heat sink. The design of the hole is very close to the die or in contact with the top surface of the die to ensure that the heat sink does not deform due to the clamping pressure without the doubt that the wafer is damaged. The above is only a preferred embodiment of the present invention. The equivalent changes and modifications made by the application of the present invention should be within the scope of the present invention. [Simplified Schematic] FIG. 1 is a schematic cross-sectional view of a conventional BGA package. It is a schematic plan view of the heat sink shown in Fig. 1. Fig. 3 is a cross-sectional view showing the deformation of the heat sink shown in Fig. 1 due to the clamping pressure. Fig. 4 is a schematic cross-sectional view showing the semiconductor package of the present invention. Fig. 5 is a schematic plan view of the heat dissipating member shown in Fig. 4. Fig. 6 is a schematic view showing the pattern of the structural reinforcing member according to another embodiment of the present invention. 12 1253731 [Description of main components] 10 BGA package 12 Substrate 14 Die 16 Adhesive layer 18 Conductor 20 Fresh ball 22 Heat sink 24 Encapsulant 26 Support portion 28 Upper cover portion 30 Pocket 32 Groove 50 Semiconductor package 52 Substrate 52a Substrate upper surface 52b Substrate lower surface 54 Grain 56 Adhesive layer 58 Conductor 60 Heat sink 62 Encapsulant 64 Pocket 66 Fresh ball 68 Support 70 Upper cover 72 Joint 74 Groove 76 Housing space 78a, 78b, 78c, 80, 82, 84 Groove

1313

Claims (1)

1253731 十、申請專利範圍： 1. 一種半導體封裝件，該半導體封裝件包含有： 一基板； 一晶粒，設於該基板之上表面； 一散熱元件(heat slug)，設於該基板以及該晶粒之上，該 散熱元件具有一凹穴(cavity)位於該散熱元件之一 上蓋部，且該散熱元件另包含有一由複數條交錯之 溝槽所構成的結構強化件，設於該凹穴之中，用以 強化該散熱元件之結構；以及 一封裝膠體，包覆該晶粒、該基板之至少一部份上表面 以及部分該散熱元件，並顯露部分該上蓋部於該半 導體封裝件表面。 2. 如申請專利範圍第1項之半導體封裝件，其中該上蓋部 係設於該散熱元件之中央。 3. 如申請專利範圍第1項之半導體封裝件，其中該散熱元 件另包含有： 一支撐部，設於該散熱元件之週緣，並與該基板相接觸； 以及 14 I25373l 連結部，連結於該上蓋部與 ^ Λ支棕部，且該連接部鱼 该上蓋部形成一容置空間， 、 J用以谷置該晶粒。 ，申請專利範圍第3項之半導體封裝件，其中該上蓋 部、該支禮部以及該連結部係為—體成型結構:。 .如申請專利範圍第3項之半導體封裝件， 體係覆蓋該支撐部以及該連結部。 其中該封裝膠1253731 X. Patent application scope: 1. A semiconductor package comprising: a substrate; a die disposed on an upper surface of the substrate; a heat slug disposed on the substrate and the Above the die, the heat dissipating component has a cavity on one of the heat dissipating components, and the heat dissipating component further comprises a structural reinforcement formed by a plurality of staggered trenches disposed in the recess a structure for reinforcing the heat dissipating component; and an encapsulant covering the die, at least a portion of the upper surface of the substrate, and a portion of the heat dissipating component, and exposing a portion of the capping portion to the surface of the semiconductor package . 2. The semiconductor package of claim 1, wherein the upper cover portion is disposed at a center of the heat dissipating member. 3. The semiconductor package of claim 1, wherein the heat dissipating component further comprises: a support portion disposed on a periphery of the heat dissipating component and in contact with the substrate; and a 14 I25373l connecting portion coupled to the The upper cover portion and the 棕 棕 brown portion, and the connecting portion of the fish portion forms an accommodating space for J to store the crystal grains. The semiconductor package of claim 3, wherein the upper cover portion, the brimming portion, and the connecting portion are body-shaped structures. The semiconductor package of claim 3, wherein the system covers the support portion and the joint portion. Where the encapsulant 其中該等溝槽 6·如申請專利範g第！項之半導體封裝件 係皆相交於一相交點。 體封裝件，其中該相交點 如申請專利範圍第6項之半導 係為該凹穴之中心點。Among these grooves 6 · as applied for patent g g! The semiconductor package of the item intersects at an intersection. The body package, wherein the intersection point is the center point of the pocket as in the sixth aspect of the patent application. ’其中部分之該 而另一部分之該 且该第一直線方 •如申請專利範圍第1項之半導體封裝件 等溝槽係沿一第一直線方向平行排列， 等溝槽係沿-第二直線方形平行排列， 向不平行於該第二直線方向。 9.如申請專利範圍第1項之半導體封裝件，其中該凹穴 15 1253731 該結構強化件以及該散熱元件係為一體沖壓構件。 10.如申請專利範圍第1項之半導體封裝件，其中該半導體 封裝件另包含有複數條導線，電性連接該晶粒以及該基 板0 11. 如申請專利範圍第1項之半導體封裝件，其中該半導體 封裝件另包含有複數個銲球，設於該基板之下表面並電 性連接該基板。 12. —種散熱元件，用來提供一半導體封裝件散熱之功能， 該散熱元件具有一碟形之凹穴，位於該散熱元件之一頂 表面，且該散熱元件另包含有一由複數條交錯之溝槽所 構成的結構強化件，設於該凹穴之中，用以強化該散熱 元件之結構。 13. 如申請專利範圍第12項之散熱元件，其中該等溝槽係 皆相交於一相交點。 11如申請專利範圍第13項之散熱元件，其中該相交點係 為該凹穴之中心點。 16 1253731 槽::ΓΓΓ 元件，其中部分該等溝 係㈣向平行_， 係沿-第二直線方向平行排列，且該第一直:;向= 行於該第二直線方向。 罝線方Θ不千 16.-種散熱片結構，適於設置於一基板上，以提升一 體元件之散熱效能，該散熱片結構包含： 、 -上^部’具有—凹穴以及至少—結構強化件位於該凹 穴中，且該結構強化件包含複數條溝槽，· 一連結部，連接於該上蓋部之週緣，並與該上蓋部形成 一上凸之容置空間；以及 複數個支撐部，連減魏結部，以㈣散熱片 撐於該基板上。 1 17·如申請專利範圍第16項之散熱片結構，其中該上莫邱 该支撐部以及該等連結部係為一體成型結構體。 18·如申請專利範圍第π項之散熱片結構，其中該散熱片 結構另包含有複數個開孔，設於該連結部上。 17 Ϊ253731 其中該等開孔 19.如申請專利範圍第18項之散熱片結構 係為複數個切槽。 2〇·如申請專利範圍第16項之散熱片結構，其中該凹穴、 該結構強化件以及該散熱片結構係為一體沖壓構件。 21.如申請專利範圍第16項之散熱片結構，其中該等溝槽 係皆相交於一相交點。 22·如申請專利範圍第22項之散熱片結構，其中該相交點 係為該凹穴之中心點。 23.如申請專利範圍第16項之散熱片結構，其中部分讀 溝槽係沿-第-直線方向平行排列，而另—部分該驾The part of the portion and the other portion of the first straight line. The trenches such as the semiconductor package of claim 1 are arranged in parallel along a first linear direction, and the grooves are parallel along the second straight square. Arranged, the direction is not parallel to the second straight line. 9. The semiconductor package of claim 1, wherein the recess 15 1253731 the structural reinforcement and the heat dissipating component are integral stamping members. 10. The semiconductor package of claim 1, wherein the semiconductor package further comprises a plurality of wires electrically connected to the die and the substrate 0. 11. The semiconductor package of claim 1 The semiconductor package further includes a plurality of solder balls disposed on a lower surface of the substrate and electrically connected to the substrate. 12. A heat dissipating component for providing a heat dissipation function of a semiconductor package, the heat dissipating component having a dish-shaped recess located on a top surface of the heat dissipating component, and the heat dissipating component further comprising a plurality of staggered A structural reinforcement formed by the groove is disposed in the recess for reinforcing the structure of the heat dissipating component. 13. The heat dissipating component of claim 12, wherein the trenches intersect at an intersection. 11 The heat dissipating component of claim 13, wherein the intersection point is a center point of the recess. 16 1253731 Slot:: 元件 Element, part of which is (4) parallel to _, parallel along the direction of the second straight line, and the first straight:; direction = in the direction of the second straight line. The heat sink structure is suitable for being disposed on a substrate to improve the heat dissipation performance of the integrated component. The heat sink structure comprises: - the upper portion has a recess and at least - a structure The reinforcing member is located in the recess, and the structural reinforcing member comprises a plurality of grooves, a connecting portion is connected to the periphery of the upper cover portion, and forms an upwardly accommodating receiving space with the upper cover portion; and a plurality of supports The Ministry, in addition to reducing the Wei junction, to (4) the heat sink is supported on the substrate. 1 17. The heat sink structure of claim 16, wherein the support portion and the joint portion are integrally formed structures. 18. The heat sink structure of claim π, wherein the heat sink structure further comprises a plurality of openings disposed on the joint. 17 Ϊ 253731 wherein the openings 19. The heat sink structure of claim 18 is a plurality of slots. 2. The heat sink structure of claim 16, wherein the recess, the structural reinforcement, and the heat sink structure are integral stamping members. 21. The fin structure of claim 16 wherein the trenches all intersect at an intersection. 22. The heat sink structure of claim 22, wherein the intersection point is a center point of the pocket. 23. The heat sink structure of claim 16, wherein the partial read grooves are arranged in parallel along the -first-linear direction, and the other portions are driven. 槽係沿-第二直線絲平行㈣，域第—直線以 平行於該第二直線方向。 18The groove system is parallel (four) along the second straight line, and the domain first line is parallel to the second straight line direction. 18
TW093133649A 2004-11-04 2004-11-04 Semiconductor package TWI253731B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093133649A TWI253731B (en) 2004-11-04 2004-11-04 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093133649A TWI253731B (en) 2004-11-04 2004-11-04 Semiconductor package

Publications (2)

Publication Number Publication Date
TWI253731B true TWI253731B (en) 2006-04-21
TW200616187A TW200616187A (en) 2006-05-16

Family

ID=37586700

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093133649A TWI253731B (en) 2004-11-04 2004-11-04 Semiconductor package

Country Status (1)

Country Link
TW (1) TWI253731B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI746939B (en) * 2019-01-22 2021-11-21 大陸商長江存儲科技有限責任公司 Integrated circuit packaging structure and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI746939B (en) * 2019-01-22 2021-11-21 大陸商長江存儲科技有限責任公司 Integrated circuit packaging structure and manufacturing method thereof
US11476173B2 (en) 2019-01-22 2022-10-18 Yangtze Memory Technologies Co., Ltd. Manufacturing method of integrated circuit packaging structure

Also Published As

Publication number Publication date
TW200616187A (en) 2006-05-16

Similar Documents

Publication Publication Date Title
US6919631B1 (en) Structures for improving heat dissipation in stacked semiconductor packages
US7361986B2 (en) Heat stud for stacked chip package
US9013035B2 (en) Thermal improvement for hotspots on dies in integrated circuit packages
US6566164B1 (en) Exposed copper strap in a semiconductor package
US7126218B1 (en) Embedded heat spreader ball grid array
EP1913633B1 (en) Packaged integrated circuit with enhanced thermal dissipation
US6853070B2 (en) Die-down ball grid array package with die-attached heat spreader and method for making the same
US6737755B1 (en) Ball grid array package with improved thermal characteristics
US6429513B1 (en) Active heat sink for cooling a semiconductor chip
CN108573936A (en) Semiconductor packages
US6673708B1 (en) Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill
JP4075204B2 (en) Multilayer semiconductor device
US7034385B2 (en) Topless semiconductor package
US8031484B2 (en) IC packages with internal heat dissipation structures
WO2006074312A2 (en) Dual flat non-leaded semiconductor package
KR101162503B1 (en) Heat slug and semiconductor package using the same
TWI253731B (en) Semiconductor package
JPH06349893A (en) Flip chip connection semiconductor package
KR101459566B1 (en) Heatslug, semiconductor package comprising the same heatslug, and method for fabricating the same semiconductor package
US9230874B1 (en) Integrated circuit package with a heat conductor
KR20040061860A (en) Tecsp
JP2003133512A (en) Resin-package type semiconductor device
KR100251889B1 (en) Semiconductor package
JP3058142B2 (en) Semiconductor device and manufacturing method thereof
KR20050011208A (en) Semiconductor chip package having heat sink and manufacturing method thereof