CN101517715B - 半导体外延结晶基板的制造方法 - Google Patents

半导体外延结晶基板的制造方法 Download PDF

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CN101517715B
CN101517715B CN2007800340622A CN200780034062A CN101517715B CN 101517715 B CN101517715 B CN 101517715B CN 2007800340622 A CN2007800340622 A CN 2007800340622A CN 200780034062 A CN200780034062 A CN 200780034062A CN 101517715 B CN101517715 B CN 101517715B
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dielectric
growth
semiconductor epitaxial
dielectric layer
crystal substrate
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CN101517715A (zh
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佐泽洋幸
西川直宏
秦雅彦
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Sumitomo Chemical Co Ltd
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Sumitomo Chemical Co Ltd
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Abstract

本发明提供一种具有低的栅极泄漏电流与小到可忽视的栅极滞后、漏极滞后、电流崩塌特性的、带电介质膜的氮化镓类半导体外延结晶基板。半导体外延结晶基板的制造方法是向通过有机金属气相生长法生长的氮化物半导体结晶层表面，赋与构成钝化膜或栅极绝缘膜并具有非结晶形的氮化物电介质或氧化物电介质的电介质层的制造方法，其中，在外延生长炉内使所述氮化物半导体结晶层生长之后，直接在该外延生长炉内使所述电介质层与所述氮化物半导体结晶层连续生长。

Description

半导体外延结晶基板的制造方法
技术领域
本发明涉及一种半导体外延结晶基板的制造方法。
背景技术
以往，将异质界面中产生的二维电子气体作为沟道的器件(GaN-MIS-HFET)在高频、高输出特性优良方面尤其引人注目。在制造这样氮化镓类晶体管的情况下，利用光刻技术来加工作为用于其的功能构件的半导体外延结晶基板，制作所需的晶体管，此时，根据目的，采用向半导体外延结晶基板施加了栅极绝缘膜、钝化膜等构件的器件方式。
栅极绝缘膜是为了防止栅极电极的泄漏电流而设置在栅极金属与半导体结晶之间的保护膜。已知一般形成于氮化物半导体中的肖特基电极表示比理论上预想的值大的泄漏电流，设置栅极绝缘膜来降低该泄漏电流。
另一方面，钝化膜是为了稳定化半导体表面以使该表面的电气性状不变化而设置在半导体结晶表面的保护膜。若半导体表面的电气性状变化，则器件动作时示出称为栅极滞后、漏极滞后、电流崩塌的过渡电流响应，存在引起输出降低或阈值电压的变动的问题，所以必要时设置钝化膜。
在设置这种保护膜的情况下，为了简化制造工序或降低制造成本，较多由相同材料将钝化膜与栅极绝缘膜构成为电介质膜。在现有方法中，这种电介质膜通过如下方法来形成，即，在由有机金属气相生长(MOCVD)法、分子束外延(MBE)法等外延结晶生长法生长后，从外延生长炉中取出基板，酸处理结晶表面等，除去表面的自然氧化物后，移至热CVD、等离子体CVD、cat-CVD等电介质制膜炉，积层至结晶表面。
例如，在P.Kordos等Applied Physics letters 87，143501(2005)中，公开了利用等离子体CVD法将SiO电介质赋与半导体表面的GaN-MISHFET。
在该例中，示出了通过赋与电介质膜而使栅极泄漏电流降低的实验结果。但是，在包含该方法在内的上述方法中，有可能产生如下所述的情况：无法完全除去半导体结晶与电介质膜界面的氧化膜；在GaN结晶表面发生氮孔腔而在该界面中电气地形成活性的中间准位导致以某时间常数响应于栅极信号或漏极电压的输入，从而引起漏极滞后或栅极滞后等现象。即，在现有方法中，基于赋与电介质膜的栅极滞后或漏极滞后的改善效果不充分，因此，实用化存在问题。
发明内容
本发明的目的在于提供一种能够解决上述问题的、赋与电介质膜的方式的半导体外延结晶基板及其制造方法。
本发明者等为了解决上述问题而积极研究的结果，直至完成本发明。即，本发明提供如下的(1)～(8)。
(1)一种半导体外延结晶基板的制造方法，向通过有机金属气相生长法生长的氮化物半导体结晶层表面，赋与构成钝化膜或栅极绝缘膜并具有非结晶形的氮化物电介质或氧化物电介质的电介质层，其中，在外延生长炉内使所述氮化物半导体结晶层生长之后，直接在该外延生长炉内使所述电介质层与所述氮化物半导体结晶层连续生长。
(2)以所述(1)记载的方法为基础，使用有机金属作为金属原料，使用乙醚或水作为氧原料，使用氨作为氮原料，并利用有机金属气相生长法使电介质层生长。
(3)以所述(2)记载的方法为基础，电介质层的至少一部分的生长为边供给作为5族原料的氨边进行。
(4)以所述(1)、(2)或(3)记载的方法为基础，电介质层的至少一部分的生长通过使用氮作为载气来进行。
(5)以所述(1)或(2)记载的方法为基础，电介质层包括从AlOx、AlOx:N(0.5＜x＜1.5)、SiO2、SiO2:N、Ga2O3、Si3N4、HfO2、HfxAlyO3(0＜x＜1、y＝2-1/2x)、HfxAlyO3:N(0＜x＜1、y＝2-1/2x)、GdO、ZrO2、MgO、Ta2O5中选择的至少一种电介质。
(6)以所述(1)或(2)记载的方法为基础，电介质层包括从Al2O3、Al2O3:N、SiO2、SiO2:N、Ga2O3、Si3N4、HfO2、HfxAlyO3(0＜x＜1、y＝2-1/2x)、HfxAlyO3:N(0＜x＜1、y＝2-1/2x)、GdO、ZrO2、MgO、Ta2O5中选择的至少一种电介质。
(7)以所述(1)～(6)中任一项记载的方法为基础，半导体外延结晶基板用于场效应晶体管。
(8)一种通过所述(1)～(6)中任一项的方法得到的半导体外延结晶基板。
附图说明
图1是本发明的半导体外延结晶基板的示意剖视图。
图2是本发明的半导体外延结晶基板的制造中使用的有机金属气相生长装置的概略图。
图3是实施例1的GaN-MISHFET的示意剖视图。
图4表示实施例1及比较例的GaN-MISHFET的栅极泄漏特性(栅极电压-栅极电流特性)。
图5表示实施例1及比较例的GaN-MISHFET的漏极滞后特性(漏极电压-漏极电流-时间特性)。
符号说明
1基底基板
2缓冲层
3沟道层
4电子供给层
5电介质层
6漏极电极
7栅极电极
8源极电极
9元件分离
10半导体外延结晶基板
100～104质量流量控制器
105、106恒温层
107、108原料容器
109～111高压储气瓶
112～114减压阀
200反应炉
201基板折叠机
202电阻加热机
203排气口
具体实施方式
图1是由本发明的制造方法得到的半导体外延结晶基板的示意剖视图。半导体外延结晶基板10是晶体管制造用的氮化镓类半导体外延结晶基板，在基底基板1上利用外延法使氮化镓半导体结晶层生长。氮化镓半导体结晶层按顺序包含AlN缓冲层2、GaN沟道层3及掺杂Si/不掺杂Si的电子供给层4。
在氮化镓半导体结晶层的表面上即电子供给层4的表面4a上生长规定厚度的、具有非结晶形的电介质层5。电介质层5是对氮化镓半导体结晶层的保护层，电介质层5在使用半导体外延结晶基板10制造的晶体管中，构成钝化膜或栅极绝缘膜。
在外延生长炉内且在基底基板1上使缓冲层2、沟道层3及电子供给层4依次生长之后，在外延生长炉内利用MOCVD在电子供给层4上生长电介质层5。作为可由MOVCD生长的电介质，可举出例如AlOx、AlOx:N(0.5＜x＜1.5)、Si3N4、SiO2、SiO2:N(包含N的SiO2)、MgO、GdO、ZrO2、HfO2、HfxAlyO3(0＜x＜1、y＝2-1/2x)、HfxAlyO3:N(包含N的HfxAlyO3)(0＜x＜1、y＝2-1/2x)、Ta2O5、MgO。AlOx优选Al2O3，AlOx:N(0.5＜x＜1.5)优选Al2O3:N。电介质层5也可例如向外延生长炉内导入3族原料气体，边导入氧气原料边利用MOCVD使所述电介质层生长。
如此得到的电介质层5在其作为钝化膜或栅极绝缘膜动作的情况下，不使晶体管的电气特性降低地实现良好的栅极泄漏特性。其结果，得到具有良好的栅极泄漏特性与小到可忽视的栅极滞后、漏极滞后、电流崩塌的半导体外延结晶基板。
说明本发明的制造方法的一实施方式。
图2是半导体外延结晶基板的制造中使用的MOCVD装置的示意图。在图2中，100～104是质量流量控制器(以下称为MFC)，105、106是恒温层，107、108是原料容器，109～111是高压储气瓶，112～114是减压阀，200是反应炉，201是电阻加热机，202是基板支架。向原料容器107中填充3族原料，向原料容器108中填充有机金属原料。向高压储气瓶111中填充氨，向高压储气瓶109中填充载气，向高压储气瓶110中填充氧气。
来自由MFC101控制流量的高压储气瓶109的载气被导入由恒温层105控制到所需温度的原料容器107内，在进入原料容器107内的3族原料中被起泡。通过起泡，原料容器107的上部空间被由恒温层107的温度确定的蒸气压的3族原料充满，对应于该蒸气压与载气流量的量的3族原料气体被导入反应炉200内。如此控制的3族原料的流量通常为10E-3～10E-5mol/min.。
填充到高压储气瓶111中的5族原料(氨等)被减压阀114减压，由MFC104控制流量，导入反应炉200内。5族原料(氨等)的量通常是3族原料气体的1倍～10000倍。
填充到高压储气瓶109中的载气被减压阀112减压，由MFC100控制流量，导入反应炉200内。载气的流量通常是10SLM～200SLM。构成掺杂的硅烷与5族原料一样的方法导入反应炉200内即可。
来自由MFC102控制流量的高压储气瓶109的载气被导入由恒温层106控制到所需温度的原料容器108内，在位于原料容器108内的有机金属原料中被起泡。通过起泡，原料容器108的上部空间被由恒温层106的温度确定的蒸气压的有机金属原料充满，对应于蒸气压与载气流量的量的有机金属原料气体被导入反应炉200内。
基底基板1由设置在反应炉200内的石墨制基板支架201保持。基板支架201具有旋转机构，另外，在其背面配置有电阻加热机201，通过基板支架110从背面加热基底基板1。在GaN类半导体结晶的情况下，进行加热，使基底基板1的表面温度为约900℃～约1300℃即可。
导入反应炉200内的原料气体在基底基板1表面附近被热分解，在基底基板1上作为结晶生长。残渣气体及未分解气体从排气口203排出。这样，通过向反应炉200内导入原料气体，掺杂硅的GaN类结晶或未掺杂硅的GaN类结晶在基底基板1上生长。
作为结晶生长中使用的3族原料，可举出例如三甲基镓(TMG)或三乙基镓(TEG)等烷基镓、三甲基铝(TMA)或三乙基铝(TEA)等烷基铝、如三甲基铟(TMI)的烷基铟。3族原料单独或混合使用以构成所需的组成即可。3族原料在MOCVD用途中被出售。
作为构成掺杂的硅原料，可举出例如乙硅烷、甲硅烷。乙硅烷或甲硅烷使用出售的结晶生长所需的高纯度的材料即可。
作为载气，可举出例如氢气、氮气。它们可单独或混合使用。载气使用出售的结晶生长所需的高纯度的材料即可。
作为基底基板1，可举出例如GaAs、GaN、蓝宝石、SiC、Si等单晶基板。基底基板1具有绝缘性、导电性任一均可，但优选具有绝缘性。基底基板1使用出售的结晶生长所需的不可欠缺的材料即可。
以下，参照图2说明图1所示的GaN类-MISHFET用外延结晶基板的制造方法。
将洗净的半绝缘性SiC的基底基板1设置在基板支架202上，在基底基板1上，使规定厚度的AlN缓冲层2生长。
AlN缓冲层2的厚度通常为
Figure G2007800340622D00061
从生产率与效果的平衡的观点出发，优选更加优选也可代替AlN缓冲层2，使用相同厚度的AlGaN缓冲层。此时，变更原料气体以构成所需的组成，此外，以与AlN缓冲层2的情况一样的方法生长即可。在提高缓冲层2的绝缘性的观点考虑，缓冲层2也可掺杂Fe、Mn、C等。
将基底基板1的温度变更为规定温度，切换3族原料气体，使规定厚度的SI形GaN沟道层3生长。沟道层3的厚度只要在向与电子供给层4的界面附近的、形成2DEG沟道的部位提供良好结晶性的范围内决定即可。结晶性的判定利用XRD的摇摆曲线的测定执行即可。作为构成测定对象的结晶面，例如使用(0001)面即可。在测定(0001)面的情况下，当峰值的半值幅度为300秒以下时，得到良好的特性。
沟道层3的厚度通常为
Figure G2007800340622D00064
以上，明显依赖于生长条件。从生产率提高的观点出发，厚度优选
Figure G2007800340622D00065
以上
Figure G2007800340622D00066
以下，更加优选
Figure G2007800340622D00067
尤其优选
Figure G2007800340622D00072
接着，通过供给或不供给掺杂硅气体，使掺杂Si或不掺杂Si的电子供给层4生长为规定厚度。电子供给层4的厚度和Al组成只要确定成在结晶不会因与沟道层3的晶格错配而恶化的范围内形成所需的沟道载流浓度、相互电导、夹断电压即可。若增大Al组成，则与沟道层3的晶格错配变大，厚度变薄。厚度的范围通常为
Figure G2007800340622D00073
优选
Figure G2007800340622D00074
进而优选
Figure G2007800340622D00075
Al组成通常为0.1～0.4，优选0.15～0.35，尤其优选0.18～0.30。
这样，在结束GaN类结晶的最上层即电子供给层4的生长之后，不将由此得到的基板曝露于大气中，而将基板置于反应炉200内，使电介质层5在电子供给层4上生长。电子供给层4与电介质层5只要在同一反应炉内连续生长即可。在电子供给层4生长后，将基板温度变更为规定温度，将作为3族原料气体的TMA导入反应炉200内，同时，还导入氧原料，作为电介质层5，生长规定厚度的Al2O3电介质即可。这样，得到图1所示构造的外延结晶基板。电介质层5的生长工序中，使用MOCVD即可。
为了使Al2O3电介质以外的氧化物电介质生长为电介质层5，在原料容器108内置入氧化物电介质生长所需的有机金属，与Al2O3电介质一样，使GaN类结晶生长，不使结晶表面曝露于大气中地使氧化物电介质生长。例如，在使GaN类结晶生长之后，将基底基板1的温度变更为所需温度，将电介质层5的生长所需的有机金属气体导入反应炉200内，使电介质层5生长。
有机金属气体的导入与3族原料的导入一样，只要通过由置入有机金属的原料容器108使由MFC102控制流量的载气起泡来执行即可。此时，也可由减压阀113减压填充在高压储气瓶110中的氧气，由MFC103控制流量后，与有机金属气体同时导入反应炉200中。
示出了电介质层5为氧化物电介质的情况，但电介质层5也可以是同一金属的氧化物与氮化物的复合电介质。由这种复合电介质构成的电介质层5的生长只要合用氮原料(氨)来执行即可。氮原料使用出售的适于结晶生长的纯度的材料即可。氮原料的导入只要适用在GaN类结晶生长中使用的方法即可。
在电介质是Al2O3的情况下，作为用于电介质生长的有机金属原料，可举出例如TMA、TEA。在HfO2的情况下，可举出例如四特丁氧基铪。在SiO2的情况下，可举出三二甲基氨基硅烷、三二乙基氨基硅烷。在MgO的情况下，可举出例如双环戊二烯基镁、二乙基环戊二烯基镁。这些使用出售的适于结晶生长的纯度的材料即可。
作为氧气原料，例如氧气、水、或二甲基醚、二乙基醚、正丁基醚等的醚类。这些使用出售的适于结晶生长的纯度的材料即可。
生长温度依赖于有机金属原料的分解温度。在电介质是Al2O3的情况下，生长温度通常为约500℃～约1100℃，优选为约600℃～约900℃，尤其优选为约700℃～约800℃的范围。在HfO2的情况下，生长温度通常为约200℃～约800℃，优选为约250℃～约700℃，更加优选为约300℃～约600℃。在Si3N4的情况下，生长温度通常为约400℃～约900℃，优选为约450℃～约800℃，更加优选为约500℃～约700℃。在MgO的情况下，生长温度通常为约200℃～约800℃，优选为约250℃～约700℃，更加优选约300℃～约600℃。
另外，电介质层5也可以是Al2O3:N(包含N的Al2O3)、SiO2:N(包含N的SiO2)、Ga2O3、HfxAlyO3(0＜x＜1、y＝2-1/2x)、HfxAlyO3:N(包含N的HfxAlyO3)(0＜x＜1、y＝2-1/2x)、HfO2、GdO、ZrO2、Ta2O5。
电介质层的厚度只要勘查电介质的介电常数与晶体管的目标阈值电压、增益特性来确定即可，为了得到良好的阈值电压、增益特性，在构成相互电导、夹断电压的范围内抑制栅极泄漏电流为好，厚度通常为约1nm～约30nm。
以上主要说明附带Al2O3电介质的GaN-异质结场效应晶体管(HFET)用外延结晶基板的制造方法，但本发明的制造方法可以包括使半导体外延结晶层与电介质层在MOCVD生长炉内连续生长的工序，适用于可以用MOCVD法生长的半导体结晶类。作为这种结晶类，可举出例如硅锗类(SiGe类)、氮化镓类(GaN类)、磷化铟类(InP类)、碳化硅类(SiC类)。
另外，通过改变半导体结晶层的构造，可以制造作为FET构造的MODFET、MESFET用外延结晶基板、各种二极管用外延结晶基板。并且，也能够适用于发光二极管(LED)等发光元件。
实施例
示出实施例，进一步详细说明本发明，但本发明不限于此。
实施例1
使用图2所示的装置，制造图1所示的层构造的半导体外延基板。使用半绝缘性SiC基板作为基底基板1。将半绝缘性SiC基板加热到1000℃，作为载气以60SLM流过氢、以40SLM流过氨，从设定为恒温槽温度30℃的原料容器以40sccm流过TMA，在半绝缘性SiC基板上生长
Figure G2007800340622D00091
的AlN缓冲层2。在将基板温度变更为1150℃，将TMA流量设为0sccm之后，从设定为恒温槽温度30℃的原料容器以40sccm流过TMG，在AlN缓冲层2上生长
Figure G2007800340622D00092
的GaN沟道层3。从设定为恒温槽温度30℃的原料容器以40sccm流过TMA，在GaN沟道层3上生长
Figure G2007800340622D00093
的AlGaN电子供给层4。
在不从装置中取出基板的情况下，将基板温度变更为900℃，停止TMG与氨的供给，供给400sccm的二乙醚，生长
Figure G2007800340622D00094
的Al2O3，从而得到电介质层5。然后，使基板冷却从反应炉中将其取出，得到具有图1所示的层构造的带电介质膜的外延基板。
使用得到的带电介质膜的外延基板，如下制造图3所示结构的GaN-MISHFET。在带电介质膜的外延基板中通过光刻形成抗蚀图案之后，通过打入N+离子，形成元件分离9至
Figure G2007800340622D00095
的深度。通过光刻，将抗蚀剂开口形成为源极电极和漏极电极形状，通过使用Ar、CH2Cl2、Cl2的混合气体的ICP等离子体蚀刻除去开口部分的电介质层5，露出AlGaN电子供给层4。
在基板的整个面上，蒸镀Ti(厚度
Figure G2007800340622D00096
)/Al(厚度
Figure G2007800340622D00097
)/Ni(厚度
Figure G2007800340622D00098
)/Au(厚度
Figure G2007800340622D00099
)的金属膜之后，以lift-off法将金属膜加工成电极形状。在氮气氛下以800℃RTA处理基板30秒，形成源极电极8与漏极电极6。通过光刻(Photolithography)形成栅极电极形状的开口，在开口的整个面上蒸镀Ni(厚度
Figure G2007800340622D000910
)/Au(厚度)的金属膜，通过lift-off将金属膜加工成电极形状，形成栅极电极7。
在氮气氛下以500℃退火基板30分钟。如此制作具有Al2O3或AlN电介质层5的栅极长度为2μm、栅极宽度为30μm的GaN-MISHFET，作为兼有栅极绝缘膜与钝化膜的层。
比较例
在使AlGaN电子供给层4生长之后，不使电介质生长，冷却基板，将基板从反应炉中取出，除此之外，执行与实施例1相同的操作，来制作栅极绝缘膜与钝化膜均不具有的栅极长度为2μm、栅极幅度为30的GaN-MISHFET。
对由实施例1及比较例得到的GaN-MISHFET，图4示出了栅极电压-栅极电流特性的测定结果。如图4所示，实施例1得到的GaN-MISHFET在负的栅极电压施加时的栅极电流比比较例约小2位数，示出了优良的栅极泄漏特性。
对实施例1和比较例得到的GaN-HFET，图5示出了漏极滞后特性(漏极电压-漏极电流-时间特性)的评价结果。评价以源极电极与栅极电极接地、测定使漏极电压从+20V急剧变化到+1V时的、从+1V施加开始时间起的电流的过渡电流变化的方法来执行。如图5所示，实施例1的GaN-HFET在使漏极电压从+20V变化到+1V之后，示出稳定电流值。另一方面，比较例的GaN-HFET在使漏极电压从+20V变化到+1V时，漏极电流值没有马上变为恒定值，缓慢增加，至变为恒定值需要一些时间。即，示出器件动作中成为问题的漏极滞后。从该结果可知，实施例1的带电介质膜的GaN-MISHFET示出优良的漏极滞后特性。
实施例2
使用图2所示的装置，如下制作图1所示的层构造的半导体外延基板。将半绝缘性SiC基板置于反应炉200内，将半绝缘性SiC基板加热到1000℃，在反应炉200内，作为载气以60SLM流过氢、以40SLM流过氨，从设定为恒温槽温度30℃的容器中以40sccm流过TMA，在半绝缘性SiC基板上生长
Figure G2007800340622D00101
的AlN缓冲层。将基板温度变更为1150℃，将TMA流量设为0sccm后，从设定为恒温槽温度30℃的容器以40sccm流过TMG，在AlN缓冲层上生长
Figure G2007800340622D00102
的GaN沟道层。从设定为恒温槽温度30℃的容器以40sccm流过TMA，在GaN沟道层上生长
Figure G2007800340622D00103
的AlGaN电子供给层。将基板温度变更为700℃，停止TMG的供给，将载气从氢切换为氮，供给40sccm的正丁基醚，在AlGaN电子供给层上生长
Figure G2007800340622D00104
的AlxOy电介质层。利用X射线光电子分光法求出电介质层的元素比。为x∶y＝6∶4。冷却基板，从反应炉200中将其取出，从而得到带电介质膜的半导体外延基板。
在半导体外延基板中，利用光刻将抗蚀剂开口形成为源极电极形状及漏极电极形状，利用使用了Ar、CH2Cl2、Cl2的混合气体的ICP等离子体蚀刻除去开口部分的电介质膜，露出AlGaN层。在基板的整个面上，蒸镀Ti(厚度
Figure G2007800340622D00111
)/Al(厚度
Figure G2007800340622D00112
)/Ni(厚度
Figure G2007800340622D00113
)/Au()的金属膜，并以lift-off法将金属膜加工成电极形状。
在氮气氛下以800℃RTA处理得到的半导体外延基板30秒，形成源极电极206与漏极电极204。在半导体外延基板中，通过光刻形成抗蚀图案之后，打入N+离子，形成元件分离层至
Figure G2007800340622D00115
的深度。通过光刻，形成栅极电极形状的开口，在基板的整个面上，淀积Ni(厚度
Figure G2007800340622D00116
)/Au(厚度
Figure G2007800340622D00117
)的金属膜，以lift-off法将金属膜加工成电极形状，形成栅极电极，得到作为兼有栅极绝缘膜与钝化膜的层的、具有电介质层(AlO)的栅极长度为2μm、栅极宽度为30μm的GaN-MISHFET。
得到的GaN-MISHFET在施加栅极偏压-10V时的泄漏电流为2×10-5mA/mm，与实施例1的GaN-MISHFET相比，泄漏电流特性提高。另外，实施例2的GaN-MISHFET的电流崩塌低至与实施例1相同的程度。
产业上的可利用性
根据本发明，得到具有低的栅极泄漏电流与小到可忽视的栅极滞后、漏极滞后、电流崩塌特性的、带电介质膜的半导体外延基板。半导体外延基板适用于氮化镓类半导体、场效应晶体管。

Claims (7)

1.一种半导体外延结晶基板的制造方法，向通过有机金属气相生长法生长的氮化物半导体结晶层表面，赋与构成钝化膜或栅极绝缘膜并具有非结晶形的氮化物电介质或氧化物电介质的电介质层，其中，
在外延生长炉内使所述氮化物半导体结晶层生长之后，直接在该外延生长炉内使所述电介质层与所述氮化物半导体结晶层连续生长。
2.根据权利要求1所述的半导体外延结晶基板的制造方法，其中，
使用有机金属作为金属原料，使用乙醚或水作为氧原料，使用氨作为氮原料，并利用有机金属气相生长法使电介质层生长。
3.根据权利要求2所述的半导体外延结晶基板的制造方法，其中，
电介质层的至少一部分的生长为边供给作为5族原料的氨边进行。
4.根据权利要求1、2或3所述的半导体外延结晶基板的制造方法，其中，
电介质层的至少一部分的生长通过使用氮作为载气来进行。
5.根据权利要求1或2所述的半导体外延结晶基板的制造方法，其中，
电介质层包括从AlOx、AlOx∶N(0.5＜x＜1.5)、SiO2、SiO2∶N、Ga2O3、Si3N4、HfO2、HfxAlyO3(0＜x＜1、y＝2-1/2x)、HfxAlyO3∶N(0＜x＜1、y＝2-1/2x)、GdO、ZrO2、MgO、Ta2O5中选择的至少一种电介质。
6.根据权利要求1或2所述的半导体外延结晶基板的制造方法，其中，
电介质层包括从Al2O3、Al2O3∶N、SiO2、SiO2∶N、Ga2O3、Si3N4、HfO2、HfxAlyO3(0＜x＜1、y＝2-1/2x)、HfxAlyO3∶N(0＜x＜1、y＝2-1/2x)、GdO、ZrO2、MgO、Ta2O5中选择的至少一种电介质。
7.根据权利要求1～3中任一项所述的半导体外延结晶基板的制造方法，其中，
半导体外延结晶基板用于场效应晶体管。
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