CN101449362B - 提高半导体器件中电感器的品质因子的方法 - Google Patents
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Abstract
一种在硅衬底(10)中制造电感器(70)的方法，其中，在沉积了抗蚀剂层(82)并且蚀刻了多晶硅层(30)之后，但在剥离抗蚀剂层(82)并且将多晶硅退火之前，执行氩注入步骤(84)。因而，在衬底(10)上产生非晶层(86)，使得在不需要附加的遮挡步骤或不对多晶硅层(30)造成不利影响的情况下改善了电感器(70)的Q因子。
Description
技术领域
本发明一般涉及通过减小衬底损耗而改善半导体器件中的电感器的品质因子的方法。
背景技术
尚未容易地使用单个半导体加工技术将射频(RF)电路集成到硅片中，如同片上系统(system-on-chip)工业对于数字电路所实现的那样。对RF应用的需求将需要使用多个半导体技术来实现必要的性能的系统级封装(system-in-package)解决方案。正在开发新的加工技术和集成技术，这将允许以可接受的成本来生产这些系统级封装RF解决方案，即使针对大量的用户产品应用。
当前的硅加工技术允许制造具有超过40GHz的增益特性的集成晶体管，满足了用户电子领域中现有无线应用的所有需要。然而，RF性能依靠这些晶体管周围的无源器件的程度与依靠晶体管本身一样。由于它们的结构，已经传统地将诸如电容器和电感器之类的无源器件实现为分立元件，并且这些无源器件赶不上由半导体技术提供的小型化的水平，当前正在开发将无源元件集成在硅上的方法，其方式不仅增强了RF性能，还满足低成本、大量生产的要求。
将无源元件集成在硅上并不一定是指如有源晶体管一样集成在同一片硅(或“管芯”)上。而是指，无源元件技术需要利用(leverage)硅片生产中固有的集成能力。然后能够将无源和有源管芯结合到封装中。
应用几种技术来集成无源元件。例如，在沉积到硅上的金属化层(metallization layer)内制造电感器和电容器。
更具体地，可以通过在半导体晶片上形成平面的金属螺线(spiral)来实现电感。近年来，随着越来越高地集成半导体器件，出于该目的广泛地使用高导电性的铜以使电感器的品质因子最大。然而，这种电感器的Q-因子趋于相对差，主要是由于低电阻率的Si晶片的高衬底RF损耗以及螺线金属的欧姆损耗。因为通过使用粗铜线能够进一步减小欧姆损耗，所以衬底损耗变成了对电感器Q-因子的主要决定因素，即使在使用高电阻率硅来抑制诸如涡电流之类的衬底感生损耗时，Q因子仍然不适于许多高频应用。这是归因于在硅衬底与电介质(SiO2)层之间的界面处积累的电荷，其中通过热氧化将所述电介质(SiO2)生长在硅衬底上以将金属化层与高电阻硅衬底隔离。
提出了几种方法来解决该问题，由此减小了由上述积累的电荷造成的影响，并且通过在电感器下面的衬底上产生非晶层增大了衬底的有效电阻。
已知通过执行注入工艺在衬底的顶部产生这样的非晶层，注入工艺将重离子(典型地在硅衬底情况下为氩，尽管认为N也是合适的)注入衬底中，以及在器件包括多晶硅层的典型情况下，已经将氩注入步骤整合到器件工艺流程中的数种方法。在第一个已知方法中，完成多晶硅加工阶段(也就是蚀刻多晶硅)，剥离抗蚀剂层，并且对剩余的多晶硅区域退火，然后是氩注入。然而，如果在氩注入期间多晶硅保持为未遮挡(unmasked)，则多晶硅的表面可能受损，然而附加的遮挡步骤的加入提高了成本。在替代方法中，在将电介质层(SiO2)生长在高电阻硅衬底上之后、在多晶硅加工阶段之前，将氩注入、未遮挡。然而，多晶硅沉积以及后续加工的热预算(budget)将使得通过注入步骤产生的非晶层部分地结晶。
K.T.Chan等在Large Q-Factor Improvement for Spiral Inductors onSilicon Using Proton Implantation，IEEE Microwave and WirelessComponents Letters，Vol.13，No.11，November 2003中提出，在整个晶片制造之后执行质子注入以便将杂质引入电感器下面的硅层中，从而增大其电阻并且改善其Q-因子。尽管在完成整个晶片制造工艺之后执行质子注入避免了对VLSI工艺线的污染，然而这使得在制造工艺最后的附加加工步骤变得有必要，所述附加加工步骤具有显著的成本引入(cost implication))。
发明内容
因此，提出一种制造半导体器件的方法，该半导体器件包括电感器，从而，在器件的制造工艺的前端在半导体衬底上形成非晶层，而不需要附加的遮挡步骤。
根据本发明，提供了一种制造集成电路的方法，该集成电路载有至少一个无源元件，该方法包括：提供可以在其上形成无源元件的半导体衬底；在所述衬底上沉积导电材料层；在所述层上提供构图的抗蚀剂层并且蚀刻所述层；执行离子注入步骤，以在所述衬底上未被所述蚀刻的多晶硅层覆盖的区域中产生非晶层；以及在所述离子注入步骤之后去除所述抗蚀剂层。
从而，通过在沉积并且蚀刻了多晶硅层之后，但在剥离抗蚀剂层以及对多晶硅退火之前执行离子注入步骤，能够在没有附加遮挡步骤并且不对多晶硅层造成不利影响的情况下，在衬底上产生非晶层。
优选地，使用重离子(如氮，或更优选的氩)执行离子注入步骤。无源元件可以包括多匝电感器，所述多匝电感器包括形成在衬底上的金属螺线。优选地，集成电路载有至少一个附加无源元件，如平面电容器、凹陷式电容器(pit capacitor)或电阻器。优选地，利用电介质层将所述至少一个无源元件与半导体衬底隔离，其中优选地在衬底是硅衬底的情况下电介质层是二氧化硅。
本发明还涉及通过以上方法制造的、载有至少一个无源元件的集成电路。
附图说明
从本文所述的实施例可以明了本发明的这些和其他方式，并将参照本文所述的实施例进行阐明。
现在将仅以示例的方式并且参考附图来描述本发明的实施例，附图中：
图1是通过PASSI工艺制造的管芯的示意性横截面图；
图2是示出了凹陷式电容器的主要部件的示意图；
图3是载有RF无源元件的集成电路的示意性横截面图；以及
图4a至4e是示出了根据本发明示例实施例的制造工艺的主要步骤的示意图。
具体实施方式
近年来，针对工业规模的使用，开发硅工艺用于制造高-Q无源如电感器和电容器，用于0.9至2GHz之间的前端(front-end)应用。该工艺使用高阻硅(HRS)作为载体衬底，本文将利用其来描述本发明的示例实施例。然而，本领域技术人员将理解，本发明还可以用于其它无源集成技术。
参考附图的图1，将具有p>4kΩ的比电阻(specific resistivity)的高欧姆硅晶片用作载体10，以制造电容器-电感器网络。使用高欧姆Si以便对与衬底耦合的RF功率的耗散加以限制。利用热生长的氧化物层12隔离Si衬底10。由PECVD SiNx电介质18分开的、相对薄的两个溅射A1层14、16用于限定电容器。继续该工艺，沉积PECVD SiOx去耦合层20，所述PECVD SiOx去耦合层20将电容器与接下来沉积的A1顶部金属化物22去耦合。5μm厚的A1顶部金属化物22用于限定高-Q电感器。该工艺结束于沉积PECVD SiNx防刮层(scratch protection)24。目前该工艺用于生产裸(naked)管芯，所述裸管芯包括能够装配到混合电路RF模块中的、诸如阻抗匹配网络或谐振(resonant)滤波器之类的电路。
目前正在开发另一工艺，其中单个低成本硅管芯不仅载有所有需要的无源元件，还载有这些无源元件之间互连图案。作为开发过程的一部分，研究提高电容密度的途径。上述工艺中制造的金属-绝缘体-金属(MIM)电容器实现了达到150pF/mm2的电容密度，然而这仍然限制了能够在硅的实际区域中实现的电容值。
研究的提高电容密度的一个途径是，在不过度增大占用的硅的面积的情况下增大电容器电极的表面面积。参考附图的图2，通过以下方式制造开发的器件(称作“凹陷式电容器”)：将深孔洞的矩阵蚀刻到n-硅衬底10的表面中，然后通过n+扩散产生下电极26，电介质、多晶硅30以及金属沉积产生电介质层28和上电极32。使用该途径证实达到100nF/mm2的电容密度。
参考附图的图3，从而，上述工艺能够用于制造载有诸如平面电容器40、凹陷式电容器50、电阻器60、多匝电感器(由位置70表示)和凸块焊盘80、以及它们之间的互连图案之类的无源元件的单个硅管芯10。
如以上解释的，为了改善(最终)电感器70的品质因子，提出执行重离子(优选地而不一定是氩)的注入，以在衬底的顶部产生非晶层。除了氩以外合适的离子包括：氮、硅(Si)、氧(O)、碳(C)、氖(Ne)。本领域技术人员将理解，还可以注入其它重离子。
参考附图的图4a至4e，在根据本发明示例实施例的过程中，一旦在硅衬底10中制造了平面电容器40、凹陷式电容器50以及电阻器60，则在多晶硅层30上施加光抗蚀剂涂层82(图4a)，并且显影(图4b)，以产生用于多晶硅蚀刻过程的掩模(图4c)。注意，参考数字70表示多匝电感器的位置，然而多匝电感器本身是在该工艺中(采用后端金属)随后制造的。在蚀刻多晶硅层30之后，执行氩注入工艺84以在衬底10的顶部上产生非晶层86(图4d)。由离子注入机(implanter)来执行氩注入。把该机器将要注入的物质电离，并对晶片进行扫描，具有三个主要参数：剂量(dose)(1016ions/cm2左右)、能量(约50KeV)以及入射束的倾斜(7度)。冲撞(impact)在晶片的表面引起结晶(crystalline)破坏。这样，能够产生非晶层。在注入工艺之后，将抗蚀剂层从剩余的多晶硅30剥离，并且对剩余的多晶硅30退火(图4e)。
因而，在没有额外的遮挡步骤并且多晶硅层不变差的情况下，实现了氩注入，并且在电感器70下面产生非晶层。在多晶硅蚀刻步骤之后立即执行氩注入，使得多晶硅仍然受光抗蚀剂层保护。然后一旦剥离抗蚀剂层，就执行多晶硅退火步骤。
应该注意，上述示例示出而不是限制本发明，在不脱离由所附权利要求所限定的本发明的范围的情况下，本领域技术人员将能够设计出许多替代实施例。在权利要求中，括号中的任何参考标记不应理解为限制权利要求。词语“包括”等不排除任何权利要求或说明书整体所列元件或步骤之外的之外其它元件或步骤的存在。元件的单数参考不排除复数的元件，反之亦然。可以通过包括几个不同(distinct)元件在内的硬件，或通过合适编程的计算机来实现本发明。在列举了几个手段的器件权利要求中，可以利用一个或相同项目的硬件来实施这些手段中的几个。重要的事实是在互不相同的从属权利要求中陈述的某些措施，不表示不能有利地利用这些措施的组合。
Claims (12)
1.一种制造集成电路的方法(70)，该集成电路载有至少一个无源元件，该方法包括：提供可以在其上形成无源元件的半导体衬底(10)；在所述衬底(10)上沉积导电材料层(30)；在所述导电材料层(30)上提供构图的抗蚀剂层(82)作为掩模并且蚀刻所述导电材料层(30)；其特征在于，该方法进一步包括：执行离子注入步骤(84)，以在所述衬底(10)上未被所述蚀刻的导电材料层(30)以及所述构图的抗蚀剂层(82)覆盖的区域中产生非晶层(86)；以及在所述离子注入步骤之后去除所述构图的抗蚀剂层(82)。
2.根据权利要求1的方法，其中，使用重离子执行离子注入步骤。
3.根据权利要求2的方法，其中，所述重离子包括氩。
4.根据权利要求1的方法，其中，所述无源元件包括多匝电感器(70)，所述多匝电感器包括形成在衬底(10)上的金属螺线。
5.根据权利要求1的方法，其中，所述集成电路载有至少一个附加无源元件。
6.根据权利要求5的方法，其中，所述至少一个附加无源元件包括平面电容器(40)、凹陷式电容器(50)或电阻器(60)。
7.根据权利要求1的方法，其中，利用电介质层将所述至少一个无源元件与半导体衬底隔离。
8.根据权利要求7的方法，其中，所述电介质层包括二氧化硅，以及所述衬底包括硅衬底。
9.根据权利要求1的方法，其中，所述导电材料是半导体材料。
10.根据权利要求1或9的方法，其中，所述导电材料是硅。
11.根据权利要求9的方法，其中，所述半导体材料具有多晶形态。
12.一种通过根据权利要求1的方法制造的、载有至少一个无源元件的集成电路。
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| PCT/IB2007/051835 WO2007135620A1 (en) | 2006-05-18 | 2007-05-15 | Method of increasing the quality factor of an inductor in a semiconductor device |
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| KR101101686B1 (ko) * | 2010-01-07 | 2011-12-30 | 삼성전기주식회사 | 고주파 반도체 소자 및 그 제조방법 |
| US8735986B2 (en) | 2011-12-06 | 2014-05-27 | International Business Machines Corporation | Forming structures on resistive substrates |
| US9469107B2 (en) | 2013-07-12 | 2016-10-18 | Hewlett-Packard Development Company, L.P. | Thermal inkjet printhead stack with amorphous metal resistor |
| CN103426729A (zh) * | 2013-08-29 | 2013-12-04 | 上海宏力半导体制造有限公司 | 提高整合被动器件电感器q值的方法 |
| CN104517803A (zh) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | 一种集成无源器件中去耦合电容结构及其制备方法 |
| CN103956362A (zh) * | 2014-05-20 | 2014-07-30 | 中国工程物理研究院电子工程研究所 | 基于图形化高能离子注入的低衬底损耗硅基集成电路及其制作方法 |
| CN103972053A (zh) * | 2014-05-29 | 2014-08-06 | 中国工程物理研究院电子工程研究所 | 一种图形化高能重离子注入的低损耗硅基射频无源器件的制作方法 |
| US11501908B2 (en) | 2016-10-04 | 2022-11-15 | Nanohenry, Inc. | Miniature inductors and related circuit components and methods of making same |
| EP3327806B1 (en) * | 2016-11-24 | 2021-07-21 | Murata Integrated Passive Solutions | Integrated electronic component suitable for broadband biasing |
| US11289474B2 (en) | 2020-04-20 | 2022-03-29 | Globalfoundries U.S. Inc. | Passive devices over polycrystalline semiconductor fins |
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| Publication number | Publication date |
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| EP2024990B1 (en) | 2011-06-29 |
| CN101449362A (zh) | 2009-06-03 |
| US20090267182A1 (en) | 2009-10-29 |
| EP2024990A1 (en) | 2009-02-18 |
| JP2009537980A (ja) | 2009-10-29 |
| WO2007135620A1 (en) | 2007-11-29 |
| ATE515059T1 (de) | 2011-07-15 |
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