CN101399194A - 在半导体器件中制造凹陷栅极的方法 - Google Patents
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Abstract
一种在半导体器件中制造凹陷栅极的方法,所述方法包括:蚀刻硅衬底以形成限定有源区的沟槽;形成填隙沟槽的器件隔离层;在硅衬底上形成硬掩模层,所述硬掩模层包括氧化物层和非晶碳层的堆叠结构,其中硬掩模层暴露有源区的沟道目标区;和通过使用所述硬掩模层作为蚀刻阻挡层来对沟道目标区进行第一蚀刻和第二蚀刻以形成具有双重轮廓的凹陷区域,其中移除非晶碳层之后实施所述第二蚀刻。
Description
相关申请
本发明要求2007年9月28日提交的韩国专利申请2007-0098221的优先权,其全部内容通过引用并入本文。
技术领域
本发明涉及半导体器件制造,并且更具体地涉及在半导体器件中制造凹陷栅极的方法。
背景技术
在半导体器件的制造中,平面栅极形成方法用于在平面有源区上形成栅极。然而,由于图案尺寸减小导致沟道长度减小,并且由于衬底的离子注入掺杂浓度增加导致电场增加,因此导致结漏电流。这使得难以获得器件的刷新(refresh)特性。
为解决上述限制,已经提出三维凹陷栅极工艺作为替代的栅极形成方法,该方法在蚀刻有源区之后形成栅极。凹陷栅极工艺使得能够增加沟道长度并且降低离子注入掺杂浓度,因此改善器件的刷新特性。
图1A~1C说明根据传统技术制造半导体器件中凹陷栅极的方法。在此,每个附图的右部是沿线l-l′截取的截面图。
参考图1A,蚀刻硅衬底11的器件隔离区以形成沟槽12,并且在沟槽12中形成器件隔离层13。该工艺被称作浅槽隔离(STI)工艺。
在所得结构上形成非晶碳层14,并且对所述非晶碳层14实施用于形成凹陷区域的掩模工艺,由此形成光刻胶图案15。
使用光刻胶图案15作为蚀刻阻挡层来蚀刻非晶碳层14。
参考图1B,使用非晶碳层14作为蚀刻阻挡层,蚀刻硅衬底11以形成用作晶体管沟道的凹陷区域16。凹陷区域16也称为凹陷沟道。
参考图1C,在包括凹陷区域16的硅衬底11上形成栅极绝缘层17。在栅极绝缘层17上沉积导电层直至填充凹陷区域16,蚀刻沉积的导电层以形成栅极18。
然而,在半导体器件的超细图案化工艺期间,由于能够形成三维凹陷栅极的凹陷区域的尺寸减小,所以在等离子体蚀刻工艺中凹陷区域16的底部轮廓形成V-形轮廓。这导致其中称为角状物(horn)H的硅(Si)残留于邻近器件隔离层13上部区域的角状物效应。硅残留物由通过非晶碳层的碳的再沉积所获得的聚合物而产生。
图2说明显示根据传统技术的角状物的扫描电子显微镜(SEM)照片。由图2可看出:角状物存在于邻近器件隔离层的上部区域。
角状物H导致栅极绝缘层17的劣化。角状物H是应力集中点并且作为漏电流源,由此降低器件制造良品率并且使得难以制造DRAM。
角状物H由凹陷区域16的V形轮廓所引起,当以约90°或更小的角度(见图3)形成填隙(gap-filled)有器件隔离层13的沟槽12的侧壁时形成所述V形轮廓。
图3说明显示根据传统技术的填隙有器件隔离层的沟槽的侧壁角度的SEM照片。由图3可看出所述沟槽形成为具有约90°或更小的角度。
发明内容
本发明的实施方案涉及提供在半导体器件中制造凹陷栅极的方法,该方法可抑制在凹陷栅极形成工艺期间在凹陷区域的蚀刻过程中产生角状物。
本发明的实施方案还涉及提供在半导体器件中形成凹陷沟道的方法,该方法可进一步增加沟道长度同时减小凹陷沟道的线宽。
根据本发明的一个方面,提供一种在半导体器件中制造凹陷栅极的方法。所述方法包括:蚀刻硅衬底以形成限定有源区的沟槽;形成填隙沟槽的器件隔离层;在硅衬底上形成硬掩模层,所述硬掩模层包括氧化物层和非晶碳层的堆叠结构,其中硬掩模层暴露有源区的沟道目标区;和通过使用所述硬掩模层作为蚀刻阻挡层来对沟道目标区进行第一蚀刻和第二蚀刻以形成具有双重轮廓(dual profile)的凹陷区域,其中在除去非晶碳层之后实施所述第二蚀刻。
根据本发明的另一个方面,提供一种在半导体器件中形成凹陷沟道的方法。所述方法包括:在半导体衬底上形成硬掩模层,所述硬掩模层包括钝化层和非晶碳层的堆叠结构,其中硬掩模层暴露半导体衬底的沟道目标区;使用非晶碳层作为蚀刻阻挡层来蚀刻沟道目标区以形成第一凹陷区域;除去非晶碳层;和使用钝化层作为蚀刻阻挡层来蚀刻第一凹陷区域的底部以形成第二凹陷区域。
根据本发明的另一个方面,提供一种在半导体器件中制造凹陷栅极的方法。所述方法包括:蚀刻硅衬底以形成限定有源区的沟槽;在沟槽中形成器件隔离层;在硅衬底上形成硬掩模层,所述硬掩模层包括氧化物层和非晶碳层,其中硬掩模层暴露有源区的沟道目标区;使用非晶碳层作为蚀刻阻挡层来对沟道目标区进行第一蚀刻以形成第一凹陷区域;除去非晶碳层;使用氧化物层作为蚀刻阻挡层来对第一凹陷区域的底部进行第二蚀刻以形成第二凹陷区域,其中第二凹陷区域宽于第一凹陷区域。
根据本发明的另一个方面,提供在半导体器件中形成凹陷沟道的方法。所述方法包括:在半导体衬底上形成硬掩模层,所述硬掩模层包含钝化层和非晶碳层,其中硬掩模层暴露半导体衬底的沟道目标区;使用非晶碳层作为蚀刻阻挡层来蚀刻沟道目标区以形成第一凹陷区域;除去非晶碳层;和使用钝化层作为蚀刻阻挡层来蚀刻第一凹陷区域的底部以形成第二凹陷区域,其中第二凹陷区域宽于第一凹陷区域。
附图说明
图1A~1C说明根据传统技术在半导体器件中制造凹陷栅极的方法。
图2说明显示根据传统技术的角状物的SEM照片。
图3说明显示根据传统技术的填隙有器件隔离层的沟槽的侧壁角度的SEM照片。
图4A~4F说明根据本发明一个实施方案在半导体器件中制造凹陷栅极的方法。
图5说明显示根据本发明一个实施方案的角状物和凹陷区域的轮廓的SEM照片。
具体实施方式
以下,将参考附图详细描述根据本发明的在半导体器件中制造凹陷栅极的方法。
应理解,在本发明中当诸如层、膜、图案和区域的要素/元件被称为在另一个要素/元件“上/下”时,其可直接在另一个要素/元件之上/之下,或者以可存在一个或更多的中间要素/元件。
在本发明的实施方案中,在用于形成凹陷区域或凹陷沟道的凹陷蚀刻工艺中,具有钝化层(例如氧化物层)和非晶碳层的堆叠结构的硬掩模层用作蚀刻阻挡层。所述凹陷蚀刻工艺包括:使用非晶碳层作为蚀刻阻挡层的第一凹陷蚀刻工艺和使用钝化层作为蚀刻阻挡层的第二凹陷蚀刻工艺。第一凹陷蚀刻工艺和第二凹陷蚀刻工艺使用相同的蚀刻气体、相同的压力、相同的源功率和相同的偏压功率来实施,并且在实施第二凹陷蚀刻工艺之前预先移除非晶碳层。换言之,在没有存在非晶碳层的情况下实施第二凹陷蚀刻工艺。在该情况下,在第二凹陷蚀刻工艺中产生的聚合物的量小于在第一凹陷蚀刻工艺中产生的聚合物的量。因此,能够形成较宽的凹陷区域并防止在邻近器件隔离层的区域中产生角状物。
图4A~4F说明根据本发明一个实施方案在半导体器件中制造凹陷栅极的方法。在此,每个附图的右部是沿线ll-ll′截取的截面图。
参考图4A,浅槽隔离(STI)工艺用于形成填充硅衬底21中的沟槽22的器件隔离层23。有源区由沟槽22限定,并且沟槽22可以形成为具有约90°或更小的角度。
在硅衬底21上形成硬掩模层24。硬掩模层24可包括氧化物层或非晶碳层。优选地,硬掩模层24可包括氧化物层24A和非晶碳层24B的堆叠结构。氧化物层24A也用作保护硅衬底21的表面的钝化层。
在硬掩模层24上形成抗反射涂层(ARC)25,并且对所得结构实施用于形成凹陷区域的掩模工艺以形成光刻胶图案26。ARC层25可以是有机底部抗反射涂层(OBARC)。
参考图4B,使用光刻胶图案26作为蚀刻阻挡层来蚀刻ARC层25和硬掩模层24。使用如电容耦合等离子体(CCP)型或磁增强反应性离子蚀刻(MERIE)型的等离子源实施这些蚀刻工艺。使用具有N2气体和O2气体混合物的等离子体并且通过同时施加源功率和偏压功率来蚀刻ARC层25和非晶碳层24B。使用氧化物层24A作为蚀刻停止层来蚀刻非晶碳层24B。此后,使用具有O2气体以及CFx(例如,CF4)气体和CHFx(例如,CHF3)气体之一的混合物的等离子体来蚀刻氧化物层24A。
参考图4C,移除光刻胶图案26和保留的ARC层25′。使用保留的非晶碳层24B′作为蚀刻阻挡层,实施第一凹陷蚀刻工艺以蚀刻硅衬底21至预定深度。通过第一凹陷蚀刻工艺形成第一凹陷区域27。使用变压器耦合等离子体(TCP)或感应耦合等离子体(ICP)作为等离子源并且使用氯基气体和溴基气体的混合物来实施第一凹陷蚀刻工艺。例如,优选以以下条件实施第一凹陷蚀刻工艺:HBr对Cl2的流量比为约5:1,施加约5毫托至约20毫托的压力,约500W至约1500W的源功率,和约100V~约300V的偏压功率。
参考图4D,在用于实施第一凹陷蚀刻工艺的蚀刻设备中原位移除保留的非晶碳层24B′。为此,使用约200sccm至约1000sccm的O2等离子体并且施加源功率而不施加偏压功率。
参考图4E,使用保留的氧化物层24A′作为蚀刻阻挡层,实施第二凹陷蚀刻工艺以蚀刻第一凹陷区域27的底部,由此形成第二凹陷区域28。在此,在用于实施第一凹陷蚀刻工艺和用于移除保留的非晶碳层24B′的蚀刻设备中原位实施第二凹陷蚀刻工艺。例如,第二凹陷蚀刻工艺可以通过使用氯基气体和溴基气体的混合物在TCP或ICP型的等离子体源下实施。例如,优选第二凹陷蚀刻工艺在以下条件下实施:施加约10毫托至约30毫托压力,约500W至约1500W的源功率,和约100V至约300V的偏压功率。具体地,如果分别使用HBr和Cl2作为溴基气体和氯基气体,那么优选HBr对Cl2的流量比为约5:1。通过在上述蚀刻条件下蚀刻第一凹陷区域27的底部形成的第二凹陷区域28具有随着第二凹陷区域28的深度增加而逐渐加宽的轮廓。优选地,形成第二凹陷区域28深于第一凹陷区域27,例如约700至约1000的厚度。
根据上述工艺,第一凹陷区域27和第二凹陷区域28构成具有不同的顶部和底部轮廓的双重轮廓的凹陷区域100。
由于以下原因,第一凹陷区域27和第二凹陷区域28具有不同的轮廓。
由于使用保留的非晶碳层24B′作为蚀刻阻挡层来蚀刻第一凹陷区域27,由于保留的非晶碳层24B′的碳而产生大量聚合物。产生的聚合物再沉积使得蚀刻轮廓具有垂直的轮廓。
另一方面,在除去保留的非晶碳层24B′之后形成第二凹陷区域28,因此产生相对少量的由碳导致的聚合物。因此,由于没有由碳聚合物导致的蚀刻障碍,所以第二凹陷区域28宽于第一凹陷区域27。
即,蚀刻第二凹陷区域28多于第一凹陷区域27。因此,可以抑制在邻近器件隔离层23的区域中产生角状物,并且即使产生角状物,其高度可以显著减小。
具有双重轮廓的凹陷区域100具有加宽的轮廓,其中底部宽度比常规凹陷区域的底部宽度大约几十纳米。因此,和传统技术不同,能够形成具有最小化的角状物的凹陷区域。再次参考图4E,附图标记‘P1’表示常规的轮廓,附图标记‘P2’表示根据本发明的一个实施方案的轮廓。由图4E可看出:根据本发明的实施方案的轮廓比常规的轮廓具有显著更低的角状物。
在用于形成加宽的第二凹陷区域28的第二凹陷蚀刻条件中,压力、功率和气体比是非常重要的。优选地,在以下条件下实施第二凹陷蚀刻工艺:施加约10毫托至约30毫托压力,约500W至约1500W源功率,和约100V至约300V偏压功率。
在另一个实施方案中,形成第二凹陷区域28之后,可以另外实施第三凹陷蚀刻工艺以进一步加宽第二凹陷区域28的宽度。原位实施第三凹陷蚀刻工艺。例如,第三凹陷蚀刻工艺可以通过使用HBr/Cl2气体和少量的SF6/O2气体的混合物以及使用TCP或ICP作为等离子体来实施。优选地,在以下条件下实施第三凹陷蚀刻工艺:施加约20毫托至约100毫托压力,约500W至约1500W的源极功率,和约50W或更小的偏压功率。第三凹陷蚀刻工艺使用氯基气体和氟基气体的混合物以及少量氧气体和氟基气体的混合物来实施。氟基气体可以是氟化氮(NFX)气体或氟化碳(CFX)气体,也可以是氟化硫气体如SF6气体。氟化氮气体可以是NF3气体,氟化碳气体可以是CF4气体。使用氟基气体和氧气以引起各向同性蚀刻,因此,第二凹陷区域28可以通过第三凹陷蚀刻工艺来进一步加宽。
当在上述蚀刻条件下实施第三凹陷蚀刻工艺时,第二凹陷区域28可以进一步加宽例如约10nm至约15nm。当实施第三凹陷蚀刻工艺时,角状物的高度可以进一步减小。
利用使用TCP或ICP作为等离子源的高密度蚀刻设备来实施根据上述实施方案的第一凹陷蚀刻工艺和第二凹陷蚀刻工艺。在另一个实施方案中,第一凹陷蚀刻工艺和第二凹陷蚀刻工艺可以在安装有法拉第屏蔽的ICP型蚀刻设备中实施。而且,第一凹陷蚀刻工艺和第二凹陷蚀刻工艺可以在使用微波下游(Microwave Down Stream,MDS)、电子回旋共振(ECR)和螺旋(helical)之一作为等离子源的蚀刻设备中实施。
参考图4F,移除保留的氧化物层24A′并在包括凹陷区域100的硅衬底21上形成栅极绝缘层29。此后,在栅极绝缘层29上沉积导电层直至填充凹陷区域100,并且蚀刻所得结构以形成栅极30。因此,栅极之下的凹陷区域100变为晶体管的凹陷沟道。
图5说明显示根据本发明一个实施方案的角状物和凹陷区域的轮廓的SEM照片。
参考图5,可看出:根据本发明的角状物显著低于常规的角状物。而且,可看出:凹陷区域100具有双重轮廓而不是尖的轮廓。因此,即使当用器件隔离层填充的沟槽形成为具有约90°或更小的角度时,也可以最小化角状物的尺寸。由于第二凹陷区域通过第二凹陷蚀刻工艺得到加宽,所以即使当第一凹陷区域形成具有较小的线宽时,本发明也可以增加沟道长度。当第一凹陷区域的线宽减小时,可以防止与栅极的未对准。例如,传统技术形成凹陷区域的线宽为约39nm,但是本发明可以降低凹陷区域的线宽为约31nm。
结果,最小化了角状物,抑制了漏电流,并且改善了器件的刷新特性。因此,可以改善器件制造良品率并且减少制造成本。
用于减小角状物高度的最优蚀刻条件可以通过实验设计(DOE)来达到。
根据上述实施方案,即使当沟槽在STI工艺中形成为约90°或更小的角度时,也能够最小化凹陷区域的角状物。
而且,能够通过形成具有双重轮廓的凹陷区域来进一步增加沟道长度。
也能够在减小角状物的同时使通过栅极(passing gate)区域的场氧化物的损失最小化。通过栅极是与邻近于有源区末端的器件隔离层顶部交叉的栅电极。由于第二蚀刻相对于由氧化物层形成的器件隔离层具有高选择性,所以可以防止场氧化物损失。
如上所述,即使当沟槽在STI工艺中形成为约90°或更小的角度时,本发明也可以最小化凹陷区域的角状物。因此,本发明可以防止栅极绝缘层的特性劣化和由于栅极绝缘层特性劣化导致的应力集中。
本发明的实施方案可以通过形成具有双重轮廓的凹陷区域来进一步增加沟道长度。
本发明的实施方案也可以在减小角状物的同时最小化通过栅极区域的场氧化物损失。因此,本发明的实施方案可以改善半导体器件的特性。
虽然本发明已经对于具体的实施方案进行了描述,但是显而易见地的是,本领域技术人员可做出各种变化和改变而未脱离在所附权利要求中限定的本发明的精神和范围。
Claims (22)
1.一种在半导体器件中制造凹陷栅极的方法,所述方法包括:
蚀刻硅衬底以形成限定有源区的沟槽;
形成填隙所述沟槽的器件隔离层;
在所述硅衬底上形成硬掩模层,所述硬掩模层包括氧化物层和非晶碳层的堆叠结构,其中所述硬掩模层暴露所述有源区的沟道目标区;和
通过使用所述硬掩模层作为蚀刻阻挡层来对所述沟道目标区进行第一蚀刻和第二蚀刻以形成具有双重轮廓的凹陷区域,
其中在移除所述非晶碳层之后实施所述第二蚀刻。
2.根据权利要求1所述的方法,还包括:在所述第二蚀刻之后,原位进行第三蚀刻以增加所述凹陷区域的宽度。
3.根据权利要求1所述的方法,其中所述凹陷区域的形成包括:
使用所述非晶碳层作为蚀刻阻挡层实施所述第一蚀刻以形成第一凹陷区域;
移除所述非晶碳层;和
使用所述氧化物层作为蚀刻阻挡层实施所述第二蚀刻,以形成宽于所述第一凹陷区域的第二凹陷区域。
4.根据权利要求3所述的方法,其中在等离子体蚀刻设备中原位实施所述第一蚀刻、所述非晶碳层的移除和所述第二蚀刻。
5.根据权利要求4所述的方法,其中所述第一蚀刻和所述第二蚀刻使用氯基气体和溴基气体的混合物来实施。
6.根据权利要求5所述的方法,其中所述第一蚀刻和所述第二蚀刻在以下条件下实施:HBr对Cl2的流量比为约5:1,施加约5毫托至约20毫托的压力,约500W至约1500W的源功率,约100V至约300V的偏压功率。
7.根据权利要求4所述的方法,其中所述非晶碳层的移除使用流量为约200sccm至约1000sccm的O2等离子体并且通过施加源功率而不施加偏压功率来实施。
8.根据权利要求2所述的方法,其中所述第三蚀刻通过将氟基气体和氧气的混合物加入氯基气体和溴基气体的混合物来实施。
9.根据权利要求8所述的方法,其中所述氟基气体包括选自氟化硫气体、氟化氮气体和氟化碳气体中的一种。
10.根据权利要求8所述的方法,其中所述第三蚀刻在以下条件下实施:施加约20毫托至约100毫托的压力,约500W至约1500W的源功率,约50W或更小的偏压功率。
11.根据权利要求8所述的方法,其中所述溴基气体是HBr,所述氯基气体是Cl2。
12.根据权利要求4所述的方法,其中所述等离子蚀刻设备使用磁增强反应性离子蚀刻(MERIE)、变压器耦合等离子体(TCP)、感应耦合等离子体(ICP)、微波下游(MDS)、电子回旋共振(ECR)和螺旋中的一种作为等离子体源。
13.一种在半导体器件中形成凹陷沟道的方法,所述方法包括:
在半导体衬底上形成硬掩模层,所述硬掩模层包括钝化层和非晶碳层的堆叠结构,其中所述硬掩模层暴露所述半导体衬底的沟道目标区;
使用所述非晶碳层作为蚀刻阻挡层来蚀刻所述沟道目标区以形成第一凹陷区域;
移除所述非晶碳层;和
使用所述钝化层作为蚀刻阻挡层来蚀刻所述第一凹陷区域的底部以形成第二凹陷区域。
14.根据权利要求13所述的方法,其中在等离子体蚀刻设备中原位实施所述沟道目标区的蚀刻、所述非晶碳层的移除和所述第一凹陷区域的底部的蚀刻。
15.根据权利要求14所述的方法,其中所述沟道目标区的蚀刻和所述第一凹陷区域的底部的蚀刻使用相同的蚀刻气体、相同的压力、相同的源功率和相同的偏压功率来实施。
16.根据权利要求14所述的方法,其中所述非晶碳层的移除使用O2等离子体并且通过施加源功率而不施加偏压功率来实施。
17.根据权利要求14所述的方法,其中所述等离子体蚀刻设备使用磁增强反应性离子蚀刻(MERIE)、变压器耦合等离子体(TCP)、感应耦合等离子体(ICP)、微波下游(MDS)、电子回旋共振(ECR)和螺旋中的一种作为等离子体源。
18.根据权利要求13所述的方法,其中所述半导体衬底包括硅衬底,所述钝化层包括氧化物层。
19.根据权利要求13所述的方法,还包括:在蚀刻所述第一凹陷区域的底部之后,原位实施蚀刻以增加所述第二凹陷区域的宽度。
20.一种在半导体器件中制造凹陷栅极的方法,所述方法包括:
蚀刻硅衬底以形成限定有源区的沟槽;
在所述沟槽中形成器件隔离层;
在所述硅衬底上形成硬掩模层,所述硬掩模层包括氧化物层和非晶碳层,其中所述硬掩模层暴露所述有源区的沟道目标区;
使用所述非晶碳层作为蚀刻阻挡层来蚀刻所述沟道目标区以形成第一凹陷区域;
移除所述非晶碳层;
使用所述氧化物层作为蚀刻阻挡层来对所述第一凹陷区域的底部进行第二蚀刻以形成第二凹陷区域,其中所述第二凹陷区域宽于所述第一凹陷区域。
21.根据权利要求20所述的方法,还包括对所述凹陷区域进行第三蚀刻以加宽所述第二凹陷区域。
22.一种在半导体器件中形成凹陷沟道的方法,所述方法包括:
在半导体衬底上形成硬掩模层,所述硬掩模层包括钝化层和非晶碳层,其中所述硬掩模层暴露所述半导体衬底的沟道目标区;
使用所述非晶碳层作为蚀刻阻挡层来蚀刻所述沟道目标区以形成第一凹陷区域;
移除所述非晶碳层;和
使用所述钝化层作为蚀刻阻挡层来蚀刻所述第一凹陷区域的底部以形成第二凹陷区域,其中所述第二凹陷区域宽于所述第一凹陷区域。23.根据权利要求22所述的方法,还包括蚀刻所述第二凹陷区域的侧面以增加所述第二凹陷区域的宽度。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111627807A (zh) * | 2016-03-28 | 2020-09-04 | 株式会社日立高新技术 | 等离子处理方法以及等离子处理装置 |
CN113594031A (zh) * | 2021-07-29 | 2021-11-02 | 上海华力微电子有限公司 | 半导体器件的制备方法 |
Families Citing this family (123)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9484462B2 (en) | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US8975137B2 (en) * | 2011-07-11 | 2015-03-10 | Nanya Technology Corporation | Process of forming slit in substrate |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
CN102496576A (zh) * | 2011-12-28 | 2012-06-13 | 上海先进半导体制造股份有限公司 | 沟槽功率器件的制作方法 |
JP6054046B2 (ja) * | 2012-03-19 | 2016-12-27 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法 |
KR20130107628A (ko) | 2012-03-22 | 2013-10-02 | 삼성디스플레이 주식회사 | 트렌치 형성 방법, 금속 배선 형성 방법, 및 박막 트랜지스터 표시판의 제조 방법 |
US8872260B2 (en) * | 2012-06-05 | 2014-10-28 | Macronix International Co., Ltd. | Semiconductor device formation |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
US9023734B2 (en) | 2012-09-18 | 2015-05-05 | Applied Materials, Inc. | Radical-component oxide etch |
US9390937B2 (en) | 2012-09-20 | 2016-07-12 | Applied Materials, Inc. | Silicon-carbon-nitride selective etch |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US8969212B2 (en) | 2012-11-20 | 2015-03-03 | Applied Materials, Inc. | Dry-etch selectivity |
US8980763B2 (en) | 2012-11-30 | 2015-03-17 | Applied Materials, Inc. | Dry-etch for selective tungsten removal |
US8921234B2 (en) | 2012-12-21 | 2014-12-30 | Applied Materials, Inc. | Selective titanium nitride etching |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
US9040422B2 (en) | 2013-03-05 | 2015-05-26 | Applied Materials, Inc. | Selective titanium nitride removal |
US20140271097A1 (en) | 2013-03-15 | 2014-09-18 | Applied Materials, Inc. | Processing systems and methods for halide scavenging |
US9493879B2 (en) | 2013-07-12 | 2016-11-15 | Applied Materials, Inc. | Selective sputtering for pattern transfer |
US9773648B2 (en) | 2013-08-30 | 2017-09-26 | Applied Materials, Inc. | Dual discharge modes operation for remote plasma |
US9576809B2 (en) | 2013-11-04 | 2017-02-21 | Applied Materials, Inc. | Etch suppression with germanium |
US9520303B2 (en) | 2013-11-12 | 2016-12-13 | Applied Materials, Inc. | Aluminum selective etch |
US9245762B2 (en) | 2013-12-02 | 2016-01-26 | Applied Materials, Inc. | Procedure for etch rate consistency |
US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
US9385028B2 (en) | 2014-02-03 | 2016-07-05 | Applied Materials, Inc. | Air gap process |
US9499898B2 (en) | 2014-03-03 | 2016-11-22 | Applied Materials, Inc. | Layered thin film heater and method of fabrication |
US9299537B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9903020B2 (en) | 2014-03-31 | 2018-02-27 | Applied Materials, Inc. | Generation of compact alumina passivation layers on aluminum plasma equipment components |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9378969B2 (en) | 2014-06-19 | 2016-06-28 | Applied Materials, Inc. | Low temperature gas-phase carbon removal |
US9406523B2 (en) | 2014-06-19 | 2016-08-02 | Applied Materials, Inc. | Highly selective doped oxide removal method |
US9425058B2 (en) | 2014-07-24 | 2016-08-23 | Applied Materials, Inc. | Simplified litho-etch-litho-etch process |
US9378978B2 (en) | 2014-07-31 | 2016-06-28 | Applied Materials, Inc. | Integrated oxide recess and floating gate fin trimming |
US9496167B2 (en) | 2014-07-31 | 2016-11-15 | Applied Materials, Inc. | Integrated bit-line airgap formation and gate stack post clean |
US9659753B2 (en) | 2014-08-07 | 2017-05-23 | Applied Materials, Inc. | Grooved insulator to reduce leakage current |
US9553102B2 (en) | 2014-08-19 | 2017-01-24 | Applied Materials, Inc. | Tungsten separation |
US9478434B2 (en) * | 2014-09-24 | 2016-10-25 | Applied Materials, Inc. | Chlorine-based hardmask removal |
US9368364B2 (en) | 2014-09-24 | 2016-06-14 | Applied Materials, Inc. | Silicon etch process with tunable selectivity to SiO2 and other materials |
US9613822B2 (en) | 2014-09-25 | 2017-04-04 | Applied Materials, Inc. | Oxide etch selectivity enhancement |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US9502258B2 (en) | 2014-12-23 | 2016-11-22 | Applied Materials, Inc. | Anisotropic gap etch |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9373522B1 (en) | 2015-01-22 | 2016-06-21 | Applied Mateials, Inc. | Titanium nitride removal |
US9449846B2 (en) | 2015-01-28 | 2016-09-20 | Applied Materials, Inc. | Vertical gate separation |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9881805B2 (en) | 2015-03-02 | 2018-01-30 | Applied Materials, Inc. | Silicon selective removal |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US9865484B1 (en) | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
US10062575B2 (en) | 2016-09-09 | 2018-08-28 | Applied Materials, Inc. | Poly directional etch by oxidation |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US10062585B2 (en) | 2016-10-04 | 2018-08-28 | Applied Materials, Inc. | Oxygen compatible plasma source |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US9721789B1 (en) | 2016-10-04 | 2017-08-01 | Applied Materials, Inc. | Saving ion-damaged spacers |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US9947549B1 (en) | 2016-10-10 | 2018-04-17 | Applied Materials, Inc. | Cobalt-containing material removal |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10043684B1 (en) | 2017-02-06 | 2018-08-07 | Applied Materials, Inc. | Self-limiting atomic thermal etching systems and methods |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10049891B1 (en) | 2017-05-31 | 2018-08-14 | Applied Materials, Inc. | Selective in situ cobalt residue removal |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10453738B2 (en) * | 2017-12-22 | 2019-10-22 | Texas Instruments Incorporated | Selective etches for reducing cone formation in shallow trench isolations |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
TWI716818B (zh) | 2018-02-28 | 2021-01-21 | 美商應用材料股份有限公司 | 形成氣隙的系統及方法 |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003092349A (ja) * | 2001-09-18 | 2003-03-28 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US20030057184A1 (en) * | 2001-09-22 | 2003-03-27 | Shiuh-Sheng Yu | Method for pull back SiN to increase rounding effect in a shallow trench isolation process |
US20060113590A1 (en) * | 2004-11-26 | 2006-06-01 | Samsung Electronics Co., Ltd. | Method of forming a recess structure, recessed channel type transistor and method of manufacturing the recessed channel type transistor |
JP2006237356A (ja) * | 2005-02-25 | 2006-09-07 | Toshiba Corp | 半導体装置の製造方法 |
JP4982962B2 (ja) * | 2005-04-14 | 2012-07-25 | 富士電機株式会社 | 半導体装置の製造方法 |
KR100744068B1 (ko) * | 2005-04-29 | 2007-07-30 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 제조 방법 |
KR20060118072A (ko) | 2005-05-16 | 2006-11-23 | 삼성전자주식회사 | 리세스형 트랜지스터 및 그 제조방법 |
KR100732767B1 (ko) * | 2005-12-29 | 2007-06-27 | 주식회사 하이닉스반도체 | 반도체 소자의 리세스 채널용 트렌치 형성방법 |
JP2007194333A (ja) * | 2006-01-18 | 2007-08-02 | Elpida Memory Inc | 半導体装置の製造方法 |
KR100753083B1 (ko) * | 2006-04-28 | 2007-08-31 | 주식회사 하이닉스반도체 | 반도체소자의 리세스채널 형성 방법 |
KR100954116B1 (ko) * | 2006-11-06 | 2010-04-23 | 주식회사 하이닉스반도체 | 반도체 소자의 리세스패턴 형성방법 |
KR100818654B1 (ko) * | 2006-12-01 | 2008-04-01 | 주식회사 하이닉스반도체 | 벌브형 리세스 게이트를 갖는 반도체 소자 및 그 제조 방법 |
KR100780658B1 (ko) * | 2006-12-27 | 2007-11-30 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US20080160742A1 (en) * | 2006-12-27 | 2008-07-03 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with recess gate |
-
2008
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- 2008-09-26 TW TW097137008A patent/TWI425578B/zh not_active IP Right Cessation
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111627807A (zh) * | 2016-03-28 | 2020-09-04 | 株式会社日立高新技术 | 等离子处理方法以及等离子处理装置 |
CN111627807B (zh) * | 2016-03-28 | 2023-08-29 | 株式会社日立高新技术 | 等离子处理方法以及等离子处理装置 |
CN113594031A (zh) * | 2021-07-29 | 2021-11-02 | 上海华力微电子有限公司 | 半导体器件的制备方法 |
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CN101399194B (zh) | 2010-12-22 |
US7838361B2 (en) | 2010-11-23 |
JP2009088522A (ja) | 2009-04-23 |
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KR20090033124A (ko) | 2009-04-01 |
TW200915439A (en) | 2009-04-01 |
US20090087960A1 (en) | 2009-04-02 |
KR101070292B1 (ko) | 2011-10-06 |
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