TWI425578B - 製造半導體元件之凹陷閘極之方法 - Google Patents

製造半導體元件之凹陷閘極之方法 Download PDF

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TWI425578B
TWI425578B TW097137008A TW97137008A TWI425578B TW I425578 B TWI425578 B TW I425578B TW 097137008 A TW097137008 A TW 097137008A TW 97137008 A TW97137008 A TW 97137008A TW I425578 B TWI425578 B TW I425578B
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Yong-Tae Cho
Eun-Mi Kim
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Hynix Semiconductor Inc
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Description

製造半導體元件之凹陷閘極之方法
本發明主張於2007年9月28日申請之韓國專利申請案號2007－0098221之優先權，將其全文以參考的方式併入本文。
本發明關於半導體元件製造，尤其是關於一種製造半導體元件之凹陷閘極之方法。
在半導體元件之製造中，使用形成平面閘極之方法來於平面主動區上形成閘極。然而，因圖案尺寸縮減而造成的通道長度減少及因基板之離子佈植掺雜濃度增加而造成的電場增加，因而造成接面漏電流(junction leakage)。這會使其難以獲得元件之更新特性。
為了解決上述限制，已提出一種三維凹陷閘極製程作為替代的形成閘極的方法，其在蝕刻主動區後形成閘極。凹陷閘極製程使其可以增加通道長度並減少離子佈植掺雜濃度，因而改善元件之更新特性。
第1A至1C圖說明根據先前技術的製造半導體元件之凹陷閘極之方法。在此，每一圖式的右邊部分為沿著I－I’線之剖面圖。
參照第1A圖，蝕刻矽基板11之元件隔離區而形成溝槽12，及將元件隔離層13形成於溝槽12中。此製程稱為矽溝槽隔離(STI)製程。
將非晶質碳層14形成在結果結構(resulting structure) 上並在非晶質碳層14上實施用以形成凹陷區之遮罩製程(mask process)，藉以形成光阻圖案15。
使用光阻圖案15作為蝕刻阻障而蝕刻非晶質碳層14。
參照第1B圖，使用非晶質碳層14作為蝕刻阻障，蝕刻矽基板11而形成作為電晶體通道之凹陷區16。凹陷區16亦稱為凹陷通道。
參照第1C圖，在含有凹陷區16之矽基板11上形成閘極絕緣層17。將導電層沉積於閘極絕緣層17上直到填滿凹陷區16，及蝕刻沉積的導電層而形成閘極18。
然而，於半導體元件之超微細圖案化製程期間，因能形成三維凹陷閘極之凹陷區的尺寸減少，而在電漿蝕刻製程中使凹陷區16的底部輪廓形成V型輪廓。此造成牛角效應(horn effect)，其中矽(Si)殘渣(參照如牛角H)位於與元件隔離層13相鄰之上區中。矽殘渣係由聚合物所產生，其中聚合物則由非晶質碳層之碳的再沉積所製得。
第2圖說明顯示根據先前技術之牛角的掃瞄式電子顯微鏡(SEM)照片。能由第2圖觀察到牛角位於與元件隔離層相鄰之上區中。
牛角H造成閘極絕緣層17劣化。牛角H係應力集中點並成為漏電流的來源，因而降低元件生產良率及使得DRAM難以製造。
參照第3圖，牛角H係在以約90°以下之角度形成溝槽12側壁時所形成的凹陷區16之V型輪廓所造成，其中溝 槽12係以元件隔離層13予以間隙填充。
第3圖說明顯示根據先前技術之以元件隔離層予以間隙填充的溝槽之側壁角度之SEM照片。能由第3圖觀察到溝槽係以約90°以下之角度形成。
本發明實施例係針對提供一種製造半導體元件之凹陷閘極之方法，其能在形成凹陷閘極製程期間抑制凹陷區之蝕刻製程中牛角的產生。
本發明實施例亦針對提供一種形成半導體元件之凹陷通道之方法，其能進一步增加通道長度同時減少凹陷通道的線寬。
根據本發明之一態樣，提供一種製造半導體元件之凹陷閘極之方法。該方法包括：蝕刻矽基板而形成界定主動區之溝槽；形成間隙填充溝槽之元件隔離層；於矽基板上形成硬遮罩層，硬遮罩層包含氧化層及非晶質碳層之堆疊，其中硬遮罩層暴露主動區之通道目標區；及藉由使用硬遮罩層作為蝕刻阻障而將通道目標區進行第一蝕刻及第二蝕刻以形成具有雙重輪廓之凹陷區，其中在移除非晶質碳層後實施第二蝕刻。
根據本發明之另一態樣，提供一種形成半導體元件之凹陷通道之方法。該方法包括：於半導體基板上形成硬遮罩層，硬遮罩層包括鈍化層(passivation layer)及非晶質碳層之堆疊，其中硬遮罩層暴露半導體基板之通道目標區； 使用非晶質碳層作為蝕刻阻障而蝕刻通道目標區以形成第一凹陷區；移除非晶質碳層；及使用鈍化層作為蝕刻阻障而蝕刻第一凹陷區底部以形成第二凹陷區。
根據本發明之另一態樣，提供一種製造半導體元件之凹陷閘極之方法。該方法包括：蝕刻矽基板而形成界定主動區之溝槽；於溝槽中形成元件隔離層；於矽基板上形成硬遮罩層，硬遮罩層包含氧化層及非晶質碳層，其中硬遮罩層暴露主動區之通道目標區；使用非晶質碳層作為蝕刻阻障而將通道目標區實施第一蝕刻以形成第一凹陷區；移除非晶質碳層；使用氧化層作為蝕刻阻障而將第一凹陷區底部實施第二蝕刻以形成第二凹陷區，其中第二凹陷區比第一凹陷區寬。
根據本發明之另一態樣，提供一種形成半導體元件之凹陷通道之方法。該方法包括：於半導體基板上形成硬遮罩層，硬遮罩層包括鈍化層及非晶質碳層，其中硬遮罩層暴露半導體基板之通道目標區；使用非晶質碳層作為蝕刻阻障而蝕刻通道目標區以形成第一凹陷區；移除非晶質碳層；及使用鈍化層作為蝕刻阻障而蝕刻第一凹陷區底部以形成第二凹陷區，其中第二凹陷區比第一凹陷區寬。
以下，將參照隨附圖式詳細敘述根據本發明之製造半導體元件之凹陷閘極之方法。
請注意本文中當指示如層、薄膜、圖案及區域之元件為 於(在)另一元件上/於(在)另一元件下時，其可能為直接於(在)另一元件上/於(在)另一元件下，及可能存在一個以上介於其間之元件。
本發明實施例中，在用以形成凹陷區或凹陷通道之凹陷蝕刻製程中使用具有鈍化層(例如氧化層)及非晶質碳層之堆疊的硬遮罩層作為蝕刻阻障。凹陷蝕刻製程包括使用非晶質碳層作為蝕刻阻障之第一凹陷蝕刻製程及使用鈍化層作為蝕刻阻障之第二凹陷蝕刻製程。使用相同的蝕刻氣體、相同的壓力、相同的來源功率(source power)及相同的偏壓功率(bias power)來實施第一凹陷蝕刻製程及第二凹陷蝕刻製程，且在實施第二凹陷蝕刻製程前預先移除非晶質碳層。換言之，係於非晶質碳層不存在的情況下實施第二凹陷蝕刻製程。在此情況下，第二凹陷蝕刻製程中所產生之聚合物量小於第一凹陷蝕刻製程中所產生者。因此，可形成較寬的凹陷區並可防止在與元件隔離層相鄰的區域中產生牛角。
第4A至4F圖說明根據本發明實施例的製造半導體元件之凹陷閘極之方法。在此，每一圖式的右邊部分為沿著Ⅱ－Ⅱ’線之剖面圖。
參照第4A圖，使用淺溝槽隔離(STI)製程來形成元件隔離層23而填充矽基板21之溝槽22。由溝槽22界定主動區，及可以約90°以下的角度形成溝槽22。
於矽基板21上形成硬遮罩層24。硬遮罩層24可包含氧 化層或非晶質碳層。較佳為硬遮罩層24可含有氧化層24A及非晶質碳層24B之堆疊。氧化層24A亦作為保護矽基板21表面的鈍化層。
於硬遮罩層24上形成抗反射塗布(ARC)層25，並在結果結構上實施用於形成凹陷區之遮罩製程，以形成光阻圖案26。ARC層25可為有機底部抗反射塗布(OBARC)層。
參照第4B圖，使用光阻圖案26作為蝕刻阻障來蝕刻ARC層25及硬遮罩層24。可使用如電容式偶合電漿(CCP)型或磁場強化反應性離子蝕刻(MERIE)型之電漿源來實施這些蝕刻製程。使用含有N2 氣體及O2 氣體之混合物，以及同時施加來源功率及偏壓功率來蝕刻ARC層25及非晶質碳層24B。使用氧化層24A作為蝕刻中止層來蝕刻非晶質碳層24B。之後，使用含有O2 氣體、及CFX (例如CF4 )氣體與CHFX (例如CHF3 )氣體之一的混合物來蝕刻氧化層24A。
參照第4C圖，移除光阻圖案26及殘留的ARC層25’。使用殘留的非晶質碳層24B’作為蝕刻阻障，實施第一凹陷蝕刻製程而將矽基板21蝕刻至預定深度。藉由第一凹陷蝕刻製程形成第一凹陷區27。使用變壓式偶合電漿(TCP)或感應偶合電漿(ICP)作為電漿源及使用氯系氣體及溴系氣體之混合物實施第一凹陷蝕刻製程。例如，較佳為使用HBr：Cl2 之流量比約為5：1，施加約5 mtorr至約20 mtorr之壓力、約500 W至約1500 W之來源功率及約100 V至約 300 V之偏壓功率來實施第一凹陷蝕刻製程。
藉由上述的第一凹陷蝕刻製程，第一凹陷區27具有垂直輪廓及具有約200至約500之深度。於另一實施例中，可在用於蝕刻非晶質碳層24B之腔中原位實施第一凹陷蝕刻製程。
參照第4D圖，在用於實施第一凹陷蝕刻製程之蝕刻設備中原位移除殘留的非晶質碳層24B’。為此目的，使用約200 sccm至約1000 sccm之O2 電漿及施加來源功率而不施加偏壓功率。
參照第4E圖，使用殘留的氧化層24A’作為蝕刻阻障，實施第二凹陷蝕刻製程來蝕刻第一凹陷區27底部，藉以形成第二凹陷區28。在此，在用於實施第一凹陷蝕刻製程及移除殘留的非晶質碳層24B’之蝕刻設備中原位實施第二凹陷蝕刻製程。例如，可在使用氯系氣體及溴系氣體之混合物的TCP或ICP型電漿源之條件下實施第二凹陷蝕刻製程。例如，較佳為藉由施加約10 mtorr至約30 mtorr之壓力、約500 W至約1500 W之來源功率及約100 V至約300 V之偏壓功率來實施第二凹陷蝕刻製程。特別是，若分別使用HBr及Cl2 作為溴系氣體及氯系氣體，則較佳地HBr：Cl2 之流量比為約5：1。藉由在上述蝕刻條件下蝕刻第一凹陷區27底部所形成之第二凹陷區28具有隨著第二凹陷區28深度增加而逐漸變寬的輪廓。較佳為將第二凹陷區28形成得比第一凹陷區27深，例如，至約700至約1000之厚 度。
根據上述多個製程，第一凹陷區27及第二凹陷區28構成具有雙重輪廓之凹陷區100，其中雙重輪廓具有不同的頂部及底部輪廓。
第一凹陷區27及第二凹陷區28因下列原因而具有不同輪廓。
因為使用殘留的非晶質碳層24B’作為蝕刻阻障而蝕刻第一凹陷區27，由殘留的非晶質碳層24B’之碳產生大量的聚合物。所產生的聚合物被再沉積使得蝕刻輪廓具有垂直輪廓。
另一方面，在移除殘留的非晶質碳層24B’後形成第二凹陷區28，而由碳產生相對小量的聚合物。如此，因為沒有來自碳聚合物之蝕刻障礙，所以第二凹陷區28比第一凹陷區27寬。
即，第二凹陷區28被蝕刻多於第一凹陷區27。如此，能抑制牛角發生於與元件隔離層23相鄰之區域中，且即使產生牛角，其高度能被明顯地降低。
具有雙重輪廓之凹陷區100具有加寬的輪廓，其中底部寬度大於傳統的凹陷區約數十奈米。因而，不像先前技術，其可形成具有縮小化牛角的凹陷區。參照第4E圖，元件符號P1代表傳統的輪廓而元件符號P2代表根據本發明實施例的輪廓。可由第4E圖觀察到與傳統的輪廓相比，根據本發明實施例之輪廓具有相當低的牛角。
在用於形成加寬的第二凹陷區28之第二凹陷蝕刻條件之中，壓力、功率及氣體比率非常重要。較佳為藉由施加約10 mtorr至約30 mtorr之壓力、約500 W至約1500 W之來源功率及約100 V至約300 V之偏壓功率來實施第二凹陷蝕刻製程。
在另一實施例中，在形成第二凹陷區28後，可額外地實施第三凹陷蝕刻製程來進一步加寬第二凹陷區28的寬度。第三凹陷蝕刻製程係原位實施。例如，可使用TCP或ICP作為電漿源，及藉由使用HBr/Cl2 氣體與小量的SF6 /O2 氣體之混合物來實施第三凹陷蝕刻製程。較佳為藉由施加約20 mtorr至約100 mtorr之壓力、約500 W至約1500 W之來源功率及約50 W以下之偏壓功率來實施第三凹陷蝕刻製程。使用氯系氣體及氟系氣體之混合物、與小量的氧氣體及氟系氣體之混合物來實施第三凹陷蝕刻製程。氟系氣體可為氟化氮(NFX )氣體或氟化碳(CFX )氣體，以及如SF6 氣體之氟化硫氣體。氟化氮氣體可為NF3 氣體，而氟化碳氣體可為CF4 氣體。使用氟系氣體及氧氣體來引發等向性蝕刻，且因此，能藉由第三凹陷蝕刻製程進一步加寬第二凹陷區28。
當在上述蝕刻條件下實施第三凹陷蝕刻製程時，能進一步將第二凹陷區28加寬例如約10 nm至約15 nm。當實施第三凹陷蝕刻製程，能進一步減少牛角高度。
利用使用TCP或ICP作為電漿源之高密度蝕刻設備來實 施根據上述實施例之第一凹陷蝕刻製程及第二凹陷蝕刻製程。在另一實施例中，可在安裝有法拉第屏蔽之ICP型蝕刻設備中實施第一凹陷蝕刻製程及第二凹陷蝕刻製程。同樣地，可在使用微波下降流(MDS)、電子迴旋共振(ECR)及螺旋型(Helical)之一作為電漿源的蝕刻設備中實施第一凹陷蝕刻製程及第二凹陷蝕刻製程。
參照第4F圖，移除殘留的氧化層24A’及在含有凹陷區100的矽基板21上形成閘極絕緣層29。之後，將導電層沉積於閘極絕緣層29上直到凹陷區100被填滿，及蝕刻結果結構而形成閘極30。因此，在閘極下之凹陷區100成為電晶體的凹陷通道。
第5圖說明顯示根據本發明實施例之牛角及凹陷區輪廓的SEM照片。
參照第5圖，能觀察到相較於傳統的牛角，根據本發明之牛角係相當低。同樣地，能觀察到凹陷區100具有雙重輪廓而非尖頭輪廓(pointed profile)。因此，即使當以約90°以下之角度形成填有元件隔離層之溝槽時，亦能減少牛角的尺寸。因為藉由第二凹陷蝕刻製程加寬第二凹陷區，所以即使當將第一凹陷區形成為具有較小線寬時，本發明亦能增加通道長度。當縮減第一凹陷區之線寬時，能防止與閘極之未對準(misalignment with a gate electrode)。提供參考，當先前技術將凹陷區線寬形成為約39 nm時，本發明能將凹陷區線寬縮減至為約31 nm。
結果，將牛角極小化，抑制漏電流，而改善元件之更新特性。因此，能改善元件製造良率及減少製造成本。
能藉由實驗設計(DOE)來達成用以減少牛角高度之最適化蝕刻條件。
根據上述實施例，即使當在STI製程中以約90°以下之角度形成溝槽時，亦可將凹陷區的牛角減到最少。
同樣地，可藉由形成具有雙重輪廓之凹陷區而進一步增加通道長度。
亦可將通過閘極(passing gate)區域的場氧化物損失(field oxide loss)減到最少同時減少牛角。通過閘極係與相鄰於主動區端部的元件隔離層頂部交叉之閘極。因為相對於由氧化層所形成的元件隔離層，第二蝕刻具有高選擇性，所以能防止場氧化物損失。
如上述，即使當在STI製程中以約90°以下之角度形成溝槽時，本發明亦能將凹陷區的牛角減到最少。因此，本發明能防止閘極絕緣層之特性劣化及由於閘極絕緣層之特性劣化所引起之應力集中。
本發明實施例能藉由形成具有雙重輪廓之凹陷區而進一步增加通道長度。
本發明實施例亦能將通過閘極區域的場氧化物損失減到最少同時減少牛角。因此，本發明實施例能改善半導體元件特性。
雖然藉由參照特定實施例描述本發明，但對本領域之具 有通常知識者而言，在不悖離下述申請專利範圍所界定的本發明之精神及範圍的情況下，可輕易進行各種變更及替代。
11、21‧‧‧矽基板
12、22‧‧‧溝槽
13、23‧‧‧元件隔離層
14、24B‧‧‧非晶質碳層
15、26‧‧‧光阻圖案
16‧‧‧凹陷區
17、29‧‧‧閘極絕緣層
18、30‧‧‧閘極
24‧‧‧硬遮罩層
24A‧‧‧氧化層
24A’‧‧‧殘留的氧化層
24B’‧‧‧殘留的非晶質碳層
25‧‧‧抗反射塗布(ARC)層
25’‧‧‧殘留的ARC層
27‧‧‧第一凹陷區
28‧‧‧第二凹陷區
100‧‧‧凹陷區
H‧‧‧牛角
P1‧‧‧傳統的輪廓
P2‧‧‧根據本發明實施例的輪廓
第1A至1C圖說明根據先前技術的製造半導體元件之凹陷閘極之方法。
第2圖說明顯示根據先前技術之牛角的SEM照片。
第3圖說明顯示根據先前技術之以元件隔離層予以間隙填充的溝槽之側壁角度之SEM照片。
第4A至4F圖說明根據本發明實施例的製造半導體元件之凹陷閘極之方法。
第5圖說明顯示根據本發明實施例之牛角及凹陷區輪廓的SEM照片。
21‧‧‧矽基板
22‧‧‧溝槽
23‧‧‧元件隔離層
24A’‧‧‧殘留的氧化層
27‧‧‧第一凹陷區
28‧‧‧第二凹陷區
100‧‧‧凹陷區
P1‧‧‧傳統的輪廓
P2‧‧‧根據本發明實施例的輪廓

Claims (23)

  1. 一種製造半導體元件之凹陷閘極之方法，該方法包括：蝕刻矽基板而形成界定主動區之溝槽；形成間隙填充(gap－fill)該溝槽之元件隔離層；於該矽基板上形成硬遮罩層，該硬遮罩層包含氧化層及非晶質碳層之堆疊，其中該硬遮罩層暴露該主動區之通道目標區；及藉由使用該硬遮罩層作為蝕刻阻障而將該通道目標區進行第一蝕刻及第二蝕刻以形成具有雙重輪廓之凹陷區，其中在移除該非晶質碳層後實施該第二蝕刻。
  2. 如申請專利範圍第1項之方法，其中進一步包括在該第二蝕刻後，實施原位第三蝕刻以增加該凹陷區之寬度。
  3. 如申請專利範圍第1項之方法，其中形成該凹陷區包括：使用該非晶質碳層作為蝕刻阻障而實施該第一蝕刻以形成第一凹陷區；移除該非晶質碳層；及使用該氧化層作為蝕刻阻障而實施該第二蝕刻以形成第二凹陷區，其中該第二凹陷區比該第一凹陷區寬。
  4. 如申請專利範圍第3項之方法，其中在電漿蝕刻設備中原位實施該第一蝕刻、該非晶質碳層之移除、及該第二蝕刻。
  5. 如申請專利範圍第4項之方法，其中使用氯系氣體及溴 系氣體之混合物實施該第一蝕刻及該第二蝕刻。
  6. 如申請專利範圍第5項之方法，其中以HBr：Cl2 為約5：1之流量比、施加約5 mtorr至約20 mtorr之壓力、約500 W至約1500 W之來源功率(source power)、及約100 V至約300 V之偏壓功率(bias power)來實施該第一蝕刻及該第二蝕刻。
  7. 如申請專利範圍第4項之方法，其中使用流量為約200 sccm至約1000 sccm之O2 電漿及藉由施加來源功率而不施加偏壓功率來移除該非晶質碳層。
  8. 如申請專利範圍第2項之方法，其中藉由將氟系氣體及氧氣體之混合物添加至氯系氣體及溴系氣體之混合物中來實施該第三蝕刻。
  9. 如申請專利範圍第8項之方法，其中該氟系氣體包括氟化硫氣體、氟化氮氣體、及氟化碳氣體之一者。
  10. 如申請專利範圍第8項之方法，其中藉由施加約20 mtorr至約100 mtorr之壓力、約500 W至約1500 W之來源功率、及約50 W以下之偏壓功率來實施該第三蝕刻。
  11. 如申請專利範圍第8項之方法，其中該溴系氣體為HBr及該氯系氣體為Cl2 。
  12. 如申請專利範圍第4項之方法，其中該電漿蝕刻設備使用磁場強化反應性離子蝕刻(MERIE)、變壓式偶合電漿(TCP)、感應偶合電漿(ICP)、微波下降流(MDS)、電子迴旋共振(ECR)、及螺旋型(Helical)之一者作 為電漿源。
  13. 一種形成半導體元件之凹陷通道之方法，該方法包括：於半導體基板上形成硬遮罩層，該硬遮罩層包括鈍化層(passivation layer)及非晶質碳層之堆疊，其中該硬遮罩層暴露該半導體基板之通道目標區；使用該非晶質碳層作為蝕刻阻障而蝕刻該通道目標區以形成第一凹陷區；移除該非晶質碳層；及使用該鈍化層作為蝕刻阻障而蝕刻該第一凹陷區底部以形成第二凹陷區。
  14. 如申請專利範圍第13項之方法，其中在電漿蝕刻設備中原位實施該蝕刻通道目標區、該移除非晶質碳層、及該蝕刻第一凹陷區底部。
  15. 如申請專利範圍第14項之方法，其中使用相同的蝕刻氣體、相同的壓力、相同的來源功率、及相同的偏壓功率來實施該蝕刻通道目標區及該蝕刻第一凹陷區底部。
  16. 如申請專利範圍第14項之方法，其中使用O2 電漿及藉由施加來源功率而不施加偏壓功率來移除該非晶質碳層。
  17. 如申請專利範圍第14項之方法，其中該電漿蝕刻設備使用磁場強化反應性離子蝕刻(MERIE)、變壓式偶合電漿(TCP)、感應偶合電漿(ICP)、微波下降流(MDS)、電子迴旋共振(ECR)、及螺旋型(Helical)之一者作 為電漿源。
  18. 如申請專利範圍第13項之方法，其中該半導體基板包括矽基板及該鈍化層包括氧化層。
  19. 如申請專利範圍第13項之方法，其中進一步包括在蝕刻該第一凹陷區底部後，實施原位蝕刻以增加該第二凹陷區之寬度。
  20. 一種製造半導體元件之凹陷閘極之方法，該方法包括：蝕刻矽基板而形成界定主動區之溝槽；於該溝槽中形成元件隔離層；於該矽基板上形成硬遮罩層，該硬遮罩層包含氧化層及非晶質碳層，其中該硬遮罩層暴露該主動區之通道目標區；使用該非晶質碳層作為蝕刻阻障而將該通道目標區進行第一蝕刻以形成第一凹陷區；移除該非晶質碳層；使用氧化層作為蝕刻阻障而將第一凹陷區底部進行第二蝕刻以形成第二凹陷區，其中該第二凹陷區比該第一凹陷區寬。
  21. 如申請專利範圍第20項之方法，其中進一步包括將該凹陷區實施第三蝕刻以加寬該第二凹陷區。
  22. 一種形成半導體元件之凹陷通道之方法，該方法包括：於半導體基板上形成硬遮罩層，該硬遮罩層包括鈍化層及非晶質碳層，其中該硬遮罩層暴露該半導體基板之 通道目標區；使用該非晶質碳層作為蝕刻阻障而蝕刻該通道目標區以形成第一凹陷區；移除該非晶質碳層；及使用該鈍化層作為蝕刻阻障而蝕刻該第一凹陷區底部以形成第二凹陷區，其中該第二凹陷區比該第一凹陷區寬。
  23. 如申請專利範圍第22項之方法，其中進一步包括蝕刻該第二凹陷區之側邊以增加該第二凹陷區之寬度。
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