CN101393848A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN101393848A
CN101393848A CNA2008101612067A CN200810161206A CN101393848A CN 101393848 A CN101393848 A CN 101393848A CN A2008101612067 A CNA2008101612067 A CN A2008101612067A CN 200810161206 A CN200810161206 A CN 200810161206A CN 101393848 A CN101393848 A CN 101393848A
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CN
China
Prior art keywords
semiconductor device
insulating layer
semiconductor
semiconductor substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2008101612067A
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English (en)
Chinese (zh)
Inventor
町田洋弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Publication of CN101393848A publication Critical patent/CN101393848A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H10W46/503—Located in scribe lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
CNA2008101612067A 2007-09-18 2008-09-18 半导体器件的制造方法 Pending CN101393848A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007241374 2007-09-18
JP2007241374A JP5064157B2 (ja) 2007-09-18 2007-09-18 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
CN101393848A true CN101393848A (zh) 2009-03-25

Family

ID=40030274

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2008101612067A Pending CN101393848A (zh) 2007-09-18 2008-09-18 半导体器件的制造方法

Country Status (6)

Country Link
US (1) US7772091B2 (https=)
EP (1) EP2040288A2 (https=)
JP (1) JP5064157B2 (https=)
KR (1) KR20090029660A (https=)
CN (1) CN101393848A (https=)
TW (1) TW200915440A (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8053279B2 (en) 2007-06-19 2011-11-08 Micron Technology, Inc. Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
JP5432481B2 (ja) 2008-07-07 2014-03-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP2010109182A (ja) * 2008-10-30 2010-05-13 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP5728947B2 (ja) * 2011-01-06 2015-06-03 セイコーエプソン株式会社 アライメントマーク形成方法、ノズル基板形成方法、ノズル基板および液滴吐出ヘッド
TWI464857B (zh) * 2011-05-20 2014-12-11 精材科技股份有限公司 晶片封裝體、其形成方法、及封裝晶圓
US10008413B2 (en) * 2013-08-27 2018-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level dicing method
KR102288381B1 (ko) * 2014-08-20 2021-08-09 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10163805B2 (en) * 2016-07-01 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
KR20190052957A (ko) * 2017-11-09 2019-05-17 에스케이하이닉스 주식회사 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지
US10607941B2 (en) * 2018-04-30 2020-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device
CN111200907B (zh) * 2018-11-20 2021-10-19 宏启胜精密电子(秦皇岛)有限公司 无撕膜内埋式电路板及其制作方法
CN112770495B (zh) * 2019-10-21 2022-05-27 宏启胜精密电子(秦皇岛)有限公司 全向内埋模组及制作方法、封装结构及制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1106036C (zh) * 1997-05-15 2003-04-16 日本电气株式会社 芯片型半导体装置的制造方法
JP2000077312A (ja) * 1998-09-02 2000-03-14 Mitsubishi Electric Corp 半導体装置
JP4037561B2 (ja) * 1999-06-28 2008-01-23 株式会社東芝 半導体装置の製造方法
JP2002057251A (ja) * 2000-08-07 2002-02-22 Hitachi Ltd 半導体装置及びその製造方法
US6900532B1 (en) * 2000-09-01 2005-05-31 National Semiconductor Corporation Wafer level chip scale package
JP3609761B2 (ja) * 2001-07-19 2005-01-12 三洋電機株式会社 半導体装置の製造方法
JP4260405B2 (ja) * 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3614828B2 (ja) * 2002-04-05 2005-01-26 沖電気工業株式会社 チップサイズパッケージの製造方法
JP4134866B2 (ja) * 2003-09-22 2008-08-20 カシオ計算機株式会社 封止膜形成方法
JP3953027B2 (ja) * 2003-12-12 2007-08-01 ソニー株式会社 半導体装置およびその製造方法
US7442624B2 (en) * 2004-08-02 2008-10-28 Infineon Technologies Ag Deep alignment marks on edge chips for subsequent alignment of opaque layers
JP4636839B2 (ja) * 2004-09-24 2011-02-23 パナソニック株式会社 電子デバイス
JP4105202B2 (ja) * 2006-09-26 2008-06-25 新光電気工業株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
EP2040288A2 (en) 2009-03-25
JP2009076496A (ja) 2009-04-09
TW200915440A (en) 2009-04-01
KR20090029660A (ko) 2009-03-23
JP5064157B2 (ja) 2012-10-31
US20090075457A1 (en) 2009-03-19
US7772091B2 (en) 2010-08-10

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