CN101243552B - 一种射频识别设备和用于制造射频识别设备的方法 - Google Patents

一种射频识别设备和用于制造射频识别设备的方法 Download PDF

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CN101243552B
CN101243552B CN2006800293699A CN200680029369A CN101243552B CN 101243552 B CN101243552 B CN 101243552B CN 2006800293699 A CN2006800293699 A CN 2006800293699A CN 200680029369 A CN200680029369 A CN 200680029369A CN 101243552 B CN101243552 B CN 101243552B
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conductive
coating
substrate
conductive coating
patterning
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CN101243552A (zh
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莱斯特·E·伯吉斯
F·佳里·科瓦奇
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    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

一种射频识别设备(RFID)，包括不导电第一基板、安装到载体基板且具有至少一个导电端子的集成电路、以及施加到非一5导电基板且与至少一个导电端子接触的图案化的导电涂层。图案化的导电涂层包括聚合物基质和导电微粒填料，该聚合物基质能够经受至少2％弹性形变而在用作天线的图案化的导电涂层的导电特性中没有显著变化。可以通过将IC 0芯片贴附到具有图案化的导电涂层的基板的表面，并且施加桥接涂层以将IC芯片的端子连接到天线上，来制造该RFID。

Description

一种射频识别设备和用于制造射频识别设备的方法
相关申请的交叉引用
本申请要求2005年6月9日提交的美国临时申请序列号60/688,875的优选权，在此将其全部内容引入以供参考。
技术领域
本发明涉及RFID标签，更具体地涉及一种直接无铅(non-lead)方法，用于将集成电路(IC)管芯芯片的端子焊盘电接合到载体基板或安装的天线上，从而提供单一平面配置的设备。
背景技术
射频识别(RFID)是公知的，并且被广泛用于，例如，跟踪RFID应答机或“标签”附连到的诸如商品、动物、机动车等等的可移动物。标签通常包括计算机芯片和天线，并且由离标签一些距离的读取设备来读取。标签可以是无源标签，其没有电源但由读取器传输的射频能量来激活，或是有源标签，其具有自身的电源，例如电池。RFID芯片通常包括其中存储有数字信息的半导体存储器，并且可以是电可擦写可编程只读存储器(EEPROM)或类似的电存储设备。在被称为“背散射调制”技术下，RFID标签通过改变它们的天线匹配阻抗来反射变化量的由RFID问答机(读取设备)提供的电磁场来传输存储的数据。
RFID系统能够操作在多种无线频率下。低频率(125-148kHz)通常需要读取器与标签非常接近(在约3英寸内)。超高频率(UHF)，通常为850到960MHz，在标签和读取器之间允许高达50英尺的距离，而微波频率(通常2.45GHz)允许高达100英尺的距离，并用于高速公路收费和机动车识别。高频(HF)正常工作在13.56MHz范围内，并且用在通行卡和交通卡中；也用在制药产业。
RFID标签制作制造系统涉及电子电路的铅基焊料的问题。
IC管芯键合(die bonding)或将芯片组装到基板上的方法已经开发且优化了几十年，并且已经被公知为传统管芯键合技术。早期管芯键合是用于管芯焊盘和天线间互连的引线键合(见图1)。该技术让路于倒装芯片键合(见图2)。自从IBM多年前引进它们的C4倒装芯片技术后，使用共晶焊料作为凸点(bump)材料是公知技术。通过焊球置放或印刷到焊盘的焊膏，将铅共晶焊料施加到芯片上。通过使用回流工艺，将焊料熔融并形成球，或“凸点”。倒装芯片是广泛用于例如IC芯片的半导体器件的安装类型，其不需要任何引线键合。替之以，最后的晶片工艺步骤将焊珠沉积到芯片焊盘上。在将晶片切割成个体管芯后，接着“倒装芯片”倒置安装在封装内或封装上，并且焊料被回流。然后倒装芯片将经历底部填充工艺，这会覆盖管芯的侧面，类似于密封工艺。术语倒装芯片源于管芯的倒置(即，倒装)安装(见图3)。这使芯片焊盘以及它们的焊珠或凸点面朝下留在封装上，而在管芯的背侧面朝上。这种安装也被公知为可控塌陷芯片连接，或“C4”。
存在用于倒装芯片键合的几种材料和方法：冷压缩、热压缩、铅共晶焊接、金共晶焊接、热/超声以及胶粘技术，ACP(各向异性导电胶)或ACF(各向异性导电膜)。这些方法具有一共同点，即，需要直压和利用直热。本发明消除了这些要求。
具有在制造RFID标签中使用的直接和间接倒装芯片组装方法。在直接组装中，通过倒装芯片技术，芯片的凸点被直接定位并放置在天线连接上。由于该技术需要较少的工艺步骤，且消耗较少的材料，所以关键性优点是较低的封装成本。然而，即使大天线节距，高吞吐率也还是需要可忽略的索引时间(indexing timing)。所以，利用传统的倒装芯片键合方法，该技术不是没有其挑战，其将是天线网(antennaweb)的键合区域越大越发是可管理的。然而，较大键合区域的折衷是芯片传输的较长行程时间。键合区域的较好平衡的尺寸将产生成功的机械加工理念。
作为一种替换方案，多个制造商采用间接RFID芯片组装。作为第一工艺步骤，间接组装引入倒装芯片内插器。在后续步骤中，以非常高吞吐量和低成本的所有权，将内插器安装在天线上，这能够通过压接(crimping)完成。间接组装是有利的，尤其对于先前没有关于裸芯片工艺处理的经验并且不想投资集聚必要的技术的制造商来说。本发明不需要使用内插器。它是更简单的技术。
例如，无铅技术中，在现今世界备受喜爱的倒装芯片安装的胶粘形式是胶粘倒装芯片键合。根据需求，存在几种形式的该技术。已经报告了这样一种倒装芯片的形式，其中使用不导电胶粘膜将钉头凸点(stud-bumped)IC直接键合到细线电路板。由于该胶粘膜不象在导电粘合剂的情况下那样包含导电微粒，所以能够用于较小焊盘节距。该膜也作为密封剂或底部填充材料，用于热-机械管理。
胶粘倒装芯片安装的其他形式利用以膜(ACF)或胶粘剂(ACA)形式的各向异性导电材料，作为电和机械接合剂。各向异性导电膜看似纸一样，并且由热固性粘合剂、导电微粒和隔离(release)膜构成。图4是各向异性导电膜倒装芯片技术的示意图。各向异性导电粘合剂看似胶一样，并且由热固性粘合剂和导电微粒构成。注意到胶粘倒装芯片安装技术的几个优点：通常，管芯的焊盘节距可能比利用焊接倒装芯片的细。清理步骤不如利用基于焊接的系统那样严格，它消除了例如利用焊料涂布互连焊盘的工艺步骤且消除了铅的使用。凸点工艺可以利用钉头凸点而简化，这是利用与到IC焊盘的引线键合相同的工艺和设备来形成凸点。
倒装芯片键合的其他实例是其中使用热压和超声能量在IC焊盘上形成金球焊键合；引线在球的顶部处被切割且被拉平，产生适合于到基板的ACF键合的金凸点。超声键合见图5。本发明可与所有这些技术竞争，这是因为它们的电互连工艺不仅需要凸点设计、直接的压力和热，而是如一些倒装芯片键合的情况下，不需要用于热-机械的底部填充材料和湿汽密封。
基于该技术，装备厂商获得高级的管芯键合机器，该机器能够进行高速度倒装芯片组装。由于构想中的对RFID标签的巨大需求，一对替换的方法(例如，射流自组装(Fluidic Self Assembly)和震动组装(Vibratory Assembly)，在本上下文中被称为“想象方法”)看似提供该挑战的解决方案。传统和高级的管芯键合装备的巨大优点是具有低投资风险的成熟技术和高产量操作。
在电子产业中利用无铅焊料替换铅锡共晶焊料的世界范围内的运动在当前已经达到新的提升后的门槛。NEMI无铅组装项目在1999年启动，以协助北美公司在2001年前开发出无铅产品。现在正在开发无铅焊料替代品。由于多种形式的铅的毒性，电子产业乐意地从事于涉及产品回收和恰当的废旧处理的环境问题。欧洲中的立法提出对大多数消费电子产品中的铅的禁令。在亚洲，诸如Hitachi、NEC、Panasonic/Matshusita、Sony和Toshiba的一些主要的日本OEM正在开发用于电子产品的循环利用工艺，并给出多种承诺消除他们产品中的铅。在1990年代早期，在美国用来禁绝电子产品中的铅的无铅焊接活动已经处于低点。然而，在美国没有铅基焊料的电子产品组装的真实前景已经呈现。不存在一对一的代替铅的直接替代品，而且找到铅的替代品不是简单的任务。英国国际锡研究机构(ITRI)已经表明，最可能的替代品将是一些Sn(锡)、Cu(铜)和/或Ag(银)的组合。熔融温度＜183℃的焊料已经在消费类和电信方面被接受，而且在要求高的机动车应用中也要求该温度(183℃)。用于通用目的的焊接的主要合金是SnAgCu，具有217℃熔融点。然而，这样高的温度可能损坏管芯芯片。
发明内容
在此提供一种射频识别设备(RFID)，该RFID包括：(a)不导电的第一基板；(b)集成电路设备，安装到第一基板且具有至少一个导电端子；(c)图案化的导电涂层，施加到第一基板且与至少一个导电端子接触；以及，(d)导电桥接涂层，用于将集成电路的至少一个导电端子电连接到图案化的涂层，该导电桥接涂层包括聚合物基质和导电微粒填料，该聚合物基质能够经经受至少2％弹性形变且在导电桥接涂层的导电特性中没有显著变化。
作为本RFID发明的重要部分，在此提供一种对大多数基板具有高粘附性的耐潮湿混合组合物导电涂层，以及在所述天线和管芯芯片接触端子上方和之间的桥接接合，其中能够以简化的工艺将该导电涂层应用于大或小的天线设计。可以利用混合在基质中的导电粘性填料的量和类型以及特定调配工艺应用溶剂系统，来控制涂层的导电性。桥接涂层具有相同的基本导电塑料填料组分，但优选地包含较高的导电填料水平以及较高的粘度。
管芯芯片/不导电基板配置能够由在板上具有光蚀刻切割(或印刷)的天线的印刷电路板来制成所期望的配置，之后可以直接施加桥接IC管芯芯片元件和较大支持天线间的间隙的导电涂层，由此而成为无铅电接触。RFID管芯芯片能够被配置有：具有面朝上、被键合到支持基板的端子焊盘的接触焊盘，和桥接键合的导体，以及在相同几何平面中的天线。应用到且在管芯芯片端子接触的边缘上的桥接弹性体导电涂层键合到天线，克服线性膨胀系数不匹配的危险。用于制造本发明的RFID设备的工艺(单一平面直接“桥接”互连键合-SPDBIB)不需要对管芯芯片任何的导致压力的直接热暴露或当前工艺的与要求相关的键合压力下降。由于不存在芯片键合凸点，该RFID设备是相对的平面配置。由于面朝上设计，故不存在接触面空区。本发明的有用特征包括键合材料组合物的方法，制造方法和具有存在于单一平面中的导电涂层天线的系统的RFID设备设计。
根据本发明的一个方面，涉及一种射频识别设备，包括：
a)不导电的第一基板；
b)集成电路设备，该集成电路设备具有外边缘且被安装到所述第一基板的上表面，且该集成电路设备在所述集成电路设备的上表面具有至少一个导电端子；
c)图案化的导电涂层，施加到所述第一基板的上表面上；以及
d)导电桥接涂层，用于将所述集成电路的上表面上的至少一个导电端子电连接到所述图案化的导电涂层，所述导电桥接涂层包括聚合物基质和导电微粒填料，所述聚合物基质能够经受至少2％弹性形变而在所述导电桥接涂层的导电特性中没有显著变化，其中，所述导电桥接涂层延展到所述集成电路设备的外边缘上。
根据本发明的另外一个方面，涉及一种制造射频识别设备的方法，该方法包括下列步骤：
a)提供不导电的载体基板；
b)将第一图案化的导电涂层施加到所述载体基板的第一表面；
c)将集成电路芯片贴附到所述载体基板的第一表面；
d)将流体的第二导电涂层制剂施加到所述载体基板和集成电路芯片，以形成在所述集成电路芯片和所述第一图案化的导电涂层间的桥接电连接，其中，所述流体的第二导电涂层制剂包括聚合物基质、溶剂和分散在所述聚合物基质中的导电微粒填料，所述聚合物基质能够经受至少2％弹性形变而在固化或干燥时在所述第二导电涂层的导电特性中没有显著变化；以及
e)固化或干燥所述第二导电涂层制剂。
附图说明
以下参考附图描述多种实施例，其中：
图1示出现有技术的引线键合管芯芯片互连；
图2示出现有技术的倒装芯片铅焊料管芯芯片互连；
图3示出现有技术的倒装芯片键合；
图4示出现有技术的各向异性导电膜倒装芯片技术；
图5示出现有技术的超声工艺；
图6是安装到载体基板的计算机芯片的透视图；
图7是示出施加到计算机芯片和载体基板的本发明的导电涂层的一部分芯片和基板的侧视图；
图8是示出具有印刷的导电天线的RFID设备的平面图；
图9是示出在上和下图案化的导电涂层之间采用通孔(via)的RFID设备的替换实施例的剖视图；
图10示出单一平面直接桥接互连键合(SPDBIB)的工艺；以及
图11示出单一平面直接桥接互连键合(SPDBIB)的替换工艺。
具体实施方式
本发明的RFID设备是包括计算机芯片的应答机或标签，该计算机芯片包含具有半导体存储能力的集成电路，其中可存储数字信息。计算机芯片可包括，例如，电可擦写可编程只读存储器(EEPROM)或类似的电存储设备。计算机芯片安装在载体基板上，并且可以是依靠来自读取器设备提供的电磁场的功率的有源设备，或者它能够连接到其自身的电源，例如电池。载体基板可为刚性的或柔性的，并且包括安装于其的天线，该天线由诸如铜或铝的金属或沉积的导电弹性体组分的光刻电路制造而成。本发明的RFID设备被设计成管芯芯片的正面向上，并且由特定的弹性聚合物导电组分构成的互连“桥接”端接管芯焊盘端接到天线上。本发明的RFID设备的一面的特性允许以简单的方式来制造该RFID设备。该新工艺不需要直接加热和加压或底部填充。
除非另外说明，术语“绝缘”、“导电”、“电阻”、“电容”和它们在此所使用的相关形式表示所描述的材料的电特性。
电阻表示材料反抗电流在材料中沿着电流路径流动，并且以欧姆为单位来测量。电阻随电流路径长度以及材料的电阻率或电阻系数成比例地增加，而其随着电流可用横截面积反向变化。电阻率是材料的特性，并且可被认为是(电阻/长度)/面积的测量结果。根据下列公式
(I)可确定电阻：
R＝ρL/A    (I)
其中
R＝以欧姆为单位的电阻
ρ＝以欧姆-英寸为单位的电阻率
L＝以英寸为单位的长度
A＝以平方英寸为单位的面积。
如欧姆定律所规定的那样，通过电路的电流与施加的电压成比例变化，而与电阻反向变化，：
I＝V/R    (II)
其中
I＝以安培为单位的电流
V＝以伏特为单位的电压
R＝以欧姆为单位的电阻。
通常，平面导电片的横跨该片的平面，即从一个边缘到相对边缘的电阻以欧姆每方为单位测量。对于任意给定厚度的导电片，不论方的大小是多少，跨该方的电阻值保持一致。在电流路径是从一个表面到另一表面，即在垂直于该片的平面的方向上的应用中，以欧姆为单位测量电阻。
术语“电容”是对于给定的电势存储(或分离)的电荷量。电容通常被定义为位于由物体的总电荷除以该物体的电势，
其中：
C是以法拉(F)为单位的电容
Q是以库伦(C)为单位的电荷
V是以伏特(V)为单位的电势
F是以库伦为单位的与电荷Q有关的电通量
因此：
C＝Q/V
或根据高斯定律，电容能够被表达为电通量/伏特
C＝F/V
在此所使用的术语“弹性体”和“弹性材料的”表示能够经受至少2％弹性形变，优选至少5％形变以及更优选至少10％弹性形变的材料，即不会定形和在导电涂层的导电特性上没有显著变化。适合于此所描述的目的的弹性体材料包括诸如增塑聚氯乙烯(PVC)、聚对苯二甲酸乙二醇酯(PET，polyethylene terephthalate)、热塑性或热固性聚氨酯、硅酮以及天然和合成橡胶的聚合材料。
本发明的可选特征是使用生胶(green rubber)。术语“生胶”表示处于某一形式的未被完全硫化或固化的热固性弹性聚合物胶料或化合物。胶料的生坯强度(green strength)是处于未固化或仅部分固化的生坯状态(green state)的胶料对形变的抵抗。处于生状态下，聚合物能够被注模、压延和另外形成为各种形状。生胶能够以片的形式来提供，这些片能够利用砑光(calendering)、辊压、夹持、层压和压花(embossing)等等在室温下处理，并且能够被涂覆并成形为各种结构。可以通过将生胶加热到分子结构经受交联的温度，而将其硫化。硫化增加胶料的弹性但使橡胶变得塑性较小。通常，生胶能够在从约280°F到约400°F下固化约10分钟到60分钟。适合于本发明中的使用的生混炼胶(green compounded rubber)是基于乙烯-丙烯-二烯单体(即，EPDM)配方的，并且可以以片的形式从多个供应商商业获得，例如Sebring，Ohio的Salem Republic Rubber Company。Salem RepublicRubber Company的片化合物，SRR EPDM#365-0，由于其高门尼粘度是优选的。由具有较低粘度的片化合物制成的冷或热形成的结构在硫化期间会失去其形状。由于处于生坯状态下橡胶的粘性，诸如涂布的隔离纸、聚乙烯膜、或其他这样的不粘片的具有不粘表面的隔离片通常与生胶同绕，用作隔离界面，从而防止橡胶粘到它本身。
现在参考图6，介质载体基板20由任何类型的合适的绝缘材料的片制成，诸如纸、聚合物膜(例如，聚烯烃、聚氨酯、聚酯(MYLAR)、聚对苯二甲酸乙二醇酯(PET)等等)、陶瓷、玻璃等等。载体基板20可以是刚性的，但优选为柔性的或柔韧的。在本发明的实施例中，载体基板由例如PET的柔韧的材料制造成的。
芯片10包括优选具有半导体存储器的集成电路(未示出)，在该半导体存储器中能够存储数字信息。芯片10上的接触焊盘11是用于在芯片10的集成电路和图案化的金属或导电聚合物涂层30a之间提供电接触的导电端子。例如，接触焊盘11可以为诸如铜、铝、银、金等等的金属膜。接触焊盘11可以是凸起的或不凸起的(即，裸的)，并且或向上或向下放置。
芯片10利用胶粘键合或任何其他合适的方法而贴附到载体基板20上。
通常芯片10可具有200到1000微米的长度，200到500微米的宽度，优选550到650微米的长度以及350到450微米的宽度。导电端子可具有40到100微米的长度和/或宽度，优选60到70微米。给定这些范围仅是为了说明性的目的，而不对本发明的范围构成限制。只要适当，就可以使用这些范围之外的尺寸。
现在参考图7和图8，示出载体基板和芯片10的一部分，说明施加到载体基板20、芯片10和导电端子11的导电桥接(单一平面直接桥接互连键合-SPDBIB)涂层30的线。利用诸如浇铸、辊、喷涂、丝网印刷、转轮凹版印刷、刀涂布、帘式涂布、胶印、喷射、旋转丝网印刷、喷墨、平板印刷等等的任何合适的方法，可以将桥接涂层30作为流体施加，接着干燥或固化导电涂层。
桥接涂层30对被施加的表面具有极好的粘附。干燥或固化的SPDBIB桥接涂层30具有充分弹性，以适应芯片10和载体基板20之间的不同的热膨胀系数。从而避免由环境温度变化导致的桥接涂层30中的断裂。涂层30的厚度范围通常在从约0.0001英寸到0.03英寸(0.1密耳到约30密耳)。在本发明的优选实施例中，作为干燥的组合物、或固化的热固性组合物，桥接涂层30类似于图案化的导电涂层30a，除了金属填充水平和粘度较高以外。较高的粘度适合Asymtech DJ 9000喷射涂布分配机器。该喷射应用产生较厚的保形涂布截面。较高的粘度也适合丝网印刷应用。桥接涂层30制剂能够利用碳/石墨填料来代替金属粉末而进行修改，以起电路中的低电阻导体(0.001到约10欧姆每方)或电阻元件(300欧姆到100千欧姆每方)的作用。电阻膜可以用作薄膜电阻器，用于较广的应用。上面给定的范围是出于说明性的目的。只要适当，也可使用这些范围之外的值。
导电涂层包括分散在弹性体树脂溶液中并被施加到诸如PET、Mylar、纸等的柔性或柔韧基质材料然后干燥的导电填料构成。有导电纤维或无导线纤维的导电的良好分开的微粒的组合允许导电填料预先混合到树脂内。导电填料可包括具有或不具有有效量的导电纤维的有效量的导电粉末。导电粉末(包括纳米粉末)的微粒大小通常范围在约(纳米粉末20到210nm)和颜料粉末0.01到约25微米的直径，微粒的形状不规则，但通常具有片或圆形结构。导电纤维可以为金属纤维，或优选为石墨，并且通常长度范围从约0.01到约0.5英寸。导电粉末的量范围通常从总组分重量的约15％到约80％。导电纤维通常范围从总组分重量的约0.1％到约10％。导电填料是包括从下述材料选择的材料的微粒：银、铜、金、锌、铝、镍、不锈钢、锡、涂布银的铜、涂布银的玻璃、涂布银的铝、涂布银的塑料、石墨粉末、石墨纤维、银或任意上述金属的纳米纤维、银或任意上述金属的纳米粉末、碳纤维、碳纳米纤维、银纳米纤维、涂布银的纳米纤维或涂布有任意上述金属的纳米管。纳米纤维的外径是从1.1到200纳米，长度是从0.1到500μm。
使用银微粒填料，组分可拥有如0.001欧姆每方那样低的电阻。使用石墨、碳、银、金或任意上述列出的其他金属的纳米纤维，可以达到0.0001到0.01欧姆每方的电阻值。
用于涂层30的基质材料的聚合物树脂可包括弹性体的PVC或其他乙烯基聚合物、聚氨酯热固性树脂、聚氨酯热塑性树脂、硅酮和EPDM橡胶树脂体系。
在本发明的涂层制剂的制备中有用的溶剂可以包括，但不限于，四氢呋喃(THF)、甲基乙基酮(MEK)、二乙基酮(diethyl ketone)、丙酮、乙酸丁酯、异丙醇、石脑油、甲苯、二甲苯、水或无有害空气污染物(non-HAP)流体。
通过物理组合基质树脂、导电填料微粒、溶剂，以及可选的其他添加剂，诸如增塑剂、用于粘度控制的增稠剂、例如硅烷的粘附促进剂、抗氧化剂、氧化剂、去沫剂或其它功能性添加剂，生成涂层材料制剂。合适材料的实例包括：增塑剂-邻苯二甲酸二辛酯(dioctylphthallate，DOP)；增稠剂-无定形热解硅石(amorphous fumedsilica)(Cab-O-Sil)或结晶硅土(膨润土)；粘附促进剂-乙烯基三乙氧基硅烷(vinyl trethoxysilane)；抗氧化剂-水杨醛(salicylaldehye)；氧化剂-二异丙苯过氧化物(dicumylperoxide)；以及去沫剂-硅酮种类。
下列表示出各种优选的制剂。表1示出基本制剂。
表1
基本制剂
  组分   量(重量份)
  聚氨酯树脂(28.9％固体在THF中)   1.7-7份
  银颜料   4.5-15份
  MEK或无-HAP溶剂   20-70份
表2示出导电涂料制剂，该制剂尤其适合利用喷枪将导电膜喷涂到基板上的应用。对0.0001英寸到约0.003英寸厚度的涂层该制剂能够达到0.01欧姆/每方的值。在应用该制剂后，能够在烤炉内70C°温度下对该制剂进行急骤干燥或外部干燥20分钟。室温下干燥较长的时间也是可能的。
表2
(导电涂料制剂)
 组分   量(重量份)
 树脂(热固性聚氨酯)   10-30份
 还原剂(水杨醛(Salicylaldehyde))   1.0-0.1份
 硅烷(Hydrosil)   1.5-0.1份
 Potter银涂布的铜片   40-120份
 MEK或特定的无-HAP溶剂   50份
表3示出生胶制剂。当被施加到生胶基板上，且在固化温度(例如，280°F-350°F)干燥或固化时，涂层和基板通过分子的交联变得连接在一起，以形成集成的无缝的单一结构。
表3
生胶制剂
  组分   量(重量份)
  树脂(生胶-调配的EPDM化合物)   1.7-7份
  银片粉末   4.5-15份
  甲苯或己烷   20-70份
表4示出采用石墨和碳纤维的生胶制剂。
表4
(生胶石墨实例制剂)
  组分   量(重量份)
  生胶树脂(生胶-调配的EPDM化合物)   5-20份
  石墨纤维(1/64到2英寸长)   10-0.05份
  碳粉末   0.1-0.0005份
  石墨粉末(或金属)   2.5-9份
  甲苯或己烷   20-70份
表5示出采用硅酮橡胶基质的导电涂层制剂。
表5
  组分   量(重量份)
  树脂(硅酮橡胶)   1.7-7份
  银片粉末   4.5-15份
  MEK或无-HAP溶剂   10-70份
表6示出用作电路中的电阻器的涂层。可以通过使用或多或少的石墨或碳纤维，来控制电阻。该涂层的电阻对于0.0001英寸到约0.003英寸的厚度，通常范围从约0.001欧姆/每方到5欧姆/每方。
表6
(电阻器制剂)
组分                   量(重量份)
硅酮橡胶树脂           5.0-20份
石墨纤维(1/64到2英寸长)10-0.05份
碳粉末                 0.1-0.0005份
石墨粉末(或金属)       2.5-95份
MEK或无-HAP溶剂        10-70份
通过组合60份石墨颜料(Asbury石墨A60)、0.4份碳黑(Shawingigan Black A)，以形成填料，并且将填料分散进入100份具有充足溶剂的增塑的PVC树脂，以提供期望的粘度，来完成替换制剂。可以通过喷涂施加该组分，从而在基板上形成具有从约100到1000欧姆/每方的薄片电阻的膜。银片能够与填料结合，以提供较低的薄膜电阻。
表7示出基于弹性体的热固性树脂体系的制剂，该制剂适合利用丝网印花到载体基板的应用。替换地，能够添加MEK或无-HAP溶剂，以降低喷涂的粘度等等。
表7
组分                               量(重量份)
芬香族聚氨酯丙烯酸树脂             6-18份
三羟甲基丙烷三甲基丙烯酸酯         1-3份
聚酯乙酸酯                         2-6份
丙烯酸化的聚酯低聚物               1-3份
环己烷二丙烯酸酯                   2-6份
过氧化物(过氧化苯甲酰或过氧化二    0.7-0.02份
异丙苯)
环烷酸钴(固体)      0.01-0.3份
银片微粒            50-90份
表8示出应用纳米纤维的基本导电涂层制剂。
表8
  组分   量(重量份)
  聚氨酯(具有THF的28.9％固体)   1.7-80份
  纳米纤维-石墨、碳、银<sup>*</sup>、金、镍、不锈钢、锡、铜   1-50份
  MEK或特定的无-HAP溶剂   20-70份
*涂布银的石墨或碳纤维或纳米纤维管。
表9示出在热塑性聚氨酯树脂中采用纳米纤维且具有添加剂的导电涂层制剂，该制剂适合于丝网印花应用。
表9
  组分   量(重量份)
  树脂(热固性塑料聚氨酯)   10-30份
  还原剂(水杨醛)   1.0-0.1份
  硅烷(Hydrosil)   1.5-0.1份
  纳米纤维-石墨、碳、银<sup>*</sup>、金、镍、不锈钢、锡、铜   1-60份
  MEK或特定的无-HAP溶剂   50份
*涂布银的石墨或碳纤维或纳米纤维管。
表10示出基于生胶基质和纳米纤维的涂层制剂。
表10
  组分   量(重量份)
  树脂(生胶-EPDM)   1.7-7份
  纳米纤维-石墨、碳、银<sup>*</sup>、金、镍、不锈钢、锡、铜   1-50份
  甲苯或己烷   20-70份
*涂布银的石墨或碳纤维或纳米纤维管。
表11示出包括硅酮橡胶和纳米纤维的制剂。
表11
  组分   量(重量份)
  硅酮橡胶   1.7-7份
  纳米纤维-石墨、碳、银*、金、镍、不锈钢、锡、铜   1-50份
  甲苯   20-70份
*涂布银的石墨或碳纤维或纳米纤维管。
采用纳米纤维的导电涂层也能够包括增塑的PVC。
表12示出采用弹性体的热固性聚氨酯树脂的制剂，其适合于丝网印花应用到基板。
表12
  组分   量(重量份)
  芬香族聚氨酯丙烯酸树脂   6-18份
  三羟甲基丙烷三甲基丙烯酸酯   1-3份
  聚酯乙酸酯   2-6份
  丙烯酸聚化的酯低聚物   1-3份
  环己烷二丙烯酸酯   2-6份
  组分   量(重量份)
  过氧化物(过氧化苯甲酰或过氧化二异丙苯)   0.7-0.02份
  环烷酸钴(固体)   0.01-0.3份
  纳米纤维-石墨、碳、银<sup>*</sup>、金、镍、不锈钢、锡、铜   1-50份
*涂布银的石墨或碳纤维或纳米纤维管。
所有上述涂层能够具有纳米微粒替代金属纳米纤维或涂布了金属的纳米纤维或纳米管。而且，具有纳米微粒的、标准金属微粒填料和纤维、纳米纤维或者涂布了金属的纳米纤维或纳米管的混合物也在本发明的范围内。
涂层制剂可以是浆、流体或油墨，其被施加到基板，接着被干燥(例如，利用溶剂的蒸发)或被固化(利用提高的温度、UV、辐射或其它固化的方法)以形成集成的涂层。
现在参考图8，图案化的导电涂层30a被施加在载体基板20之上。桥接涂层30提供图案化的导电涂层30a和集成电路芯片10的端子11之间的电连接。在本发明的优选实施例中，图案化的涂层30a类似于桥接涂层30，但是其粘度和颜料填料水平可以相同或不同。如从图7和8中所看见的，图案化的涂层30a包括：连接部分31，由桥接涂层30电连接到芯片10；和天线部分32，在与芯片10相同的平面水平处。在替换实施例中，图案化的涂层30a可包括金属膜。
涂层30a能够在组分、几何配置和位置上变化，以提供电导、阻抗、电阻、电容、电感、共振、介电常数、磁导率和介电值的期望值。
可以替换地应用替换的配置布置。例如，可制造交迭，其中不导电涂层覆盖导电涂层的第一线的一部分。接着可以施加导电涂层的第二线，以在绝缘部分处交迭第一线。此外，由绝缘层隔离的导电涂层的层在电路中能够执行电容器的功能。而且，能够从填充有导电涂层材料的层之间的单个或多个通孔，制造导电通路(via)。
现在参考图9，示出了RFID设备的实施例40，其中将第一图案化的导电涂层45施加到包含开口42a的打孔的第一不导电载体基板42(例如，PET)的一侧。第一图案化的导电涂层45的一部分占据开口42a，以便提供导电通路43。将上面的第二图案化的导电涂层41施加到第二不导电基板42的另一侧，使得第二图案化的导电涂层的一部分接触通孔，以便提供到较低第一图案化的导电涂层45的电连接。将第二不导电基板44(例如，纸)施加到第一载体基板42的一侧，以便形成不导电基底层。导电层41和45能够被制造以便向电路提供电容器功能性。
现在参考图10，示出了对于用于UHF 850-960MHz(嵌入式或完成的封装)的单一平面直接桥接互连键合(SPDBIB)的工艺流程图。该工艺包括12个步骤，直至RFID设备的最终用户。
步骤1是将纸或PET基板回卷馈送到例如转轮凹版印刷的一些形式的印刷中。在本发明的实施例中，涂层30a用于形成天线。在该步骤中，替换地可提供连续蚀刻金属膜图案。
步骤2是胶辊印刷(roto-printing)操作。
步骤3(在制品(Work in progress)-WIP)是将材料重绕且传送到步骤4，其中天线片被馈送到步骤5。
步骤5是印刷天线基板的定位馈送。
该步骤继之以步骤6，其中干法施加(dry application)的粘合剂被施加到管芯芯片的背面，并且它被定位且被键合到天线基板。步骤6a是为步骤6提供管芯芯片(晶片)。
在该胶粘操作后，工艺继续前进到步骤7：SPDBIB涂层30的喷射应用用于形成管芯焊盘和天线之间的互连。
在步骤8中施加保形保护涂料。利用该保形涂料涂布完整的标签或嵌入物，从而保护电元件以免受潮同时增加机械稳定性。在本领域技术中，保形涂料是公知的，且可由热塑性或热固性树脂，例如聚氨酯、环氧树脂、硅酮等等组成。
步骤9使用传统的分体和打孔来提供工件的切割形式以用于下游封装。
步骤10是质量控制操作，其中嵌入式的或完成的制品被测试电连通性和传输。
操作步骤11为能使人阅读的进一步印刷提供标签(将空白纸施加到非天线侧)。
步骤12表示用户的设备使用。
现在参考图11，示出SPDBIB工艺流程图，用于HF 13.56MHz(嵌入物或完成的封装)，其包括两侧使用的基板。类似于图10中示出的工艺，流体导电涂层制剂用来形成天线，也形成利用通孔或通路到在具有涂层30a的天线之下印刷的图案化的带的连接。当执行图11的步骤9时，不仅提供连接天线的管芯焊盘，而且进行到导电通孔的连接。由于将导电通孔或通路连接到所述图案条(pattern bar)，当给RFID供能时，在其间具有PET电介质的金属涂层(天线和导电的图案条)，产生用于给设备以能量的电容。
为了描述图11的工艺，示出15个步骤，直至RFID设备的最终用户。
步骤1是将纸或PET基板回卷馈送到步骤2的打孔操作中。
打孔的PET从步骤2馈送到例如转轮凹版印刷的一些形式的印刷，其中PET基板的两侧均可被印刷。
步骤3是胶辊印刷(roto-printing)操作，如上所述可能需要两个操作。
当将第二涂层(30a)(步骤4)应用于印刷图案条时，导电涂料流过通孔以形成导电通孔。
步骤5(在制品-WIP)是将材料重绕且传送到步骤6，其中天线片被馈送到步骤5。
步骤6是印刷天线基板的定位馈送。
该步骤继之以步骤7，其中干法施加的粘合剂被施加到管芯芯片的背面，在步骤8中它被定位且被键合到天线基板。
在该粘合操作后，工艺继续前进到步骤9，用于SPDBIB涂层30的喷射应用以形成管芯焊盘和天线之间的互连。
在步骤10中施加保形保护涂料。利用该保形涂料涂布完整的标签或嵌入物，从而保护电元件以免受潮同时增加机械稳定性。
步骤11使用传统的分体和打孔，以提供工件的切割形式以用于下游封装。
步骤12是质量控制操作，其中嵌入物或完成的制品被测试电连通性和传输。
可选步骤14为使人能够阅读的进一步印刷提供标签(将空白纸施加到非天线侧)。步骤12表示用户的设备使用。
尽管上述描述包含许多细节，这些细节不应该被理解为对本发明的限制，而是仅作为其优选实施例的例证。本领域技术人员将想象到在通过所附权利要求所定义的本发明的范围和精神之内的许多其他实施例。

Claims (34)

1.一种射频识别设备，包括：
a)不导电的第一基板；
b)集成电路设备，该集成电路设备具有外边缘且被安装到所述第一基板的上表面，且该集成电路设备在所述集成电路设备的上表面具有至少一个导电端子；
c)图案化的导电涂层，施加到所述第一基板的上表面上；以及
d)导电桥接涂层，用于将所述集成电路的上表面上的至少一个导电端子电连接到所述图案化的导电涂层，所述导电桥接涂层包括聚合物基质和导电微粒填料，所述聚合物基质能够经受至少2％弹性形变而在所述导电桥接涂层的导电特性中没有显著变化，其中，所述导电桥接涂层延展到所述集成电路设备的外边缘上。
2.根据权利要求1所述的设备，其中，所述聚合物基质能够经受至少10％弹性形变而在所述导电桥接涂层的导电特性中没有显著变化。
3.根据权利要求1所述的设备，其中，所述图案化的导电涂层被形成为能够接收和传导电磁信号的天线。
4.根据权利要求3所述的设备，其中，所述集成电路设备的导电端子和所述第一基板的表面分别处于空间上隔开的平行平面上。
5.根据权利要求1所述的设备，其中，所述第一基板是柔韧的。
6.根据权利要求1所述的设备，其中，所述第一基板由从纸、聚合物膜、陶瓷和玻璃中选择的材料来制造。
7.根据权利要求6所述的设备，其中，所述聚合物膜包括聚对苯二甲酸乙二醇酯和/或聚氨酯。
8.根据权利要求1所述的设备，其中，所述图案化的导电涂层包括金属膜。
9.根据权利要求1所述的设备，其中，所述图案化的导电涂层包括聚合物基质和导电微粒填料，所述聚合物基质能够经受至少2％弹性形变而在所述导电桥接涂层的导电特性中没有显著变化。
10.根据权利要求9所述的设备，其中，所述图案化的导电涂层由固化的生胶来制造。
11.根据权利要求10所述的设备，其中，所述第一基板是固化的生胶，且所述图案化的导电涂层和第一基板被集成地形成为单块。
12.根据权利要求1所述的设备，进一步包括其上施加有第二图案化的导电涂层的不导电的第二基板，所述第二基板包括含有导电涂层材料的至少一个通路，其与所述第二基板上的第二图案化的涂层和所述不导电的第一基板上的图案化的导电涂层两者电接合且物理接触。
13.根据权利要求1所述的设备，其中，所述导电微粒填料包括石墨、碳、银、金、镍、不锈钢、锡或铜的纳米纤维，或金属化的纳米管，涂布金属的石墨，或涂布金属的玻璃。
14.根据权利要求1所述的设备，其中，所述导电桥接涂层具有从0.0001英寸到0.03英寸的厚度范围和从0.001到10欧姆每方的片电阻范围。
15.一种制造射频识别设备的方法，该方法包括下列步骤：
a)提供不导电的载体基板；
b)将第一图案化的导电涂层施加到所述载体基板的第一表面；
c)将集成电路芯片贴附到所述载体基板的第一表面；
d)将流体的第二导电涂层制剂施加到所述载体基板和集成电路芯片，以形成在所述集成电路芯片和所述第一图案化的导电涂层间的桥接电连接，其中，所述流体的第二导电涂层制剂包括聚合物基质、溶剂和分散在所述聚合物基质中的导电微粒填料，所述聚合物基质能够经受至少2％弹性形变而在固化或干燥时在所述第二导电涂层的导电特性中没有显著变化；以及
e)固化或干燥所述第二导电涂层制剂。
16.根据权利要求15所述的方法，其中，所述聚合物基质能够经受至少10％弹性形变而在所述第二导电涂层的导电特性中没有显著变化。
17.根据权利要求15所述的方法，其中，所述不导电载体基板由纸、聚合物膜、陶瓷或玻璃制造。
18.根据权利要求15所述的方法，其中，所述不导电载体基板由聚对苯二甲酸乙二醇酯和/或聚氨酯来制造。
19.根据权利要求15所述的方法，其中，所述贴附步骤c)通过胶粘接合来完成。
20.根据权利要求15所述的方法，其中，所述施加流体的第二导电涂层的步骤d)由选自以下的印刷操作来执行：浇铸、辊、喷涂、丝网印刷、转轮凹版印刷、刀涂布、帘式涂布、胶印、喷射、喷墨、平板印刷。
21.根据权利要求15所述的方法，其中，所述聚合物基质包括选自增塑的聚氯乙烯、聚氨酯、硅酮以及天然和合成橡胶的材料。
22.根据权利要求15所述的方法，其中，所述流体的第二导电涂层制剂包括选自下列的添加剂：增塑剂、增稠剂、还原剂、粘附促进剂、抗氧化剂、氧化剂和去沫剂。
23.根据权利要求15所述的方法，其中，所述固化或干燥步骤e)包括通过从其去除溶剂和/或通过化学交联聚合物基质材料，来干燥所述流体的第二导电涂层制剂。
24.根据权利要求15所述的方法，其中，所述图案化的第一导电涂层被施加为流体的第一导电涂层制剂，该第一导电涂层制剂包括聚合物基质材料、溶剂和分散在所述基质中的导电微粒填料，所述聚合物基质材料能够经受至少2％弹性形变而在固化时在所述第二导电涂层的导电特性中没有显著变化。
25.根据权利要求24所述的方法，其中，所述不导电载体基板由生胶制造，且聚合物基质材料包括生胶，以及步骤(e)进一步包括一起热固化所述载体基板和所述聚合物基质材料，以便形成集成的单块结构。
26.根据权利要求24所述的方法，其中将第二图案化的导电涂层施加到所述不导电载体基板的与所述第一表面相反的第二表面上，其中，在所述不导电载体基板中进行穿孔，以便提供用于所述第一和第二图案化导电涂层间的电连接的通路。
27.根据权利要求26所述的方法，其中，所述第一和第二图案化的导电涂层由选自以下的印刷操作来施加：浇铸、辊、喷涂、丝网印刷、转轮凹版印刷、刀涂布、帘式涂布、胶印、喷射、喷墨、平板印刷。
28.根据权利要求27所述的方法，进一步包括将不导电基底层贴附到印刷的不导电载体基板。
29.根据权利要求15所述的方法，其中，所述第一图案化的导电涂层包括金属膜。
30.根据权利要求15所述的方法，其中，所述第一图案化的导电涂层被形成为能够接收和传导电磁信号的天线。
31.根据权利要求30所述的方法，其中，所述流体的第二导电涂层被施加到向上或向下放置的所述集成电路芯片的一个或多个突出的或不突出的端子，并且连接到所述天线。
32.根据权利要求15所述的方法，进一步包括将第二图案化的导电涂层施加到所述载体基板的相反的第二表面，所述载体基板包括用于电连接所述第一和第二图案化导电涂层的至少一个导电通路。
33.根据权利要求24所述的方法，进一步包括改变所述第一图案化的导电涂层的组分、位置和/或几何配置，以提供预定值的电导、阻抗、电阻、电容、电感、共振、介电常数、磁导率和介电值中的一个或多个。
34.根据权利要求15所述的方法，其中，所述第二导电涂层具有从0.0001英寸到0.03英寸的厚度范围和从0.001到10欧姆每方的片电阻范围。
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DE602006012184D1 (de) 2010-03-25
EP1900025B1 (en) 2010-02-10
US20070007661A1 (en) 2007-01-11
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ATE457526T1 (de) 2010-02-15

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