CN101183649A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101183649A
CN101183649A CNA2007101481579A CN200710148157A CN101183649A CN 101183649 A CN101183649 A CN 101183649A CN A2007101481579 A CNA2007101481579 A CN A2007101481579A CN 200710148157 A CN200710148157 A CN 200710148157A CN 101183649 A CN101183649 A CN 101183649A
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吴珑虎
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DB HiTek Co Ltd
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Abstract

本发明提供一种用于制造半导体器件的方法。在该方法中，在半导体衬底上顺序地形成栅极氧化层、栅极多晶硅层以及覆盖氧化层。在覆盖氧化层上形成光致抗蚀剂图案。使用光致抗蚀剂图案作为蚀刻掩模顺序地蚀刻覆盖氧化层、栅极多晶硅层以及栅极氧化层。然后使用光致抗蚀剂图案作为掩模将离子注入到半导体衬底内。进行热扩散工艺以形成源极/漏极区域。移除覆盖氧化层，且将离子注入栅极多晶硅层中。在将金属沉积在栅极多晶硅层上之后，就形成了硅化物。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
大多数互补金属氧化物半导体(CMOS)器件使用多晶硅形成多晶栅(poly gate)。当多晶栅由多晶硅形成时，必须或多或少地形成耗尽层。在器件的集成度不是很高的情况下，多晶栅可能会相对较大。因此，即使在产生耗尽层时，也可以忽略器件的电学特性的降低。
然而，近来随着半导体器件的集成技术的显著发展，栅极的尺寸逐步减小，因此栅极产生的耗尽层就具有相对较大的影响，该影响是降低半导体器件的性能的因素。上述问题成为对使用多晶硅的半导体器件的限制。
为了克服这种限制，已经尝试了多种技术，并且提出了一种作为基本解决方案的金属栅极。然而，金属栅极在制造工艺中可能会有困难，且形成双栅极需要相对较高的成本。
作为替代，提出一种形成全硅化栅极(例如，使用全硅化物或FUSI)的工艺作为向全金属栅极的过渡。金属硅化物通常被认为是类金属材料。
然而，FUSI栅极在工艺中也有困难，即，在金属沉积以及离子已注入多晶硅后进行热扩散工艺时，由于沉积的金属和多晶硅的热膨胀系数不同，可能会产生缺陷。
发明内容
本发明的实施例提供一种用于制造半导体器件的方法以及通过该方法制造的半导体器件，该方法解决了在FUSI栅极形成期间由于热膨胀的不同在FUSI栅极工艺中出现的困难。
在一个实施例中，用于制造半导体器件的方法包括以下步骤：在半导体衬底上顺序地形成栅极氧化层、栅极多晶硅层以及覆盖氧化层；在该覆盖氧化层上形成光致抗蚀剂图案；使用该光致抗蚀图案作为蚀刻掩模顺序地蚀刻该覆盖氧化层、该栅极多晶硅层以及该栅极氧化层；形成多个隔离物，且使用该光致抗蚀剂图案和所述隔离物作为离子注入掩模将第一离子注入半导体衬底中；在已注入了离子的半导体衬底上进行热扩散工艺，以形成源极/漏极区域；移除该覆盖氧化层并将离子注入该栅极多晶硅层；以及在该栅极多晶硅层上沉积金属，然后由该金属和该栅极多晶硅层形成金属硅化物。
在下面的附图和说明书中阐述一个或多个实施例的细节。通过说明书和附图以及权利要求书，其它特征将会变得明显。
附图说明
图1到图5是示出根据本发明实施例的用于制造半导体器件的方法的视图；
图6是示出根据本发明实施例的半导体器件的剖视图。
具体实施方式
现将参照附图，详细描述本发明的多个实施例。
图1到图5是示出根据本发明实施例的用于制造半导体器件的方法的视图。
首先，参照图1，在半导体衬底10上顺序形成栅极氧化层21、栅极多晶硅层31以及覆盖氧化层41。该覆盖氧化层41被用作虚拟电极(dummyelectrode)或硅化物阻挡掩模以将源极/漏极区域的硅化和该多晶硅层的硅化分开。当该覆盖氧化层41的厚度较厚时，该源极/漏极区域的硅化可以有效地与该多晶硅层的硅化分开。然而，当该覆盖氧化层41的厚度过厚时，就会增加工艺成本。
因此，有利地，该覆盖氧化层41的厚度是该栅极多晶硅层31的厚度的1到3倍。该栅极多晶硅层31的厚度可以是30-60nm，且该覆盖氧化层41的厚度可以是30-180nm。
下面，参照图2，将光致抗蚀剂(未示出)涂敷在该覆盖氧化层41上。使用例如步进曝光机(stepper)之类的曝光设备将来自光刻掩模的图案缩小投影到光致抗蚀剂上，且曝光该光致抗蚀剂并使其显影以形成光致抗蚀剂图案(未示出)。之后，顺序蚀刻该覆盖氧化层41、该栅极多晶硅层31以及该氧化层21，以形成覆盖氧化层图案40、栅极多晶硅图案30以及栅极氧化层图案20。
下面，参照图3，使用该覆盖氧化层图案40作为硬掩模通过公知方法注入离子，从而形成多个轻掺杂漏极(LDD)61。在该覆盖氧化层图案40、该栅极多晶硅图案30、该栅极氧化层图案20的侧面分别形成隔离物50，然后使用所述隔离物50和该覆盖氧化层40作为掩模，通过离子注入形成源极/漏极区域62。为形成源极/漏极区域62而注入的离子通常与用于LDD61的掺杂物是同一类型，但所述离子以比LDD61的掺杂物更多的量和更高的能量注入。
下面，参照图4，在金属沉积在半导体基底10的整个表面上之后，进行热处理以使该金属与源极/漏极端子的底层硅化物反应，并(在一个实施例中)形成包含类金属材料的全硅化(FUSI)源极/漏极F1。沉积的金属可以包括W、Ti、Co、和/或Ni，或主要由W、Ti、Co、和/或Ni组成，这些金属中的一些或全部还可以包含氮(N)。然而，如图4所示，不需要使源极/漏极注入物62的整个厚度都被硅化源极/漏极F1消耗。在热硅化反应之后，未反应的金属被移除以形成如图4所示的结构。
下面，参照图5，覆盖氧化层图案40和隔离物50的一部分被移除，从而暴露出栅极多晶硅图案30的最上表面，且将离子注入该栅极多晶硅图案30。这样的离子可以包括N型(例如，含有P-，As-和/或Sb)或P型(例如，含有B)离子。在一个实施例中，注入栅极多晶硅图案30的离子的类型(或离子本身)与注入源极/漏极端子62的离子相匹配。
下面，参照图6，在金属沉积在已注入离子的栅极多晶硅图案30上之后进行热处理，以通过栅极多晶硅的Si和金属之间的化学反应形成包括类金属材料的FUSI栅极F2。该金属独立于形成金属硅化物F1的金属，且可以包括W、Ti、Co和Ni或主要由W、Ti、Co和Ni组成。然而，与图4中所示的实施例不同，基本上该栅极多晶硅图案30的整个厚度都在硅化反应中被消耗，从而形成FUSI栅极F2。在热硅化反应之后，未反应的金属被移除以形成如图6所示的结构。
在用于制造根据实施例的半导体器件的方法中，在形成栅极氧化层和栅极多晶硅层之后，接着形成覆盖氧化层并使其图案化(与栅极氧化层和栅极多晶硅层一起)，且进行离子注入工艺和隔离物形成工艺，以能够分开源极/漏极区域和栅极多晶硅图案的硅化。此后，沉积金属并在源极/漏极区域上通过热处理形成硅化物。此时，由覆盖氧化层保护的栅极多晶硅图案没有被硅化。
此后，移除覆盖氧化层，将离子注入该栅极多晶硅图案，沉积金属，并通过热处理由栅极多晶硅图案和沉积于其上的金属形成硅化物。当该栅极多晶硅图案相对较薄时，该多晶硅图案基本上可以被完全硅化，以使得与此处描述的现有技术的实施例相比，由于金属和多晶硅之间热膨胀系数的不同引起的有缺陷的器件显著减少。由于已形成源极/漏极硅化物(例如，F1)，因此在多种情况下(例如，此处描述的“薄栅极”实施例)，在源极/漏极硅化物F1上顺序沉积更多金属并对其进行热处理(例如，用于形成栅极硅化物F2)除了可能对源极/漏极硅化物F1的化学计量(stoichiometry)产生影响，对源极/漏极硅化物F1几乎没有影响。
参照图6，使用上述根据实施例的方法制造的半导体器件包括：半导体衬底10，包括源极/漏极区域62；源极/漏极区域62之间的沟道C；沟道C上的栅极氧化层20；第一金属硅化物栅极F2，其在栅极氧化层上且包括金属和多晶硅的化合物；以及隔离物50，其形成于栅极氧化层20和金属硅化物栅极F2的侧面上。在此，该金属可以包括W、Ti、Co、和/或Ni。栅极30或栅极硅化物F2的厚度是栅极氧化层20的厚度的20-30倍。在某些实施例中，栅极30或栅极硅化物F2的厚度可以是30-60nm。在移除了覆盖氧化层之后，该半导体器件的栅极的硅化厚度可以是30-60nm，这可能必要地或有效地导致厚度减少了大约移除的覆盖氧化层的厚度。
根据上述半导体器件及其制造方法，将厚度相对薄的多晶硅图案硅化，从而可以显著地减小由金属和多晶硅之间的热膨胀系数的不同导致的有缺陷的器件的形成速率，由此，可以提高制造的半导体器件的电学特性。
在本说明书中，对“一个实施例”、“实施例”、“示例性实施例”等的引用是指与该实施例相关联的描述的特定特征、结构或特性包含在本发明的至少一个实施例中。说明书中多处出现的这些用语并不都参照同一实施例。而且，当与任何实施例相关联地描述特定的特征、结构或特性时，默认本领域的技术人员能将这些特征、结构或特性实施在其它的实施例上。
尽管已参照一些说明性实施例描述了实施例，但应理解的是，本领域的技术人员可以作出大量其它修改和实施例，这些修改和实施例将落入本公开的原理的构思和范围内。尤其是，在说明书、附图和所附权利要求书的范围内的组成部件和/或目标组合排列内可能有多种变化和修改。除组成部件和/或目标组合排列的变化和修改之外，对本领域技术人员来说，可选择的使用也是显然的。

Claims (10)

1.一种用于制造半导体器件的方法，该方法包括以下步骤：
在半导体衬底上顺序地形成栅极氧化层、栅极多晶硅层以及覆盖氧化层；
在该覆盖氧化层上形成光致抗蚀剂图案；
使用该光致抗蚀剂图案作为蚀刻掩模顺序地蚀刻该覆盖氧化层、该栅极多晶硅层以及该栅极氧化层；
使用该光致抗蚀剂图案作为离子注入掩模将第一离子注入该半导体衬底中，以形成多个隔离物；
在已注入了离子的半导体衬底上进行热扩散工艺，以形成源极/漏极区域；
移除该覆盖氧化层并将第二离子注入该栅极多晶硅层；以及
在该栅极多晶硅层上沉积金属，然后由该金属和该栅极多晶硅层形成金属硅化物。
2.如权利要求1所述的方法，其中该覆盖氧化层的厚度是该栅极多晶硅层的厚度的1-3倍。
3.如权利要求1所述的方法，其中该栅极多晶硅层的厚度是30-60nm，而该覆盖氧化层的厚度是30-180nm。
4.如权利要求1所述的方法，其中该金属包括W、Ti、Co或Ni。
5.如权利要求1所述的方法，其中形成该金属硅化物基本上消耗了整个该栅极多晶硅层。
6.一种半导体器件，包括：
半导体衬底，其包括源极区域和漏极区域、以及该源极区域与该漏极区域之间的沟道；
栅极氧化层，其位于该沟道上；
栅极，其位于该栅极氧化层上，且该栅极包括W硅化物、Ti硅化物或Ni硅化物；以及
多个隔离物，其位于该栅极氧化层上和该栅极的侧面上。
7.如权利要求6所述的半导体器件，其中该栅极的厚度是该栅极氧化层的厚度的20-30倍。
8.如权利要求6所述的半导体器件，其中该栅极的厚度是30-60nm。
9.如权利要求6所述的半导体器件，其中该栅极基本上由W硅化物、Ti硅化物或Ni硅化物组成。
10.如权利要求6所述的半导体器件，其中该半导体器件还包括在该半导体衬底中接近所述多个隔离物的多个源极/漏极端子，所述源极/漏极端子包括第一离子，且该栅极包括第二离子。
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