CN101131928B - 在多孔低-k介电层中形成双镶嵌特征的方法 - Google Patents

在多孔低-k介电层中形成双镶嵌特征的方法 Download PDF

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Publication number
CN101131928B
CN101131928B CN2007101426514A CN200710142651A CN101131928B CN 101131928 B CN101131928 B CN 101131928B CN 2007101426514 A CN2007101426514 A CN 2007101426514A CN 200710142651 A CN200710142651 A CN 200710142651A CN 101131928 B CN101131928 B CN 101131928B
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gas
dielectric layer
layer
etching
porous low
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CN101131928A (zh
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S·S·康
S·J·曹
T·蔡
T·韩
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Lam Research Corp
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Lam Research Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
CN2007101426514A 2006-08-21 2007-08-20 在多孔低-k介电层中形成双镶嵌特征的方法 Active CN101131928B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/507,862 US8124516B2 (en) 2006-08-21 2006-08-21 Trilayer resist organic layer etch
US11/507862 2006-08-21

Publications (2)

Publication Number Publication Date
CN101131928A CN101131928A (zh) 2008-02-27
CN101131928B true CN101131928B (zh) 2011-11-02

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CN2007101426514A Active CN101131928B (zh) 2006-08-21 2007-08-20 在多孔低-k介电层中形成双镶嵌特征的方法

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Country Link
US (1) US8124516B2 (enExample)
JP (1) JP5165306B2 (enExample)
KR (1) KR101392570B1 (enExample)
CN (1) CN101131928B (enExample)
MY (1) MY150187A (enExample)
SG (1) SG140537A1 (enExample)
TW (1) TWI427696B (enExample)

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US8721797B2 (en) 2009-12-11 2014-05-13 Novellus Systems, Inc. Enhanced passivation process to protect silicon prior to high dose implant strip
US9373497B2 (en) 2007-04-04 2016-06-21 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films
US9564344B2 (en) 2009-12-11 2017-02-07 Novellus Systems, Inc. Ultra low silicon loss high dose implant strip

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US8193096B2 (en) 2004-12-13 2012-06-05 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry
US7595005B2 (en) * 2006-12-11 2009-09-29 Tokyo Electron Limited Method and apparatus for ashing a substrate using carbon dioxide
US8003488B2 (en) * 2007-09-26 2011-08-23 International Business Machines Corporation Shallow trench isolation structure compatible with SOI embedded DRAM
CN103258729B (zh) 2007-12-21 2016-07-06 朗姆研究公司 硅结构的制造和带有形貌控制的深硅蚀刻
KR101791685B1 (ko) * 2008-10-14 2017-11-20 노벨러스 시스템즈, 인코포레이티드 수소 이용 화학 반응으로 고용량 주입 스트립(ｈｄｉｓ) 방법 및 장치
US8173547B2 (en) * 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
CN101958277B (zh) * 2009-07-16 2013-01-23 中芯国际集成电路制造(上海)有限公司 金属布线沟槽的形成方法
US7637269B1 (en) 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
JP5532826B2 (ja) * 2009-11-04 2014-06-25 富士通セミコンダクター株式会社 半導体素子の製造方法
CN102208333A (zh) * 2011-05-27 2011-10-05 中微半导体设备(上海)有限公司 等离子体刻蚀方法
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
CN102364670B (zh) * 2011-09-15 2013-06-12 上海华力微电子有限公司 金属铜大马士革互联结构的制造方法
US9666414B2 (en) 2011-10-27 2017-05-30 Applied Materials, Inc. Process chamber for etching low k and other dielectric films
CN103227108B (zh) * 2012-01-31 2016-01-06 中微半导体设备(上海)有限公司 一种有机物层刻蚀方法
CN102915959B (zh) * 2012-10-08 2015-06-17 上海华力微电子有限公司 一种简化存储器中字线介电质膜刻蚀成型工艺的方法
US9385000B2 (en) * 2014-01-24 2016-07-05 United Microelectronics Corp. Method of performing etching process

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US6258732B1 (en) * 1999-02-04 2001-07-10 International Business Machines Corporation Method of forming a patterned organic dielectric layer on a substrate
CN1591818A (zh) * 2003-08-29 2005-03-09 华邦电子股份有限公司 双镶嵌式开口结构的制作方法

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US4484979A (en) 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4659426A (en) 1985-05-03 1987-04-21 Texas Instruments Incorporated Plasma etching of refractory metals and their silicides
US4772488A (en) * 1987-03-23 1988-09-20 General Electric Company Organic binder removal using CO2 plasma
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US6037266A (en) * 1998-09-28 2000-03-14 Taiwan Semiconductor Manufacturing Company Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher
JP3803528B2 (ja) * 2000-03-31 2006-08-02 株式会社東芝 半導体装置の製造方法及び半導体装置
US6794293B2 (en) * 2001-10-05 2004-09-21 Lam Research Corporation Trench etch process for low-k dielectrics
US7109119B2 (en) * 2002-10-31 2006-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Scum solution for chemically amplified resist patterning in cu/low k dual damascene
US6995087B2 (en) 2002-12-23 2006-02-07 Chartered Semiconductor Manufacturing Ltd. Integrated circuit with simultaneous fabrication of dual damascene via and trench
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JP2004253659A (ja) 2003-02-20 2004-09-09 Renesas Technology Corp 半導体装置の製造方法
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JP4940722B2 (ja) * 2006-03-24 2012-05-30 東京エレクトロン株式会社 半導体装置の製造方法及びプラズマ処理装置並びに記憶媒体
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US6258732B1 (en) * 1999-02-04 2001-07-10 International Business Machines Corporation Method of forming a patterned organic dielectric layer on a substrate
CN1591818A (zh) * 2003-08-29 2005-03-09 华邦电子股份有限公司 双镶嵌式开口结构的制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373497B2 (en) 2007-04-04 2016-06-21 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US8721797B2 (en) 2009-12-11 2014-05-13 Novellus Systems, Inc. Enhanced passivation process to protect silicon prior to high dose implant strip
US9564344B2 (en) 2009-12-11 2017-02-07 Novellus Systems, Inc. Ultra low silicon loss high dose implant strip
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films

Also Published As

Publication number Publication date
JP5165306B2 (ja) 2013-03-21
CN101131928A (zh) 2008-02-27
US20080044995A1 (en) 2008-02-21
TW200830405A (en) 2008-07-16
US8124516B2 (en) 2012-02-28
KR101392570B1 (ko) 2014-05-08
TWI427696B (zh) 2014-02-21
JP2008060565A (ja) 2008-03-13
MY150187A (en) 2013-12-13
KR20080017287A (ko) 2008-02-26
SG140537A1 (en) 2008-03-28

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