JP2007528610A - ラインエッジラフネス制御 - Google Patents
ラインエッジラフネス制御 Download PDFInfo
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- 238000005530 etching Methods 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000012545 processing Methods 0.000 claims abstract description 23
- 238000006116 polymerization reaction Methods 0.000 claims abstract description 10
- 239000000203 mixture Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000011368 organic material Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 239000003623 enhancer Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 81
- 239000006117 anti-reflective coating Substances 0.000 description 80
- 241000699666 Mus <mouse, genus> Species 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000012044 organic layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 241000699670 Mus sp. Species 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Drying Of Semiconductors (AREA)
Abstract
【選択図】図3
Description
本発明の一実施例において、エッチング層204は、シリコンウエハ基板208の上に位置するシリコン酸化物の誘電体層である。ARC層は、有機ARC材料である下部反射防止膜(Bottom−ARC、すなわちBARC)である。BARCは、フォトレジストマスクと同様の剥離特性を有するように、フォトレジストマスクに類似していることが好まれる。他の実施形態では、ARC層をその他の有機材料で作成して有機ARC層を形成することができる。フォトレジストマスク220は、193対応のフォトレジストで形成される。他の実施例では、フォトレジストマスクは、193対応のフォトレジストマスクまたは更に次世代のフォトレジストマスクで形成可能である。このようなマスク材料は柔らかいので、ラインエッジラフネスを生じたりエッチングを不均一にしたりする恐れがある。本発明は、このような柔らかいフォトレジスト材料の限界を補うことができる。
208…基板
216…ARC層
220…フォトレジストマスク
228…微細構造
400…プラズマ処理室
402…閉じ込めリング
404…上部電極
408…下部電極
410…ガス供給源
412…ARC開口用エッチャントガス供給源
416…ARC開口用エッチング増進ガス供給源
418…ARC開口用エッチング重合ガス供給源
419…微細構造エッチング用ガス供給源
420…排気ポンプ
428…反応器の頂部
435…コントローラ
448…RF電源
452…室壁
500…コンピュータシステム
502…モニタ
504…ディスプレイ
506…ハウジング
508…ディスクデバイス
510…キーボード
512…マウス
514…ディスク
520…システムバス
522…プロセッサ
524…メモリ
526…固定ディスク
530…スピーカ
540…ネットワークインターフェース
620…フォトレジストマスク
804…エッチング層
808…基板
816…ARC層
820…フォトレジストマスク
904…微細構造
908…ラインエッジラフネス
Claims (17)
- 基板の上で、エッチング対象層とフォトレジストマスクとの間にARC層を配した状態で、前記フォトレジストマスクを通して前記エッチング対象層をエッチングするための方法であって、
前記基板を処理室の中に置き、
前記処理室の中に、エッチャントガスと、COおよびCH3Fを含む重合ガスとを含むARC開口用混合ガスを供給し、
前記ARC開口用混合ガスからARC開口用プラズマを形成し、
前記ARC層が開口されるまで、前記ARC開口用プラズマで前記ARC層をエッチングし、
前記エッチング対象層が完全にエッチングされる前に、前記ARC開口用混合ガスを停止させる
方法。 - 請求項1に記載の方法であって、
ARC開口用プラズマは、前記エッチング対象層に対する選択性よりも高い選択性で前記ARCをエッチングする、方法。 - 請求項1ないし2のいずれかに記載の方法であって、
前記COの流量は、少なくとも150sccmである、方法。 - 請求項1ないし3のいずれかに記載の方法であって、
前記ARC開口用混合ガスは、更に、O2であるエッチング速度増進剤を含む、方法。 - 請求項1ないし4のいずれかに記載の方法であって、
前記エッチング対象層は、誘電体層であり、前記エッチャントガスは、N2およびH2の混合物と、CH4との少なくとも一方を含む、方法。 - 請求項1ないし5のいずれかに記載の方法であって、更に、
前記スタックの上にフォトレジストマスクを用意する方法。 - 請求項1ないし6のいずれかに記載の方法であって、
前記フォトレジストマスクは、193以上の生成フォトレジストで形成される、方法。 - 請求項1ないし7のいずれかに記載の方法であって、
前記ARC層は、有機材料で形成される、方法。 - 請求項1ないし8のいずれかに記載の方法であって、
前記ARC層は、有機材料で形成され、前記フォトレジストマスクは、193以上の生成フォトレジストで形成される、方法。 - 請求項1ないし9のいずれかに記載の方法であって、
前記ARC開口用プラズマは、前記エッチング対象層に対する場合と比べて50:1を超える選択性で前記ARCをエッチングする、方法。 - 請求項1ないし10のいずれかに記載の方法であって、
前記エッチング対象層は、シリコン酸化物である、方法。 - 請求項1ないし11のいずれかに記載の方法であって、
前記ARC開口用プラズマは、前記エッチング対象層をエッチングしない、方法。 - 請求項1ないし12のいずれかに記載の方法で形成された半導体素子。
- 請求項1ないし12のいずれかの方法を実施するための、コンピュータ可読媒体を伴う装置。
- 半導体素子を形成するための方法であって、
エッチング対象層を基板の上に置き、
前記エッチング対象層の上に有機ARC層を形成し、
前記ARC層の上にフォトレジストマスクを形成し、
前記基板を前記処理室の中に置き、
前記処理室の中に、エッチャントガスと、COおよびCH3Fを含む重合ガスとを含むARC開口用混合ガスを供給し、
前記ARC開口用混合ガスからARC開口用プラズマを形成し、
前記ARC層が開口されるまで、前記ARC開口用プラズマで前記ARC層をエッチングし、
前記エッチング対象層が前記ARC開口用プラズマでエッチングされないように、前記ARC開口用混合ガスの供給を停止し、
前記ARC開口用プラズマと異なるエッチング用プラズマを供給し、
前記エッチング対象層を前記エッチング用プラズマでエッチングする
方法。 - 請求項15に記載の方法であって、
前記ARC開口用混合ガスは、更に、O2であるエッチング速度増進剤を含む、方法。 - 請求項15ないし16のいずれかに記載の方法であって、
前記エッチング対象層は、誘電体層であり、前記ARCの開口を可能にするための前記エッチャントガスは、N2およびH2の混合と、CH4とのうち少なくとも一方を含む、方法。
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Application Number | Priority Date | Filing Date | Title |
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US10/798,456 US20040171260A1 (en) | 2002-06-14 | 2004-03-10 | Line edge roughness control |
PCT/US2005/007386 WO2005088693A1 (en) | 2004-03-10 | 2005-03-02 | Line edge roughness control |
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Publication Number | Publication Date |
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JP2007528610A true JP2007528610A (ja) | 2007-10-11 |
JP2007528610A5 JP2007528610A5 (ja) | 2008-10-02 |
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JP2007502898A Pending JP2007528610A (ja) | 2004-03-10 | 2005-03-02 | ラインエッジラフネス制御 |
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US (1) | US20040171260A1 (ja) |
JP (1) | JP2007528610A (ja) |
KR (1) | KR20070011306A (ja) |
CN (1) | CN101027759A (ja) |
TW (1) | TW200537580A (ja) |
WO (1) | WO2005088693A1 (ja) |
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US20040171260A1 (en) * | 2002-06-14 | 2004-09-02 | Lam Research Corporation | Line edge roughness control |
US7547635B2 (en) * | 2002-06-14 | 2009-06-16 | Lam Research Corporation | Process for etching dielectric films with improved resist and/or etch profile characteristics |
US20090311871A1 (en) * | 2008-06-13 | 2009-12-17 | Lam Research Corporation | Organic arc etch selective for immersion photoresist |
TWI627667B (zh) | 2012-11-26 | 2018-06-21 | 應用材料股份有限公司 | 用於高深寬比半導體元件結構具有污染物去除之無黏附乾燥處理 |
GB201315424D0 (en) * | 2013-08-29 | 2013-10-16 | Occles Ltd | An eye cover device |
CN106575630B (zh) * | 2014-07-13 | 2021-05-25 | 科磊股份有限公司 | 使用叠加及成品率关键图案的度量 |
US9899219B2 (en) * | 2016-02-19 | 2018-02-20 | Tokyo Electron Limited | Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables |
CN108885402B (zh) * | 2016-02-29 | 2020-01-14 | 东京毅力科创株式会社 | 选择性SiARC去除 |
Citations (2)
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- 2005-03-02 JP JP2007502898A patent/JP2007528610A/ja active Pending
- 2005-03-02 KR KR1020067018628A patent/KR20070011306A/ko not_active Application Discontinuation
- 2005-03-02 WO PCT/US2005/007386 patent/WO2005088693A1/en active Application Filing
- 2005-03-08 TW TW094107021A patent/TW200537580A/zh unknown
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JP2003133287A (ja) * | 2001-10-30 | 2003-05-09 | Matsushita Electric Ind Co Ltd | ドライエッチング方法 |
WO2004003988A1 (ja) * | 2002-06-27 | 2004-01-08 | Tokyo Electron Limited | プラズマ処理方法 |
Also Published As
Publication number | Publication date |
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CN101027759A (zh) | 2007-08-29 |
KR20070011306A (ko) | 2007-01-24 |
US20040171260A1 (en) | 2004-09-02 |
TW200537580A (en) | 2005-11-16 |
WO2005088693A1 (en) | 2005-09-22 |
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