CN101120444A - 形成自钝化互连的方法以及所得到的装置 - Google Patents
形成自钝化互连的方法以及所得到的装置 Download PDFInfo
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- CN101120444A CN101120444A CNA2006800050451A CN200680005045A CN101120444A CN 101120444 A CN101120444 A CN 101120444A CN A2006800050451 A CNA2006800050451 A CN A2006800050451A CN 200680005045 A CN200680005045 A CN 200680005045A CN 101120444 A CN101120444 A CN 101120444A
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Abstract
一种形成自钝化互连的方法。两个相匹配的键合结构(213、223)中的至少一个,至少部分由第一金属和第二金属(或其它元素)的合金形成。第二金属能够迁移通过第一金属到达相匹配的键合结构的自由表面。在键合期间,这两个相匹配的键合结构(213、223)键合在一起以形成互连,并且第二金属偏析到该互连的自由表面以形成钝化层(240)。说明并要求保护其它的实施例。
Description
技术领域
所公开的实施例通常涉及用于集成电路器件的互连的形成,更为具体的,涉及自钝化互连结构的形成。
背景技术
三维晶片键合或晶片叠置是将两个或多个半导体晶片键合在一起,在所述半导体晶片上已形成集成电路。随后将形成的晶片叠层切割成分离的叠置管芯,每一个叠置管芯具有多个集成电路层。晶片叠置可以提供许多潜在的好处。例如,通过晶片叠置形成的集成电路(IC)器件可以提供增强的性能和功能性,同时可能降低成本和提高成形系数。通过晶片叠置形成的片上系统(SOC)结构可以在利用另外具有不兼容的工艺流程的不同技术(例如,逻辑电路和动态随机存取存储器(DRAM))的叠置管芯之间获得高带宽连接性。同样,通过利用三维晶片键合,可以实现较小的管芯尺寸,这可以减小互连延迟。对于晶片叠置技术有许多潜在的应用,包括高性能处理装置、视频和图形处理器、高密度和高带宽存储器芯片、之前所述的SOC解决方案,以及其它应用。
一种用于三维晶片键合的方法是金属键合。在金属晶片键合中,通过将形成在晶片之一上的金属键合结构与形成在另一个晶片上的相应的金属键合结构键合,来结合两个晶片。例如,可以在第一晶片上形成若干铜键合焊盘,并且可以在第二晶片上形成相应数量的铜键合焊盘。将第一和第二晶片对准并集合在一起,使得第一晶片上的每一个铜焊盘与第二晶片上相应的一个铜焊盘相匹配。然后执行键合工艺(例如,通过施加压力和/或升高温度)以使相匹配的键合焊盘结合在一起,由此在第一和第二晶片之间形成多个互连,此时形成晶片叠层。第一和第二晶片中的每一个包括用于多个管芯的集成电路,并且将晶片叠层切割成许多叠置管芯。每一个叠置管芯包括一个来自第一晶片的管芯和另一个来自第二晶片的管芯,这些管芯通过一些先前形成的互连被机械和电耦合在一起。
附图说明
图1是示出形成自钝化互连的方法的实施例的示意图;
图2A-2D是示出图1的方法的实施例的示意图;
图3A-3C是示出可以用于形成自钝化互连的键合结构的各种实施例的示意图;
图4是示出如图2C所示的两个键合结构的对准和键合的实施例的示意图;
图5A是示出可以包括自钝化互连的晶片叠层的实施例的示意图;
图5B是示出如沿图5A中B-B线截取的图5A的晶片叠层的截面图的示意图;
图6是示出计算机系统的实施例的示意图,该计算机系统可以包括根据所公开的实施例形成的部件。
具体实施方式
参考图1,其示出形成自钝化互连的方法的实施例。在图2A-2D以及图3A-3C和图4中进一步示出图1的方法的实施例,并且参考在下文中所提及的这些附图。
现在参考图1中的方框110,在第一衬底上形成一个或多个键合结构,这些键合结构中的每一个至少部分包括第一金属和第二金属(或其它元素)。这在图2A中示出,图2A示出了具有表面211的第一衬底210,在所述表面211上形成了大量的键合结构213。每一个键合结构213与形成在衬底210上的导体电耦合。在一个实施例中,衬底210包括半导体晶片,在该半导体晶片上形成用于大量管芯的集成电路。在第一衬底210的表面211上还可以设置电介质材料层217。电介质层217可以包括任何适当的电介质材料,例如SiO2、Si3N4、掺杂碳的氧化物(CDO)、SiOF、或纺制(spun-on)材料(例如,纺制玻璃或聚合物)。在一个实施例中,键合结构213在电介质层217的外表面(例如,通过抛光或回蚀电介质层可以实现)的上方延伸。
如上所述,键合结构213至少部分包括第一金属和第二金属(或其它元素)的合金。第一金属包括导电金属,该导电金属最终形成部分导电互连。在一个实施例中,第一金属包括铜。然而,第一金属可以包括任何其它适当的导电金属(例如,铝、金、银等)或导电金属合金。同样,如上面所建议的那样,仅每一个键合结构213的一部分可以包括第一和第二金属的合金,而该键合结构的其它部分主要包括第一金属,如下文中关于图3A-3C所详细说明的那样。
第二金属或元素包括具有在将要形成的互连上形成钝化层的能力的任何金属(或其它材料)。在一个实施例中,第二金属包括可以扩散穿过第一金属的物质,使得第二金属可以迁移到互连结构的自由表面以形成钝化层。被认为适合用于第二金属的金属包括,但不限于,铝、钴、锡、镁和钛。在一个实施例中,第二元素包括非金属。根据一个实施例,存在于(第一和第二金属的)合金中的第二金属(或元素)的含量处于或低于第二金属在第一金属中的溶度极限。在一个实施例中,第二金属在金属合金中的含量在0.1和10原子百分比之间。例如,如果第一金属包括铜以及第二金属包括铝,则存在于Cu(Al)合金中的铝的含量达到大约3原子百分比。
根据另一个实施例,在室温下,能够使第二金属(或元素)在第一金属内迁移的扩散机制缓慢或基本不存在,使得将第二金属“俘获”在第一金属的晶格结构中,这能防止钝化层的过早形成。过早形成钝化层(例如,在键合结构213与第二衬底的键合结构键合之前,如下面所述)可以潜在地妨碍金属键合。然而在高温下,第二金属(或元素)能够扩散穿过第一金属,使得第二金属能够偏析到互连结构的自由表面以形成钝化层。某些金属在与另一金属成为合金时迁移到自由表面的趋势是公知的现象且不再进一步说明。
在另一实施例中,键合结构213包括第一金属和两种或多种附加金属(或其它元素)。这些附加金属(或元素)中的每一种包括可以扩散穿过第一金属以形成钝化层的物质。因此,钝化层可以包括两种(或多种)附加金属或其它元素的组合。
在一个实施例中,在含有氧的环境下形成钝化层,并且该钝化层包括第二金属的氧化物(例如,Al2O3)。根据另一实施例,在含有氮的环境下形成钝化层,并且该钝化层包括第二金属的氮化物(例如,AlN)。在另一实施例中,钝化层主要包括第二金属(或其它金属)。
参考图1中的方框120,在第二衬底上形成一个或多个键合结构,这些键合结构中的每一个包括第一金属。第二衬底上的键合结构可以任选包括第二金属(或其它元素),使得每一个键合结构的至少一部分包括第一和第二金属的合金。这在图2B中示出,图2B示出了具有表面221的第二衬底220,在所述表面221上形成了大量的键合结构223。键合结构223中的每一个可以与形成在衬底220中的导体电耦合。在一个实施例中,衬底220包括另一个半导体晶片,在该半导体晶片上形成用于相应数量的管芯的集成电路。在第二衬底220的表面221上还可以设置电介质材料层227。电介质层227可以包括任何适当的电介质材料,例如SiO2、Si3N4、CDO、SiOF、或纺制材料(例如,纺制玻璃或聚合物)。在一个实施例中,键合结构223在电介质层227的外表面(例如,通过抛光或回蚀电介质层可以实现)的上方延伸。
第二衬底220上的键合结构223与第一衬底210上的键合结构213对准并匹配,并且执行键合工艺以在第一和第二衬底之间形成互连。这些互连中的每一个由第一衬底210上的键合结构213以及第二衬底220上的匹配键合结构223形成,并且在每一个互连上由第二金属(或元素或其它金属和/或元素的组合)形成钝化层。如上所述,第二衬底上的键合结构223可以主要包括第一金属(没有第二金属)。根据该实施例,相匹配的键合结构中只有一个(例如,键合结构213或键合结构223)包括第二金属,并且钝化层由存在于这一键合结构中的第二金属形成。然而,根据另一个实施例,第二衬底220上的键合结构223至少部分包括第一金属和第二金属的合金。因此,最终形成在每一个互连结构上的钝化层由分别存在于第一和第二衬底210、220的相匹配的键合结构213、223中的每一个中的第二金属形成。以上说明第一和第二金属(或元素)的特性。
第一和第二衬底210、220上的键合结构213、223可以具有任何适当的形状,只要第一衬底210上的键合结构213能与第二衬底220上的键合结构223匹配和键合以形成在这两个衬底之间延伸的互连即可。在一个实施例中,键合结构213、223中的每一个包括圆形或正方形的键合焊盘。然而,应该理解的是所公开的实施例不限于形成这种键合焊盘,而且此外,键合结构213、223可以包括任何其它适当的形状(例如,球形突起)。在一个实施例中,键合结构213、223具有在0.1μm和10μm之间的厚度T(参见图3A)。键合结构213、223也可以通过任何适当的工艺形成。下面将参考图3A-3C更加详细地说明键合结构213、223的各种实施例。
再次参照图1,并且特别是参照方框130,将第一和第二衬底的键合结构对准并且为键合而使其接触,使得第一衬底上的键合结构可以与第二衬底上的键合结构键合,以在第一和第二衬底之间形成互连。这进一步在图2C中示出,其中将第一和第二衬底210、220对准并且为键合而使其集合在一起。第一衬底210上的键合结构213中的每一个与第二衬底220上的键合结构223中相对应的一个对准并相匹配。
在图3A至3C中示出在对准和接触后的键合结构213、223的各种实施例。首先参考图3A,其示出键合结构213a、223a的实施例。整个键合结构213a、223a(或这些结构的主要部分)包括第一和第二金属的合金(例如,铜和铝的合金)。可以通过如下方式形成键合结构213a:首先在衬底210上沉积电介质材料层217,并且然后在键合结构的位置处将通孔或其它孔(例如,通过掩模和蚀刻工艺)形成到电介质层217中。然后在通孔中沉积(例如,通过均厚沉积(blanketdeposition)步骤,其随后是诸如化学机械抛光的平坦化步骤)第一和第二金属的合金以形成键合结构213a。也可以抛光或回蚀电介质层217以暴露键合结构的上部,如图3A所示。以相似的方式在衬底220上形成键合结构223a。
参考图3B,其示出键合结构213b、223b的另一实施例。键合结构213b包括:上部301,该部分主要包括第一金属(例如,铜);以及下部303,该部分包括第一和第二金属(例如,铜和铝)的合金。同样,键合结构223b包括:上部302,该部分主要包括第一金属;以及下部304,该部分包括第一和第二金属的合金。可以通过如下方式形成键合结构213b:首先在衬底210上沉积电介质材料层217,并且然后在键合结构的位置处将通孔或其它孔(例如,通过掩模和蚀刻工艺)形成到电介质层217中。然后在通孔中沉积第一和第二金属的合金层(例如,通过选择性沉积到位于键合结构的位置之下的衬底210中的导体上)以形成键合结构的下部303。然后在合金层上沉积第一金属层(例如,通过选择性沉积到先前沉积在每一个通孔中的合金层上,并且也许,随后是平坦化步骤)以形成键合结构213a的上部301。也可以抛光或回蚀电介质层217以暴露键合结构的上部,如图3B所示。以相似的方式在衬底220上形成键合结构223b。
接下来参考图3C,其示出键合结构213c、223c的其他实施例。键合结构213c包括主要由第一金属(例如,铜)构成的内部305。键合结构213c的内部305被由第一和第二金属(例如,铜和铝)的合金构成的外部307所环绕。同样,键合结构223c包括主要由第一金属构成的内部306,该内部306被由第一和第二金属的合金构成的外部308所环绕。可以通过如下方式形成键合结构213c:首先在衬底210上沉积电介质层217,并且然后在键合结构的位置处将通孔或其它孔(例如,通过掩模和蚀刻工艺)形成到电介质层217中。然后可以在通孔中沉积第一和第二金属的合金的籽晶层(例如,通过均厚沉积工艺)以形成键合结构的外部307。然后在合金层上沉积第一金属层(例如,通过随后的均厚沉积步骤,该步骤之后可以是平坦化步骤)以形成键合结构213c的内部305。也可以抛光或回蚀电介质层217以暴露键合结构的上部,如图3C所示。以相似的方式在衬底220上形成键合结构223c。
在图3A-3C中的每一幅图中,键合结构213、223是相同的。然而,应该理解的是,第一和第二衬底210、220上的键合结构可以是不同的。例如,第一衬底210可以具有与图3A所示的键合结构相似的键合结构,而第二衬底220可以具有与图3B所示的键合结构相似的键合结构。作为另一实例,第一衬底210可以具有与图3A到3C中任意一幅所示的键合结构相似的键合结构,而第二衬底220可以具有主要由第一金属(例如,铜)构成的键合结构。读者应该意识到,取决于将要形成的互连的期望特性和工作环境,可以使用相匹配的键合结构的任意组合。
在键合期间,将第一衬底210上的键合结构213与第二衬底220上的键合结构223键合以形成在这两个衬底之间延伸的互连。为了最优化的键合,在一些实施例中期望抑制钝化层在键合结构213、223之间的界面(参考图2C、3A-3C和4中的参考数字290)处的形成。因此,根据一个实施例,期望延迟第二金属迁移到键合结构213、223的界面表面,直到完成键合结构之间的键合为止。在一个实施例中,这可以通过在界面290处设置主要包括第一金属(例如,铜)的材料来实现。图3B和3C中的每一幅都是键合结构(213b、223b和213c、223c)的实例,其在键合结构之间的界面290处提供第一金属层(或一定数量的第一金属)。界面290处的该第一金属层(或一定数量的第一金属)主要用作延迟功能,该功能延缓第二金属在键合之前到界面的迁移。在另一个实施例中,可以在金属层之间设置一个或多个金属(或其它元素)附加层以在键合之前进一步延迟第二金属到界面的迁移(例如,在图3B和3C中的每一幅图中,可以在Cu(Al)和Cu层之间设置材料附加层)。
在图4中进一步示出两个键合结构213、223的对准。参考该图,当将两个键合结构213、223对准并使其接触时,有大量的暴露在周围环境下的自由表面(例如,键合结构的外表面)。这些暴露的自由表面包括键合结构213、223的在它们各自的电介质层217、227上延伸的表面418、428。此外,由于键合结构213、223之间的未对准,暴露的自由表面419、429也可以存在于界面290处。在键合结构213、223键合以形成互连之后,这些自由表面418、428、419、429可以继续暴露在周围环境下,使得它们易于氧化和腐蚀。然而,在键合期间或之后(由第二金属迁移到这些自由表面)形成的钝化层能够抑制这种氧化和腐蚀(尽管钝化层本身可以部分地通过氧化工艺形成)。
键合可以在任何适当的工艺条件下进行。在一个实施例中,在压力和高温下使第一和第二衬底210、220上的键合结构213、223接触。根据一个实施例,键合结构213、223之间的接触压力在高达5Mpa的范围内,并且在高达450摄氏度的温度下进行键合。其中键合发生的周围环境也会影响键合、以及钝化层的形成。在一个实施例中,在包括氧的气氛下进行键合,在这种情况下所形成的钝化层可以是第二金属的氧化物(例如,Al2O3)。在另一个实施例中,在包括氮的气氛下进行键合,并且所形成的钝化层可以是第二金属的氮化物(例如,AlN)。在另一实施例中,在真空下进行键合,并且所形成的钝化层可以主要包括第二金属(尽管如果键合衬底不被密封,则随后将会发生钝化层的氧化)。这仅为在其下进行键合的条件的几个实例,并且读者应该意识到,取决于形成的互连的期望特性,可以使用其它工艺条件。
在键合期间,应该出现两个过程:(1)形成匹配的键合结构213、223之间的金属键合以形成在第一和第二衬底210、220之间延伸的互连(参见方框130);以及(2)第二金属迁移到键合结构213、223的自由表面(参见图4)以在每一个互连上形成钝化层,如在图1的方框140中所阐述的那样。这在图2D中进一步示出,该图示出由目前彼此键合在一起的匹配的键合结构213、223形成的互连230。此外如图2D所示,在每一个互连230上形成钝化层240,该钝化层240由第二金属形成(例如,第二金属的氧化物或氮化物,或者也许主要由第二金属形成)。在一个实施例中,每一个互连230主要包括第一金属;然而,在另一个实施例中,第二金属中的一些可以保留在互连230内(例如,第二金属中的一些可以保持“俘获”在第一金属的晶格结构中,因为在所有的第二金属偏析到自由表面之前停止键合)。上述两个过程—例如,键合和钝化层的形成—可以在一个实施例中同时(或几乎同时)发生。然而,在另一个实施例中,这两个过程可以依次发生(例如,可以首先发生键合,随后第二金属迁移到自由表面和形成钝化层)。
钝化层240的厚度是第一和第二金属的选择以及在其下形成该层的处理条件(例如,气氛、温度和时间,等等)的函数。可以确定该厚度以获得钝化层240的期望特性(例如,抗腐蚀性、抗电迁移性、电绝缘,等等)。根据一个实施例,互连230上的钝化层240具有在大约5埃与1000埃之间的厚度。例如,如果钝化层240包括Al2O3(并且互连主要为铜),则钝化层可以具有大约30埃的厚度。作为另一实例,如果钝化层240包括AIN(并且互连主要为铜),则钝化层可以具有大约100埃的厚度。读者应该意识到能够实现其它的厚度,如所期望的那样。
如前所述,可以使用上述用于形成自钝化互连的实施例将半导体晶片键合在一起以形成晶片叠层。在图5A和5B中示出这种晶片叠层500的一个实施例,其中图5B示出图5A的晶片叠层沿图5A中的线B-B截取的截面图。参考这些附图,晶片叠层500包括第一晶片501和第二晶片502,晶片501、502中的每一个分别包括衬底510、520。每一个晶片501、502的衬底510、520通常包括半导体材料,例如硅(Si)、绝缘体上硅(SOI)、砷化镓(GaAs)等等。在晶片501、502中的每一个上形成了用于大量叠置管芯505的集成电路,并且最终将晶片叠层500切割成这些分离的叠置管芯505。用于每一叠置管芯505的集成电路可以包括形成在第一晶片501的衬底510上的大量有源器件512(例如,晶体管、电容器等等)和形成在第二晶片502的衬底520上的大量有源器件522。
在第一晶片501的表面上设置互连结构514,并在第二晶片502的表面上设置互连结构524。通常,互连结构514、524中的每一个包括大量的金属化层,每一金属化层通过电介质材料(或其它绝缘材料)层与相邻层分开并通过通孔与相邻层互连。互连514、524的电介质层各自通常被称为“层间电介质”(或“ILD”),并且ILD层可以包括任何适当的绝缘材料,例如SiO2、Si3N4、CDO、SiOF或纺制材料(例如,纺制玻璃或聚合物)。每个层上的金属化包括大量的导体(例如,迹线),所述导体可以确定到达每个管芯505的集成电路的信号、电源和接地线以及来自每个管芯505的集成电路的信号、电源和接地线,并且该金属化包括导电材料,例如铜、铝、银、金、以及这些(或其它)材料的合金。
大量的互连530设置在第一和第二晶片501、502之间,并将这两个晶片机械和电耦合在一起。在每一个互连上形成钝化层540。根据一个实施例,互连530主要包括铜,而钝化层540包括铝。根据另一个实施例,钝化层包括氧化铝,而在另一实施例中钝化层包括氮化铝。在一个实施例中,互连自钝化,并且根据一个或多个上述实施例形成它们。
在一个实施例中,第一和第二晶片501、502具有相同的尺寸和形状;然而,在另一个实施例中,这些晶片具有不同的形状和/或尺寸。在一个实施例中,第一和第二晶片501、502包括相同的材料,而在另一实施例中,第一和第二晶片501、502包括不同的材料。同样,虽然晶片501、502可以利用基本相同的工艺流程来制造,但是在另一个实施例中,晶片501、502利用不同的工艺流程来制造。在一个实施例中,晶片中的一个(例如,晶片501)包括利用第一种工艺流程形成的逻辑电路,而另一个晶片(例如,晶片502)包括利用第二种不同的工艺流程形成的存储器电路(例如,DRAM、SRAM,等等)。因此,读者应该意识到,所公开的实施例可应用于任何类型的晶片或晶片组合一而不考虑尺寸、形状、材料、结构和/或工艺流程-并且,如在本文中使用的那样,术语“晶片”在范围上不应该限于任何特定类型的晶片或晶片组合。
最后,将晶片叠层500切割成大量的分离的叠置管芯505,如上所述。每个叠置管芯将包括来自第一晶片501的管芯和来自第二晶片502的管芯。利用互连530中的一些将这两个叠置管芯电和机械地互连。
至少部分在形成三维晶片叠层的背景下说明用于形成自钝化互连的上述实施例。然而,应该理解的是所公开的实施例不限于应用于晶片叠置,并且此外,所公开的实施例可以应用于其它的器件或应用。例如,上述实施例可以用于在集成电路管芯与封装衬底之间形成自钝化互连,和/或在封装和电路板之间形成自钝化互连。上述实施例也可以应用于晶片与管芯的键合和管芯与管芯的键合。
同样,值得注意的是,在图2A-2D中,为了简化说明示出有限数量的键合结构和互连。类似的,在图5A-5B中,为了清楚和简化说明,仅示出有限数量的互连530以及有源器件512、522。然而,如读者将会意识到的那样,图2A-2D的衬底210、220和图5A-5B的半导体晶片501、502可以包括数千或上百万个这样的互连(230或530)。类似的,形成在晶片501、502上的用于每个叠置管芯505的集成电路实际上可以包括上千万、甚至上亿的有源器件512、522(例如,晶体管)。因此,应该理解的是图2A-2D和图5A-5B仅仅是为有助于理解所公开的实施例而示出的示意性图,并且此外不应该从这些示意性图中得出不必要的限制。
参考图6,其示出计算机系统600的实施例。计算机系统600包括将不同部件耦合到其上的总线605。总线605旨在表示使系统600的部件互连的一个或多个总线(例如,系统总线、外围部件接口(PCI)总线、小型计算机系统接口(SCSI)总线等等)的集合。为了方便理解将这些总线表示为单个总线605,并且应该理解的是系统600不受限制。本领域的普通技术人员应该意识到计算机系统600可以具有任何适当的总线结构,并且可以包括任意数量的总线及其组合。
处理装置610与总线605耦合。处理装置610可以包括任何适当的处理装置或系统,包括微处理器、网络处理器、特定用途集成电路(ASIC)、或场可编程门阵列(FPGA)、或相似的装置。应该理解的是,虽然图6示出单个的处理装置610,但是计算机系统600可以包括两个或多个处理装置。
计算机系统600还包括与总线605耦合的系统存储器620,例如,系统存储器620包括任何适当类型和数量的存储器,例如静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、同步DRAM(SDRAM)、或双数据速率DRAM(DDRDRAM)。在计算机系统600操作期间,操作系统和其它应用软件驻留在系统存储器620中。
计算机系统600还可以包括与总线605耦合的只读存储器(ROM)630。ROM 630可以存储用于处理装置610的指令。系统600还可以包括与总线605耦合的存储装置640。存储装置640包括任何适当的非易失性存储器,例如硬盘驱动器。操作系统和其它程序可以存储在存储器件640中。此外,用于访问可移动存储介质的装置650(例如,软盘驱动器或CD ROM驱动器)可以与总线605耦合。
计算机系统600还可以包括一个或多个与总线605耦合的I/O(输入/输出)装置660。普通的输入装置包括键盘、诸如鼠标的指示装置以及其它的数据输入装置,而普通的输出装置包括视频显示器、打印装置以及音频输出装置。应该意识到这些仅是可以与计算机系统600耦合的I/O装置类型的几个实例。
计算机系统600还可以包括与总线605耦合的网络接口670。网络接口670包括能够将系统600与网络(例如,网络接口卡)耦合的任何适当的硬件、软件、或硬件和软件的组合。网络接口670可以通过任何适当的介质-例如,无线电、铜线、光纤、或其组合—建立与网络的链接,以支持经由任何适当协议(例如,TCP/IP(传输控制协议/网际协议)、HTTP(超文本传输协议)、以及其它协议)的信息交换。
应该理解的是图6所示的计算机系统600旨在表述这种系统的示例性实施例,并且此外,该系统可以包括许多附加部件,为了清楚和容易理解而将其省略。例如,系统600可以包括DMA(直接存储器存取)控制器、与处理装置810相关联的芯片组、附加存储器(例如,高速缓冲存储器)以及附加的信号线和总线。因此,应该理解的是计算机系统600可以不包括图6所示的所有部件。
在一个实施例中,计算机系统600包括具有叠置管芯的部件,所述叠置管芯包括根据一个或多个上述实施例形成的自钝化互连。例如,系统600的处理装置610可以包括这种具有自钝化互连的叠置管芯。然而,应该理解的是系统600的其它部件(例如,网络接口670,等等)可以包括具有自钝化互连的部件的装置。
前面的详细说明和附图仅为示例性的而非限制性的。它们主要用于清楚并全面地理解所公开的实施例,并且不会从其中得出不必要的限制。在不背离所公开的实施例的精神和附属权利要求的范围的情况下,本领域技术人员可以对本文所述的实施例作出各种添加、删除和修改以及想出可选的设置。
Claims (32)
1.一种方法,包括:
在第一衬底上形成键合结构,所述第一衬底的所述键合结构包括导电金属和元素;
在第二衬底上形成键合结构,所述第二衬底的所述键合结构包括所述导电金属和所述元素;以及
将所述第一衬底的所述键合结构与所述第二衬底的所述键合结构键合以在所述第一和第二衬底之间形成互连,其中所述元素迁移到所述键合结构的自由表面以在所述互连上形成钝化层。
2.根据权利要求1所述的方法,还包括在有氧的情况下进行键合,其中所述钝化层包括所述元素的氧化物。
3.根据权利要求1所述的方法,还包括在有氮的情况下进行键合,其中所述钝化层包括所述元素的氮化物。
4.根据权利要求1所述的方法,还包括在真空中进行键合,其中所述钝化层主要包括所述元素。
5.根据权利要求1所述的方法,其中所述第一衬底包括具有用于若干管芯的集成电路的第一半导体晶片,以及所述第二衬底包括具有用于相应数量的管芯的集成电路的第二半导体晶片。
6.根据权利要求1所述的方法,其中形成所述键合结构中的至少一个包括由所述导电金属和所述元素的合金形成所述键合结构。
7.根据权利要求1所述的方法,其中形成所述键合结构中的至少一个包括由所述导电金属和所述元素的合金形成所述键合结构的第一部分,并且主要由所述导电金属形成所述键合结构的第二部分。
8.根据权利要求1所述的方法,其中所述导电金属包括铜。
9.根据权利要求1所述的方法,其中所述元素包括金属。
10.根据权利要求1所述的方法,其中所述元素包括非金属。
11.根据权利要求1所述的方法,其中所述键合结构中的至少一个包括所述元素,并且还包括一种附加元素,其中所述附加元素迁移到所述键合结构的所述自由表面以与所述元素结合形成所述钝化层。
12.一种装置,包括:
第一集成电路管芯;
第二集成电路管芯;
在所述第一管芯和第二管芯之间延伸的多个互连,所述互连中的每一个包括导电金属;以及
设置在所述互连中的每一个上的钝化层,所述钝化层包括能够迁移通过所述导电金属至自由表面的元素。
13.根据权利要求12所述的装置,其中所述钝化层包括所述元素的氧化物。
14.根据权利要求12所述的装置,其中所述钝化层包括所述元素的氮化物。
15.根据权利要求12所述的装置,其中所述钝化层主要包括所述元素。
16.根据权利要求12所述的装置,其中所述导电金属包括铜。
17.根据权利要求16所述的装置,其中所述元素包括选自由铝、锡、钴、镁和钛组成的组的金属。
18.根据权利要求12所述的装置,其中所述元素包括非金属。
19.根据权利要求12所述的装置,其中所述钝化层包括至少一种能够迁移通过所述导电金属至所述自由表面的附加元素。
20.一种方法,包括:
在包括用于若干管芯的电路的第一半导体晶片上形成多个键合焊盘,所述键合焊盘中的每一个包括铜和第二金属;
在包括用于相应数量的管芯的电路的第二半导体晶片上形成多个键合焊盘,所述键合焊盘中的每一个包括铜和所述第二金属;以及
将所述第一晶片上的所述多个键合焊盘中的每一个与所述第二晶片上的所述多个键合焊盘中的相匹配的那个键合焊盘键合以在所述第一和第二晶片之间形成多个互连,其中所述第二金属迁移到所述键合焊盘的自由表面以在所述互连中的每一个上形成钝化层。
21.根据权利要求20所述的方法,其中所述第二金属包括选自由铝、锡、钴、镁和钛组成的组的金属。
22.根据权利要求20所述的方法,其中所述钝化层包括所述第二金属的氧化物或所述第二金属的氮化物。
23.根据权利要求20所述的方法,还包括将键合的晶片切割成大量的叠置管芯,每一个叠置管芯包括一个来自所述第一晶片的管芯、一个来自所述第二晶片的管芯、以及电耦合这两个管芯的一些所述互连。
24.一种方法,包括:
在第一衬底上形成键合结构,所述第一衬底的所述键合结构包括导电金属和元素;
在第二衬底上形成键合结构,所述第二衬底的所述键合结构包括所述导电金属;以及
将所述第一衬底的所述键合结构与所述第二衬底的所述键合结构键合以在所述第一和第二衬底之间形成互连,其中所述元素迁移到所述键合结构的自由表面以在所述互连上形成钝化层。
25.根据权利要求24所述的方法,还包括在有氧的情况下进行键合,其中所述钝化层包括所述元素的氧化物。
26.根据权利要求24所述的方法,还包括在有氮的情况下进行键合,其中所述钝化层包括所述元素的氮化物。
27.根据权利要求24所述的方法,还包括在真空中进行键合,其中所述钝化层主要包括所述元素。
28.根据权利要求24所述的方法,其中形成所述第一衬底的所述键合结构包括由所述导电金属和所述元素的合金形成所述键合结构。
29.根据权利要求24所述的方法,其中形成所述第一衬底的所述键合结构包括由所述导电金属和所述元素的合金形成所述键合结构的第一部分,并且主要由所述导电金属形成所述键合结构的第二部分。
30.根据权利要求24所述的方法,其中所述元素包括金属。
31.根据权利要求24所述的方法,其中所述元素包括非金属。
32.根据权利要求24所述的方法,其中所述第一衬底的所述键合结构还包括一种附加元素,其中所述附加元素迁移到所述键合结构的所述自由表面以与所述元素结合形成所述钝化层。
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US11/081,187 US7402509B2 (en) | 2005-03-16 | 2005-03-16 | Method of forming self-passivating interconnects and resulting devices |
US11/081,187 | 2005-03-16 |
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Country Status (6)
Country | Link |
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US (1) | US7402509B2 (zh) |
JP (1) | JP4777415B2 (zh) |
CN (1) | CN100561714C (zh) |
DE (1) | DE112006000647B4 (zh) |
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WO (1) | WO2006102046A1 (zh) |
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