TWI433268B - 三維積體電路之接合方法及其三維積體電路 - Google Patents

三維積體電路之接合方法及其三維積體電路 Download PDF

Info

Publication number
TWI433268B
TWI433268B TW100133482A TW100133482A TWI433268B TW I433268 B TWI433268 B TW I433268B TW 100133482 A TW100133482 A TW 100133482A TW 100133482 A TW100133482 A TW 100133482A TW I433268 B TWI433268 B TW I433268B
Authority
TW
Taiwan
Prior art keywords
metal
integrated circuit
layer
film layer
dimensional integrated
Prior art date
Application number
TW100133482A
Other languages
English (en)
Other versions
TW201314838A (zh
Inventor
Kuan Neng Chen
Sheng Yao Hsu
Original Assignee
Univ Nat Chiao Tung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Chiao Tung filed Critical Univ Nat Chiao Tung
Priority to TW100133482A priority Critical patent/TWI433268B/zh
Priority to US13/325,587 priority patent/US8508041B2/en
Priority to KR1020120011321A priority patent/KR101384131B1/ko
Publication of TW201314838A publication Critical patent/TW201314838A/zh
Application granted granted Critical
Publication of TWI433268B publication Critical patent/TWI433268B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16137—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H01L2224/81055—Composition of the atmosphere being oxidating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/8183—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

三維積體電路之接合方法及其三維積體電路
本發明是有關於一種三維積體電路之接合方法及其三維積體電路，特別是有關於一種可自動形成附著層、阻擋層及邊界保護層的三維積體電路之接合方法及其三維積體電路。
隨著科技與半導體技術的發展，科技產品也漸漸趨向小型化、多功能及輕薄化，而容置空間不斷縮小也使積體電路(Integrated Circuit，IC)的設計上更加具有挑戰性。以目前三維積體電路堆疊技術的發展而言，除了大幅縮小記憶體在電路板上所佔面積，提升電子產品縮小化的效率外，更能將不同功能晶片整合在同一構裝模組中，達到系統級封裝(System in Package，SiP)的效益。
習知應用於積體電路的接合方法，如美國專利公告第5334804號，係提出一種利用可導電的銅柱連結積體電路晶片及基板，然而此種方法製程繁複，製造上較具困難性，且較適合於後段封裝，無法應用於前段製程發展。又如S.TSUKIMOTO等人於2007年提出「Effect of Annealing Ambient on the Self-Formation Mechanism of Diffusion Barrier Layers Used in Cu(Ti)Interconnects」，可應用於銅導線，使其不易被氧化。然而，此方法僅適用於二維平面的接合，無法應用於維度的延伸，使得發展受到限制。
經由上述可知，習知技術具有製程繁雜、維度無法延伸，或只適用於傳統的製程方法，科技的發展受到限制等問題。因此，以需求來說，設計一個三維積體電路之接合方法及其三維積體電路，已成市場應用上之一個刻不容緩的議題。
有鑑於上述習知技藝之問題，本發明之目的就是在提供一種三維積體電路之接合方法及其三維積體電路，以解決先前技術費時、製程繁雜且限制維度延伸之問題。
根據本發明之目的，提出一種三維積體電路之接合方法，適用於製造一三維積體電路，其包含下列步驟：提供一第一積體電路及一第二積體電路，其分別包含一基板、一薄膜層及一金屬共鍍層，形成第一積體電路及第二積體電路係包含下列.步驟：提供一基板；沉積薄膜層於基板上；利用光源透過一光罩照射於薄膜層，以形成圖形結構；以及共鍍第一金屬及第二金屬於薄膜層上，以形成金屬共鍍層；以及在一設定溫度下，疊合第一積體電路於第二積體電路上，使得各金屬共鍍層互相接合，且第一金屬之至少一部份的原子向各金屬共鍍層間接合的介面擴散，以及第二金屬之至少一部分的原子向第一積體電路與第二積體電路之各薄膜層擴散，以形成用於第一金屬之一附著層及該阻擋層。
其中，附著層及阻擋層在第一金屬及薄膜層間提供穩定地一附著力，且防止第一金屬之原子擴散至薄膜層。
其中，設定溫度係介於200℃至400℃之間。
其中，疊合步驟係於大氣環境下執行。
其中，在金屬共鍍層邊緣之第二金屬之至少另一部份的原子與氧發生反應，從而形成一邊界保護層，以保護第一金屬不受氧化。
其中，第一金屬係為銅，第二金屬係為鈦。
根據本發明之目的，再提出一種三維積體電路，其包含：一第一積體電路及一第二積體電路。第一積體電路，係依序包含：一第一基板；一第一薄膜層形成於第一基板上，並形成一第一圖形結構於第一薄膜層上方；以及一第一金屬共鍍層設置於第一薄膜層上方，且具有一第一金屬及一第二金屬沉積於第一金屬共鍍層之中。第二積體電路，係依序包含：一第二基板；一第二薄膜層，係形成於第二基板上，並形成一第二圖形結構於第二薄膜層上方；以及一第二金屬共鍍層，係設置於第二薄膜層上方，且具有第一金屬及第二金屬沉積於第二金屬共鍍層之中。其中，第二積體電路在一設定溫度下疊合於第一積體電路上，使得第一金屬共鍍層及第二金屬共鍍層互相接合，且第一金屬之至少一部份的原子向第一金屬共鍍層與第二金屬共鍍層間接合的介面間擴散，以及第二金屬之至少一部分的原子向第一積體電路及第二積體電路各自之第一薄膜層與第二薄膜層間擴散，以形成用於第一金屬之附著層及阻擋層。
其中，附著層及該阻擋層在第一金屬及薄膜層間提供穩定地一附著力，且防止第一金屬之原子擴散至薄膜層。
其中，設定溫度係介於200℃至400℃之間。
其中，疊合步驟係於大氣環境下執行。
其中，在金屬共鍍層邊緣之第二金屬之至少另一部份的原子與氧發生反應，從而形成一邊界保護層，以保護第一金屬不受氧化。
其中，第一金屬係為銅，第二金屬係為鈦。
根據本發明之目的，更提出一種三維積體電路，其包含：一第一積體電路係依序包含第一基板、第一薄膜層及第一金屬共鍍層；以及一第二積體電路係依序包含第二金屬共鍍層、第二薄膜層及第二基板；其中，第一金屬共鍍層與第二金屬共鍍層係於一設定溫度相互接合，且第一薄膜層或第二薄膜層之表面係自動形成一附著層或一阻擋層，並第一金屬共鍍層或第二金屬共鍍層之表面係自動形成一邊界保護層。
其中，第一金屬共鍍層與第二金屬共鍍層係在設定溫度且大氣環境下相互接合。
其中，第一金屬共鍍層與第二金屬共鍍層係在設定溫度下於腔體中相互接合。
綜上所述，本發明之三維積體電路之接合方法及其三維積體電路，可克服先前技藝製程繁雜、維度無法延伸，造成科技的發展受到限制等問題，且藉由本發明之三維積體電路之接合方法及其三維積體電路可於一般大氣環境中進行高溫接合銅鈦之製程，且於接合時自動形成鈦 附著層、阻擋層及防銅氧化的氧化鈦之邊界保護層。進一步地，可簡化製造流程，直接形成具有銅鈦共鍍的結構，無需額外進行鈦附著層、銅種晶層或巨量銅層的濺鍍沉積。
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。
以下將參照相關圖式，說明依本發明之三維積體電路之接合方法及其三維積體電路之實施例，為使便於理解，下述實施例中之相同元件係以相同之符號標示來說明。
請參閱第1圖至第4圖，其係為本發明之三維積體電路之第一實施例之第一、第二、第三及第四示意圖。在本實施例中，第一基板11和第二基板21可為矽晶圓，其矽晶圓不限於任何尺寸或規格。第一薄膜層12或第二薄膜層22可為二氧化矽或其他薄膜材料。第一金屬與第二金屬可為金屬元素，第一金屬於本實施例較佳可為銅，第二金屬於本實施例較佳可為鈦，但不以此為限。如第1圖至第4圖所示，第一積體電路10依序可包含第一基板11、第一薄膜層12以及第一金屬共鍍層13。如第1圖所示，第一薄膜層12可設置於第一基板11上，且其厚度或材料可根據需求改變，在本實施例中，較佳可沉積1000nm的二氧化矽於第一基板11，可以作為第一薄膜層12。可利用一光源1照射於第一薄膜層12，透過光罩以形成一圖形結構。
進一步地，如第2圖所示，可以利用物理氣相沉積法於第一薄膜層12上方沉積第一金屬及第二金屬，以形成該第一金屬共鍍層13。第一金屬於本實施例較佳可為銅，第二金屬於本實施例較佳可為鈦，但不以此為限。如此一來，第一金屬共鍍層13可為銅鈦共鍍的結構，並形成第一積體電路10。
附帶一提的是，物理氣相沉積法是一種可利用高溫熱源將原料加熱至高溫，使其氣化或形成等離子體，然後在基體上冷卻凝聚成各種形態的材料，例如：單晶、薄膜或晶粒等。
接著，請一併參閱第2圖、第3圖及第4圖，第二積體電路20依序可包含第二金屬共鍍層23、第二薄膜層22及第二基板21，且第二積體電路20可於設定溫度下疊合於第一積體電路10上。值得注意的是，第一積體電路10的第一金屬共鍍層13及第二積體電路20的第二金屬共鍍層23在高溫過程中其接觸面互相接合。設定溫度較佳可為200℃至400℃。如圖所示，第一積體電路10與第二積體電路20可接合為三維積體電路。值得一提的是，在本實施例中，是將第一積體電路10與第二積體電路20作兩層的堆疊接合，然，其推疊的層數並不侷限於兩層，可以一層一層的堆疊上去，且每一層可任意改變其製程條件、製程中之金屬材料。
特別注意的是，在較佳可於溫度為200℃至400℃下，將第一積體電路10與第二積體電路20接合，並可於第一薄膜層12和第二薄膜層22的表面自動地形成附著層100或阻 擋層200。在本實施例中，第一金屬共鍍層13和第二金屬共鍍層23較佳可為銅鈦共鍍的結構，所以在溫度為200℃至400℃接合第一積體電路10與第二積體電路20時，銅原子會往介面擴散移動，而鈦原子會往二氧化矽的基板移動，而在二氧化矽的表面形成鈦的附著層100，以及防止銅擴散進入二氧化矽的阻擋層200。
同時，在溫度較佳可為200℃至400℃及在大氣環境下或在通少量氧氣的腔體內，將第一積體電路10與第二積體電路20接合，第一金屬共鍍層13與第二金屬共鍍層23的表面可自動形成一邊界保護層300。在本實施例中，鈦金屬傾向與大氣中的氧形成鈦的氧化物，使得部份的鈦會往邊界移動，而鈦的氧化物非常的緻密，故鈦的氧化物一旦形成，氧便無法擴散進入銅鈦共鍍的結構中。換句話說，此一擴散作用進一步可防止銅進行氧化反應。
順帶一提的是，在本發明所屬領域中具有通常知識者應當明瞭，於前面敘述方式之材質和各層疊合之實施態樣僅為舉例而非限制。
依據第一實施例，本發明更提出第二實施例作更進一步之舉例說明。
請參閱第5圖，其係為本發明之三維積體電路之第二實施例之示意圖。在本實施例中，第一基板11和第三基板31可為矽晶圓，其矽晶圓不限於任何尺寸或規格。第一薄膜層12或第三薄膜層32可為二氧化矽或其他薄膜材料。第一金屬與第二金屬可為金屬元素，第一金屬於本實施 例較佳可為銅，第二金屬於本實施例較佳可為鈦，但不以此為限。如圖所示，第一積體電路依序可包含第一基板11、第一薄膜層12以及第一金屬共鍍層13。第一薄膜層12可設置於第一基板11上，且其厚度或材料可根據需求改變，在本實施例中，較佳可沉積1000nm的二氧化矽於第一基板11，可以作為第一薄膜層12。利用一光源照射於第一薄膜層12，可透過光罩以形成一圖形結構。
更進一步地，可以利用物理氣相沉積法於第一薄膜層12上方沉積第一金屬及第二金屬，以形成該第一金屬共鍍層13。第一金屬於本實施例較佳可為銅，第二金屬於本實施例較佳可為鈦，但不以此為限。如此一來，第一金屬共鍍層13可為銅鈦共鍍的結構，並形成第一積體電路10。同時，第三積體電路40可以與第一積體電路10一般，具有相同的堆疊和製造方法來形成第三積體電路40，第三積體電路40依序可包含第三基板31、第三薄膜層32及第三金屬共鍍層33。第一積體電路10於一設定溫度下可貼合於第三積體電路40的一側，其溫度較佳可為200℃至400℃。如圖所示，在本實施例中，是將第一積體電路10與第三積體電路40左右貼合以作為接合，然，排列之位置並不以此為限。
儘管前述在說明本發明之三維積體電路之接合方法及其三維積體電路的過程中，亦已同時說明本發明之三維積體電路之接合方法的概念，但為求清楚起見，以下仍另繪示流程圖詳細說明。
請參閱第6圖，其係為本發明之三維積體電路之接合方法 流程圖，如圖所示，本發明之三維積體電路之接合方法，其適用於製造一三維積體電路，其三維積體電路包含一第一積體電路及一第二積體電路。第一積體電路依序包含一第一基板、一第一薄膜層及一第一金屬共鍍層，第二積體電路係依序包含一第二金屬共鍍層、一第二薄膜層及一第二基板。三維積體電路之接合方法包含下列步驟：
在步驟S11中，提供一基板。
在步驟S12中，沉積薄膜層於基板上。
在步驟S13中，利用光源照射於薄膜層，以形成圖形結構。
在步驟S14中，藉由第一金屬及第二金屬共鍍於薄膜層上，以形成金屬共鍍層。
在步驟S15中，提供依序具有基板、薄膜層及金屬共鍍層之第一積體電路。
在步驟S16中，提供依序具有金屬共鍍層、薄膜層及基板之第二積體電路。
在步驟S17中，透過一設定溫度、於大氣環境下或通入少量氧氣的腔體中，將第一積體電路與第二積體電路接合。
本發明之三維積體電路之接合方法的詳細說明以及實施方式已於前面敘述本發明之三維積體電路之接合方法及其三維積體電路時描述過，在此為了簡略說明便不再敘 述。
綜上所述，依本發明之三維積體電路之接合方法及其三維積體電路，其可具有一或多個下述優點：
(1)此發明克服先前技藝製程繁雜、維度無法延伸，造成科技的發展受到限制等問題。
(2)此發明之三維積體電路之接合方法及其三維積體電路可於大氣環境中進行高溫接合銅鈦之製程，且於接合時自動形成鈦附著層、阻擋層及防銅氧化的氧化鈦之邊界保護層。
(3)此發明之三維積體電路之接合方法及其三維積體電路可簡化製造流程，直接形成具有銅鈦共鍍的結構，無需額外進行鈦附著層、銅種晶層或巨量銅層的濺鍍沉積。
雖然前述的描述及圖示已揭示本發明之較佳實施例，必須瞭解到各種增添、許多修改和取代可能使用於本發明較佳實施例，而不會脫離如所附申請專利範圍所界定的本發明原理之精神及範圍。熟悉該技藝者將可體會本發明可能使用於很多形式、結構、佈置、比例、材料、元件和組件的修改。
因此，本文於此所揭示的實施例於所有觀點，應被視為用以說明本發明，而非用以限制本發明。本發明的範圍應由後附申請專利範圍所界定，並涵蓋其合法均等物，並不限於先前的描述。
1‧‧‧光源
10‧‧‧第一積體電路
11‧‧‧第一基板
12‧‧‧第一薄膜層
13‧‧‧第一金屬共鍍層
20‧‧‧第二積體電路
21‧‧‧第二基板
22‧‧‧第二薄膜層
23‧‧‧第二金屬共鍍層
31‧‧‧第三基板
32‧‧‧第三薄膜層
33‧‧‧第三金屬共鍍層
40‧‧‧第三積體電路
100‧‧‧附著層
200‧‧‧阻擋層
300‧‧‧邊界保護層
S11~S17‧‧‧步驟流程
第1圖 係為本發明之三維積體電路之第一實施例之第一示意圖；第2圖 係為本發明之三維積體電路之第一實施例之第二示意圖；第3圖 係為本發明之三維積體電路之第一實施例之第三示意圖；第4圖 係為本發明之三維積體電路之第一實施例之第四示意圖；第5圖 係為本發明之三維積體電路之第二實施例之示意圖；以及第6圖 係為本發明之三維積體電路之接合方法流程圖。
11‧‧‧第一基板
12‧‧‧第一薄膜層
13‧‧‧第一金屬共鍍層
21‧‧‧第二基板
22‧‧‧第二薄膜層
23‧‧‧第二金屬共鍍層
100‧‧‧附著層
200‧‧‧阻擋層
300‧‧‧邊界保護層

Claims (15)

  1. 一種三維積體電路之接合方法，適用於製造一三維積體電路，該三維積體電路之接合方法包含下列步驟：提供一第一積體電路及一第二積體電路，其分別依序具有一基板、一薄膜層及一金屬共鍍層，形成該第一積體電路及該第二積體電路係各自包含下列步驟：提供該基板；沉積該薄膜層於該基板上；利用一光源透過一光罩照射於該薄膜層，以形成一圖形結構；以及共鍍一第一金屬及一第二金屬於該薄膜層上，以形成該金屬共鍍層；以及在一設定溫度下，疊合該第一積體電路於該第二積體電路上，使得各該金屬共鍍層互相接合，且該第一金屬之至少一部份的原子向各該金屬共鍍層間接合的介面擴散，以及該第二金屬之至少一部分的原子向該第一積體電路與該第二積體電路之各該薄膜層擴散，以形成用於該第一金屬之一附著層及一阻擋層。
  2. 如申請專利範圍第1項所述之三維積體電路之接合方法，其中該附著層及該阻擋層在該第一金屬及該薄膜層間提供穩定地一附著力，且防止該第一金屬之原子擴散至該薄膜層。
  3. 如申請專利範圍第1項所述之三維積體電路之接合方法，其中該設定溫度係介於200℃至400℃之間。
  4. 如申請專利範圍第1項所述之三維積體電路之接合方法， 其中該疊合步驟係於大氣環境下執行。
  5. 如申請專利範圍第1項所述之三維積體電路之接合方法，其中在該金屬共鍍層邊緣之該第二金屬之至少另一部份的原子與氧發生反應，從而形成一邊界保護層，以保護該第一金屬不受氧化。
  6. 如申請專利範圍第5項所述之三維積體電路之接合方法，其中該第一金屬係為銅，該第二金屬係為鈦。
  7. 一種三維積體電路，其包含：一第一積體電路，係包含：一第一基板；一第一薄膜層，係形成於該第一基板上，並形成一第一圖形結構於該第一薄膜層上方；以及一第一金屬共鍍層，係設置於該第一薄膜層上方，且具有一第一金屬及一第二金屬沉積於該第一金屬共鍍層之中；以及一第二積體電路，其包含：一第二基板；一第二薄膜層，係形成於該第二基板上，並形成一第二圖形結構於該第二薄膜層上方；以及一第二金屬共鍍層，係設置於該第二薄膜層上方，且具有該第一金屬及該第二金屬沉積於該第二金屬共鍍層之中；其中，該第二積體電路係在一設定溫度下疊合於該第一積體電路上，使得該第一金屬共鍍層及該第二金屬共鍍層互相接合，且該第一金屬之至少一部份的原子向該第一金屬共鍍層與該第二金屬共鍍層間接合的介面擴散，以及該第二金屬之至少一部分的原子向該第一積體電路與該第二積 體電路各自之該第一薄膜層與該第二薄膜層擴散，以形成用於該第一金屬之一附著層及一阻擋層。
  8. 如申請專利範圍第7項所述之三維積體電路之接合方法，其中該附著層及該阻擋層在該第一金屬及該第一薄膜層與該第二薄膜層間提供穩定地一附著力，且防止該第一金屬之原子擴散至該第一薄膜層與該第二薄膜層。
  9. 如申請專利範圍第7項所述之三維積體電路之接合方法，其中該設定溫度係介於200℃至4()0℃之間。
  10. 如申請專利範圍第7項所述之三維積體電路之接合方法，其中該疊合步驟係於大氣環境下執行。
  11. 如申請專利範圍第7項所述之三維積體電路之接合方法，其中在該金屬共鍍層邊緣之該第二金屬之至少另一部份的原子與氧發生反應，從而形成一邊界保護層，以保護該第一金屬不受氧化。
  12. 如申請專利範圍第11項所述之三維積體電路之接合方法，其中該第一金屬係為銅，該第二金屬係為鈦。
  13. 一種三維積體電路，其包含：一第一積體電路，係依序包含一第一基板、一第一薄膜層及一第一金屬共鍍層；以及一第二積體電路，係依序包含一第二金屬共鍍層、一第二薄膜層及一第二基板；其中，該第一金屬共鍍層與該第二金屬共鍍層係在一設定溫度下相互接合，且該第一薄膜層或該第二薄膜層之表面係自動形成一附著層及一阻擋層，並該第一金屬共鍍層或該第二金屬共鍍層之表面係自動形成一邊界保護層。
  14. 如申請專利範圍第13項所述之三維積體電路，其中該第一 金屬共鍍層與該第二金屬共鍍層係在該設定溫度且大氣環境下相互接合。
  15. 如申請專利範圍第13項所述之三維積體電路，其中該第一金屬共鍍層與該第二金屬共鍍層係在該設定溫度下於一腔體中相互接合。
TW100133482A 2011-09-16 2011-09-16 三維積體電路之接合方法及其三維積體電路 TWI433268B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW100133482A TWI433268B (zh) 2011-09-16 2011-09-16 三維積體電路之接合方法及其三維積體電路
US13/325,587 US8508041B2 (en) 2011-09-16 2011-12-14 Bonding method for three-dimensional integrated circuit and three-dimensional integrated circuit thereof
KR1020120011321A KR101384131B1 (ko) 2011-09-16 2012-02-03 3차원 집적 회로의 접합 방법 및 3차원 집적 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100133482A TWI433268B (zh) 2011-09-16 2011-09-16 三維積體電路之接合方法及其三維積體電路

Publications (2)

Publication Number Publication Date
TW201314838A TW201314838A (zh) 2013-04-01
TWI433268B true TWI433268B (zh) 2014-04-01

Family

ID=47879922

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100133482A TWI433268B (zh) 2011-09-16 2011-09-16 三維積體電路之接合方法及其三維積體電路

Country Status (3)

Country Link
US (1) US8508041B2 (zh)
KR (1) KR101384131B1 (zh)
TW (1) TWI433268B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465428B (zh) * 2013-09-16 2017-10-13 中国科学院上海微系统与信息技术研究所 一种铜‑铜金属热压键合的方法
CN113718206B (zh) * 2021-08-23 2023-03-07 中山市气相科技有限公司 一种具有三明治结构的TaTiN多层薄膜的制备方法以及薄膜

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334804A (en) 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US6191468B1 (en) * 1999-02-03 2001-02-20 Micron Technology, Inc. Inductor with magnetic material layers
US6844253B2 (en) * 1999-02-19 2005-01-18 Micron Technology, Inc. Selective deposition of solder ball contacts
US6890829B2 (en) * 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US7402509B2 (en) * 2005-03-16 2008-07-22 Intel Corporation Method of forming self-passivating interconnects and resulting devices
US7932590B2 (en) * 2006-07-13 2011-04-26 Atmel Corporation Stacked-die electronics package with planar and three-dimensional inductor elements

Also Published As

Publication number Publication date
KR101384131B1 (ko) 2014-04-10
US8508041B2 (en) 2013-08-13
TW201314838A (zh) 2013-04-01
KR20130030182A (ko) 2013-03-26
US20130069248A1 (en) 2013-03-21

Similar Documents

Publication Publication Date Title
US10354972B2 (en) Hybrid bonding systems and methods for semiconductor wafers
TWI362710B (en) Method for forming metal electrode of system in package
US8377565B2 (en) Filling material and filling method using the same
TWI523189B (zh) 層疊封裝裝置的形成方法
TW200826253A (en) Hybrid structure of multi-layer substrates and manufacture method thereof
TW200741919A (en) Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication
JP2012216773A5 (zh)
CN104465582A (zh) 半导体装置及半导体装置的生产方法
US8381964B2 (en) Tin-silver bonding and method thereof
JP2013077711A5 (zh)
JP2009038358A5 (zh)
JP2008543049A5 (zh)
TWI433268B (zh) 三維積體電路之接合方法及其三維積體電路
TW200935579A (en) Stacked chip structure and fabrication method thereof
US9024453B2 (en) Functional material systems and processes for package-level interconnects
JP2006269607A5 (zh)
CN104465428A (zh) 一种铜-铜金属热压键合的方法
JP2003347522A5 (zh)
TWI241666B (en) Chip structure, wafer structure and fabricating method of wafer protecting layer
JP2019114607A (ja) 半導体装置およびその製造方法
Huang et al. Novel copper metallization schemes on ultra-thin, bare glass interposers with through-vias
Wang et al. Self-aligned flat ultra-thin chip package for flexible circuits
TWI486107B (zh) 用於晶片封裝件之基板的製造方法
JP2010147051A5 (zh)
TW200933770A (en) Fabrication method of UBM layers

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees