CN102883991A - 灵敏的微米系统和纳米系统的连接方法 - Google Patents

灵敏的微米系统和纳米系统的连接方法 Download PDF

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CN102883991A
CN102883991A CN2011800107910A CN201180010791A CN102883991A CN 102883991 A CN102883991 A CN 102883991A CN 2011800107910 A CN2011800107910 A CN 2011800107910A CN 201180010791 A CN201180010791 A CN 201180010791A CN 102883991 A CN102883991 A CN 102883991A
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metal
wafer
bonding pressure
temperature
connection
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CN102883991B (zh
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尼尔斯·霍伊维克
伯杰尔·斯塔克
安德斯·艾尔芬
王凯英
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Sensonor Technologies AS
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
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Abstract

一种金属内扩散连接方法，用于形成MEMS装置的气密密封的晶片级封装，包括下列步骤：在第一晶片和第二晶片的表面上提供第一金属堆，第一金属在空气中易氧化；在每一个第一金属堆的上表面上提供第二金属层，第二金属具有比第一金属低的熔点，所述第二金属层的厚度足以抑制所述第一金属上表面的氧化；使所述第一晶片上的第二金属层接触第二晶片上的第二金属层以形成连接界面；以及在低于所述第二金属的熔点的连接温度向第一和第二晶片施加连接压力以促使连接，所述连接压力足以使连接界面处的第二金属层变形。

Description

灵敏的微米系统和纳米系统的连接方法
技术领域
本发明涉及一种连接微米结构和纳米结构的内扩散方法，特别地，涉及一种通常以晶片级实施的灵敏的和易碎的结构或部件的3D集成及封装方法。
背景技术
研发诸如微米或纳米机电系统（MEMS）和基于MEMS的装置时的难题是所有的MEMS装置都需要特别设计的封装以便气密密封和/或保护其内灵敏的和精密的部件。特别地，一些种类的MEMS装置在封装中需要非常低的真空级，然而其它一些则需要特别的压力和/或气体混合物以便根据具体的设计和目的来操作。
US7132721教导了一种连接方法，其中在第一晶片表面沉积第一材料，在第二晶片表面沉积第二材料，将两个晶片表面压在一起以实现连接，其中第一和第二材料之间的内扩散形成合金化合物，该合金化合物随后将晶片固定在一起。
但是，这种方法或类似方法的一个问题是每个晶片上沉积不同材料将增加每个晶片的连接表面的不规则和不均匀性，从而影响所有合成连接的质量。此外，如果沉积的材料是在空气中易氧化的，则在连接表面可能形成天然氧化物，这将减少湿润并成为阻止当晶片和芯片上或晶片对上的连接表面开始接触时第一和第二材料之间的混合的障碍物。
预处理通常包括熔化程序（flux procedure），优选地，系统组装期间在原位而不是在非原位执行所述熔化程序以阻止氧化，这是因为在非原位氧化发生的非常快。通常用于这种程序的化学制品的一些例子是盐酸、硫酸、蒸汽状的甲酸，或合成气体。但是，虽然这些酸是有效的氧化物去除剂，然而正如人们所熟知的，它们对于灵敏的微米结构或纳米结构具有非常大的负面影响。特别地，如前所述的通常包括在液态酸或类似物中处理晶片的任何湿润处理，如果不需要额外的笨重处理技术，其与释放的和易碎的微米或纳米结构不相适应。
此外，大多数简单的表面处理程序在第二材料的熔点温度附近是非常有效的。因此，在原位预处理之后，例如在上述熔化处理之后，在已经相对较高温度的压力下，第一和第二材料通常开始接触，所述相对较高温度随后上升超出第二材料的熔点温度。这可能使得大体积的第二材料突然熔化，导致第二材料不希望的挤压并流向周围，这将反过来造成电短路或损坏该微米或纳米装置。此外，存在这样一种危险，即在连接处理结束时，任何未反应的第二材料在诸如吸气剂活化或无铅焊接的后续处理的高温期间将再次熔化。
因此，在包括诸如MEMS构件、薄膜金属导体或绝缘体的精密结构的任何连接处理期间，通常难于执行任何表面处理以去除氧化层而不潜在地损坏这些精密结构。
另一种已知的内扩散连接方法是固液内扩散（SLID）技术，该技术起源于用于3D微系统集成的芯片到晶片方法。这种技术的典型实施包括具有第一金属的芯片，所述第一金属在空气中易氧化并具有设置于其上的第二金属层，其中第一金属具有比第二金属高的熔点。一个例子是Cu-Sn SLID连接，其中Cu在空气中易氧化并具有比Sn高的多的熔点。
但是，现有的芯片到晶片方法的SLID连接存在多个与之相关的问题。作为例子，其中芯片单独地固定于晶片上，所使用的并且可以固定晶片的典型的最大连接温度超出第二金属的熔点。这将阻止第一和第二金属存在于晶片表面上，因为在所有模件被组装之前，第一金属在第二金属中的扩散将导致化合物沿着所有连接表面形成，这是不希望的。因此，当第一和第二金属都沉积在芯片表面上时只有第一金属沉积在晶片表面上。
US6872464中描述的另一种可替换的芯片到晶片的连接方法基于高温回流之前的低温组装。但是，这种方法包括利用基于热塑聚合体的焊接媒介实现的低温预连接。类似地，US2006/0292824教导了一种模件到晶片的连接方法，其中聚合连接层被图案化于设置在第一晶片上的模件周围并且这种聚合体在连接过程期间硬化以提供永久胶合层，这种永久胶合层在粘结压力释放之后固定模件-晶片连接。
但是，这两种方法的哪一个都不适于形成气密密封的MEMS封装，因为随着时间的逝去，聚合体将恶化（渗气）并且分子将分散进入封装的密封真空腔中的环境中，从而危及真空水平。
发明内容
本发明的一个方面是提供一种在晶片级形成用于包封MEMS装置的气密密封封装的连接方法，特别地，适于诸如微测辐射热计的化学灵敏的MEMS装置。
根据本发明，提供一种用于形成MEMS装置的气密密封的晶片级封装的金属内扩散连接方法，包括步骤：在第一晶片和第二晶片表面上提供第一金属堆，第一金属在空气中易氧化；在每一个第一金属堆的上表面上提供第二金属层，第二金属具有比第一金属更低的熔点，所述第二金属层的厚度足以抑制第一金属上表面的氧化；使第一晶片上的第二金属层接触第二晶片上的第二金属层以形成连接界面；以及在低于第二金属的熔点的连接温度施加连接压力到第一和第二晶片以促使连接，所述连接压力足以使连接界面处的第二金属层变形。
因此，本发明提供的连接方法使得晶片间的金属连接能够包封可以用于多种应用、需要气密密封以及具有或不具有真空腔的具有精密或化学灵敏的部件的装置。利用本发明的方法，可以在不能抵抗住通常需要去除表面氧化物或阻止连接表面的氧化的熔化程序或其它表面预处理的晶片上以晶片级执行连接和3D集成。因此，精密的或化学灵敏的部件或装置能够设置在两个晶片上以便连接。
这是因为具有比第一金属低的熔点的第二金属充当将被连接在一起的两个晶片上的第一金属的保护层，以阻止第一金属表面的氧化。这使得所制造的连接搭档比具有暴露的易于氧化的第一金属表面的样品具有较长的存储周期。
更特别地，没有充当保护层的第二金属，天然氧化将很快覆盖第一金属的暴露表面，这对阻止湿润和在连接处理期间的两种金属的内扩散具有负面影响，并且因此需要蚀刻移除或利用还原处理，这将潜在地损坏精密部件。
此外，由于连接压力足够大以使连接界面处的第二金属层表面变形，这对于移除任一层上的任何表面凹凸以获得非常好的、均匀的连接界面是有效的。同样，由于连接表面为相同金属，因而可以增强连接表面的湿润条件。
此外，使晶片以相对于第二金属的熔点较低的温度接触，提供在较早处理阶段整个晶片堆的更均匀的温度分布，因为两个晶片以调节连接夹头的温度热接触。
本发明的进一步优点是在第二金属的熔点之下形成最多的金属互化物，与现有的SLID方法相比，这减少了液态材料在连接过程期间存在的空间。
本发明提供了一种不用熔剂的连接方法，其同样不需要诸如预退火的任何其它表面预处理或焊接媒介的使用，并因此，特别是在它们被释放且没有支撑之后，适于精密的微米和纳米级别的机电装置，薄膜金属导体或绝缘体表面。
附图说明
现在，将参考附图描述本发明的例子，其中：
图1示出根据本发明所准备的在连接之前的两个晶片；
图2a示出图1中的晶片刚开始接触在一起；
图2b是与图2a中的连接处理阶段有关的时间对温度的曲线图；
图3a示出当温度上升时形成在两个表面之间的内扩散连接区域；
图3b是与图3a中的连接处理阶段有关的时间对温度的曲线图；
图4a示出在连接形成之后的最终化合物构成；
图4b是与图4a中的连接处理阶段有关的时间对温度的曲线图；
图5a利用本发明的方法施加大约10MPa连接压力连接的两个晶片之间的连接界面；以及
图5b利用本发明的方法施加大约17MPa连接压力接合的两个晶片之间的连接界面。
具体实施方式
虽然在本发明的例子中，第一金属是铜（Cu）且第二金属是锡（Sn），然而本领域技术人员可以理解的是可以使用其它合适金属的组合，其中具有较高熔点的金属在空气中氧化以形成厚的天然氧化物，可以使用例如但不限于银（Ag）或镍（Ni）。此外，虽然在此论述的例子是硅晶片或基板，但是可以意识到晶片或基板可以包括其它材料，例如但不限于锗、玻璃、石英、SiC和/或Ⅲ-Ⅴ族半导体。
在Si晶片的例子中，通常具有1-10μm之间范围内厚度的Cu堆3图案化于第一晶片1的表面上。然后将Sn层4沉积于Cu堆3的顶部上，如图1所示。如上所述，Sn层4足够厚以阻止Cu堆3表面的氧化并且在第一晶片1开始结合相应的第二晶片2的同时确保保留一定量未反应的Sn。在本例中，Sn层4具有大于0.5μm的厚度，并且为了完成内扩散过程，Cu与Sn的比必须大于1.3以便保证在固化连接中完全转变成合成的Cu3Sn化合物7。
除了形成部分最终的金属化合物之外，Sn还保护Cu免于氧化以便晶片1、2能够储存渡过沉积和组装过程之间长的时间周期。
在这一特殊例子中，沉积在第一晶片1的表面上的Cu和Sn图案限定已经被形成在表中的凹槽5周围的边界。可以施加吸气剂材料或其它化学灵敏材料（未示出）于第一晶片1的凹槽5中和/或第二晶片2上。优选地，Cu和Sn也可以以与沉积在第一晶片1上的Cu堆3和Sn层4具有相同的厚度和横向几何形状的相似构造沉积于第二晶片2上，但这不是必须的。
为了说明，所示的第二晶片2具有设置于其上的多个精密部件8。这种精密部件8经常是化学灵敏的并且，当然，可以设置在第一晶片1和/或第二晶片2上，这取决于所获结构的期望目的。
例如，沉积可以利用起始于适当种子层的电喷镀或非电喷镀方式实施，或者以本领域熟知的任何其它沉积方法实施。
图2a示出第一和第二晶片1、2开始连接处理，它们通过施加于第一晶片1上（假设第二晶片2放置在固体表面上）的连接力F开始接触。在Sn的熔点温度以下执行处理的开始步骤，如图2b中所示的“温度与时间”曲线图中所示。有利地，与现有的SLID方法相比，这一开始步骤可以以相对低的温度实施，如果需要，甚至可以在室温下实施。但是，晶片结合在一起的温度取决于最后所获连接结构的期望特性，所述期望特征由其诸如真空包封或气密密封的使用目的所决定，这是本领域技术人员能够理解的。
图3a示出了示范性过程的另一步骤，其中当第一和第二晶片1、2开始接触时，Sn层4在连接力F产生的压力下被挤压在一起并且在Sn-Sn界面之间容易产生亲密的金属接触。可以从图3b看出，虽然能够看出温度在开始连接之后开始升高，但是，处理的这一步骤同样是在Sn的熔点温度以下发生。连接力F产生的压力导致Sn变形，破碎通常形成在Sn上的任何薄的氧化物层并且消除表面凹凸。通过使用超声能量，这种变形可以进一步增强。
热加速内部原子扩散并因此形成Sn-Sn连接。热同样加速每一个Cu堆3上的Cu-Sn界面处金属间化合物6的形成以致当Sn的熔点温度（大约232℃）被超过时，只有少量的纯Sn层4留在Cu堆3之间，如果有的话，这取决于温度分布和金属厚度。当具有多余的Cu时，在150℃温度下由Cu6Sn5组成的金属间化合物6逐渐转变成更高温度下的Cu3Sn。
图4a示出在处理结束时所获的结构，由CuxSny合金化合物7连接第一和第二晶片1、2。虽然CuxSny合金化合物7优选是Cu3Sn，但是CuxSny合金化合物的组成取决于Cu-Sn界面在处理期间的温度。从图4b的曲线图所示的温度分布可以看出，在本例中，连接处理以超过Sn熔点的温度完成。温度分布必须被调整以确保所有Sn4被转化成期望的CuxSny合金化合物。
在本例中，温度在整个过程中按常量增加。但是，温度也可以不是按常量增加，并且可以在Sn熔点之下及之上变化。这种变化对于控制连接是有益的。但是，如上所述，利用本方法能够实现好的中间金属Sn-Sn连接并且利用在到达其熔点之前的适当温度分布同时能减少留在连接界面处的未反应Sn的剩余量。
因此，本发明能够被认为是固态方法，其中能够形成金属间化合物6和/或所获得的CuxSny合金化合物7阶段而不必依赖于纯Sn层4的液化，因为Cu6Sn5和Cu3Sn阶段都具有高于Sn熔化温度和最大粘结温度的熔点。取决于如何设置本方法，液态Sn阶段可能完全不存在，或者可能被限制在Sn-Sn界面附近非常窄的区域。
当第一和第二晶片接合时，施加到它们上的连接力必须足够高以允许形成两个晶片1、2的匹配表面的Sn层4亲密接触以便横跨晶片1、2的任何非均匀性可由易延展的Sn吸收。
相对于现有技术，两个匹配表面上的Sn层4能进一步提高全部Sn的厚度均匀性。通过利用晶片1、2其中一个上的改进设计，也能够补偿另一晶片1、2上的非均匀性。例如，这可能包括在两个晶片1、2上反映单独的虚拟结构。
当晶片组装时施加于其上的连接力应该足够高以提供大于0.05MPa的连接压力，更优选地，在5MPa-50MPa的范围内，以便易延展的Sn吸收横跨连接表面的任何非均匀性。实际上，已经发现在15MPa到25MPa范围内的连接压力适于降低任何表面凹凸的影响并产生良好的和均匀的连接线。
图5a示出根据本发明的利用大约10MPa的连接压力在较低的温度连接的封装的横截面。可以看出，在这种连接压力下，Sn 3的表面已经变形以提供好的连接界面，尽管仍可看见少数的空隙9。图5b示出在17MPa下连接的封装的横截面，这在优选的大约15MPa到大约25MPa的压力范围内。本例中可以看出，Sn 3的表面已经变形足以提供完全平滑的连接界面，从而消除所有空隙9。
在上述例子中，从图3a和3b中可以看出，选择温度分布以便Cu和Sn明显的内扩散在Sn的熔点232℃以下发生。当达到Sn的熔点时，这种方法容易具有非常少的未反应的Sn保留在Sn-Sn界面处（如果有的话）。因此，由于在连接过程期间存在，存在非常有限的熔融材料，从而有效地最小化熔融Sn的任何未受控的流出。图4a和4b示出在Sn的熔点以上连接形成获得的CuxSny 7。如上所述，所获结构的不同应用目的可能需要不同CuxSny的组成。
有利地，所述结构在其形成期间不需要长时间保持在Sn的熔化温度以上，因为大多数内扩散过程已经在较低温度发生。
通过在温度上升期间于晶片1、2施加大的粘结力F，横跨晶片1、2的任何厚度非均匀性在处理期间将被易延展的Sn吸收。
在本发明的另一例子中，CuSn连接结构能够用于3D互联。通过两个晶片上Cu堆和Sn层构造的沉积可以执行晶片级的少熔化组装，类似如上所述。在本例中，结构被设计成单独接触。在更进一步的例子中，通过允许232℃以下的Cu-Sn/Sn-Cu内扩散，也可以最小化Sn流动。
上述两个例子都适于利用传统的晶片级处理大批量生产，并且此外，可以在相同晶片上结合在一起。
有利地，具有较低熔点的第二金属（例如Sn）的连接表面都不需要在连接之前或连接期间熔化处理。此外，当与需要熔化的现有方法相比，通过调整温度分布和力将晶片接合在一起时，利用少熔化处理能够完成晶片级的气密密封并且可以最优化连接参数以限制Sn流。
虽然上述给定的例子适于晶片级连接，然而本领域技术人员能够意识到相同原理可以用于灵敏的和精密的部件的芯片级连接，所述灵敏的和精密的部件可能被利用在连接之前需要预处理连接表面的方法损坏。
因此，本发明提供适于以晶片级连接可能包括易碎部件的灵敏结构的SLID型连接方法而不需要对分开的晶片进行所需的任何预处理。

Claims (14)

1.一种金属内扩散连接方法，用于形成MEMS装置的气密密封的晶片级封装，包括下列步骤：
在第一晶片和第二晶片的表面上提供第一金属堆，第一金属在空气中易氧化；
在每一个第一金属堆的上表面上提供第二金属层，第二金属具有比所述第一金属更低的熔点，所述第二金属层厚度足以抑制第一金属的上表面的氧化；
使所述第一晶片上的第二金属层接触所述第二晶片上的所述第二金属层以形成连接界面；以及
在低于所述第二金属的熔点的连接温度向所述第一和第二晶片施加连接压力以促使连接，所述连接压力足以使所述连接界面处的所述第二金属层变形。
2.根据权利要求1所述的方法，还包括将所述连接温度提高到所述第二金属的熔点以形成将所述第一和第二晶片连接在一起的金属间化合物。
3.根据权利要求1或2所述的方法，其中所述第一金属是铜而第二金属是锡。
4.根据权利要求1到3中任一项所述的方法，其中当施加所述连接压力时，所述连接温度按常量增加。
5.根据权利要求1到3中任一项所述的方法，其中当施加所述连接压力时，所述连接温度以非常量方式增加。
6.根据上述任一权利要求所述的方法，其中当施加所述连接压力时，所述连接温度不超过所述第二金属的熔点。
7.根据上述任一权利要求所述的方法，其中所述连接压力大于0.05MPa。
8.根据权利要求7所述的方法，其中所述连接压力在5MPa和50MPa之间。
9.根据权利要求7所述的方法，其中所述连接压力在15MPa和25MPa之间。
10.根据上述任一权利要求所述的方法，其中包括力、温度和声能中的一个或多个连接参数在连接处理期间是可控制的以改变在连接界面实现的内扩散。
11.一种气密密封结构，包括通过金属间化合物连接在一起的第一晶片和第二晶片，所述金属间化合物利用上述任一权利要求所述的方法形成，其中所述金属间化合物具有金属间连接界面。
12.根据权利要求11所述的气密密封结构，其中所述结构包括MEMS装置、吸气剂材料或化学灵敏材料。
13.根据权利要求12所述的气密密封结构，其中所述MEMS装置是化学灵敏的。
14.多个根据权利要求11到13的任一项所述的气密密封结构，其中所述多个气密密封结构以晶片级形成。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103434998A (zh) * 2013-08-29 2013-12-11 上海宏力半导体制造有限公司 晶圆级气密性的测试结构及测试方法
CN105358473A (zh) * 2013-07-11 2016-02-24 雷神公司 用作真空吸气剂的晶片级封装焊料阻挡物
CN105517947A (zh) * 2013-09-13 2016-04-20 Ev集团E·索尔纳有限责任公司 用于施加接合层的方法
CN105826243A (zh) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 晶圆键合方法以及晶圆键合结构

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5588419B2 (ja) * 2011-10-26 2014-09-10 株式会社東芝 パッケージ
FR3008690B1 (fr) * 2013-07-22 2016-12-23 Commissariat Energie Atomique Dispositif comportant un canal fluidique muni d'au moins un systeme micro ou nanoelectronique et procede de realisation d'un tel dispositif
US11094661B2 (en) * 2015-11-16 2021-08-17 Kabushiki Kaisha Toyota Chuo Kenkyusho Bonded structure and method of manufacturing the same
US9865565B2 (en) * 2015-12-08 2018-01-09 Amkor Technology, Inc. Transient interface gradient bonding for metal bonds
US11470727B2 (en) * 2016-10-24 2022-10-11 Jaguar Land Rover Limited Apparatus and method relating to electrochemical migration
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
RU2662061C1 (ru) * 2017-10-25 2018-07-23 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" Способ герметизации мэмс устройств
CN111792621B (zh) * 2020-07-06 2024-04-16 中国科学院上海微系统与信息技术研究所 一种圆片级薄膜封装方法及封装器件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0365807B1 (en) * 1988-10-12 1993-12-22 International Business Machines Corporation Bonding of metallic surfaces
DE19531158A1 (de) * 1995-08-24 1997-02-27 Daimler Benz Ag Verfahren zur Erzeugung einer temperaturstabilen Verbindung
US20020090756A1 (en) * 2000-10-04 2002-07-11 Masamoto Tago Semiconductor device and method of manufacturing the same
US20060292824A1 (en) * 2005-06-08 2006-12-28 Eric Beyne Methods for bonding and micro-electronic devices produced according to such methods
US7276789B1 (en) * 1999-10-12 2007-10-02 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
CN101120444A (zh) * 2005-03-16 2008-02-06 英特尔公司 形成自钝化互连的方法以及所得到的装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821161A (en) * 1997-05-01 1998-10-13 International Business Machines Corporation Cast metal seal for semiconductor substrates and process thereof
EP0951068A1 (en) * 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
EP1337376B1 (de) 2000-09-07 2005-10-12 Infineon Technologies AG Lotmittel zur verwendung bei diffusionslotprozessen
US6667225B2 (en) * 2001-12-17 2003-12-23 Intel Corporation Wafer-bonding using solder and method of making the same
RU2219027C2 (ru) * 2002-01-15 2003-12-20 Общество с ограниченной ответственностью "Амалгамэйтед Технологическая группа" Способ изготовления неразъемного соединения двух тел, выполненных из разнородных металлов, и неразъемное соединение, получаемое этим способом
US6793829B2 (en) 2002-02-27 2004-09-21 Honeywell International Inc. Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices
AU2003264717A1 (en) * 2002-08-16 2004-03-03 New Transducers Limited Method of bonding a piezoelectric material and a substrate
JP4961532B2 (ja) * 2006-07-25 2012-06-27 日産自動車株式会社 異種金属の接合方法及び装置
WO2008136352A1 (ja) * 2007-04-27 2008-11-13 Sumitomo Bakelite Company Limited 半導体ウエハーの接合方法および半導体装置の製造方法
FR2922202B1 (fr) * 2007-10-15 2009-11-20 Commissariat Energie Atomique Structure comportant une couche getter et une sous-couche d'ajustement et procede de fabrication.
US7943411B2 (en) * 2008-09-10 2011-05-17 Analog Devices, Inc. Apparatus and method of wafer bonding using compatible alloy
EP2340554B1 (en) * 2008-09-18 2017-05-10 Imec Methods and systems for material bonding
CN102104090B (zh) * 2009-12-22 2014-03-19 财团法人工业技术研究院 发光二极管芯片固晶方法、固晶的发光二极管及芯片结构

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0365807B1 (en) * 1988-10-12 1993-12-22 International Business Machines Corporation Bonding of metallic surfaces
DE19531158A1 (de) * 1995-08-24 1997-02-27 Daimler Benz Ag Verfahren zur Erzeugung einer temperaturstabilen Verbindung
US7276789B1 (en) * 1999-10-12 2007-10-02 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
US20020090756A1 (en) * 2000-10-04 2002-07-11 Masamoto Tago Semiconductor device and method of manufacturing the same
CN101120444A (zh) * 2005-03-16 2008-02-06 英特尔公司 形成自钝化互连的方法以及所得到的装置
US20060292824A1 (en) * 2005-06-08 2006-12-28 Eric Beyne Methods for bonding and micro-electronic devices produced according to such methods
US7547625B2 (en) * 2005-06-08 2009-06-16 Interuniversitair Microelektronica Centrum Vzw (Imec) Methods for bonding and micro-electronic devices produced according to such methods

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
A.MUNDING ET AL.: "《Wafer-Level 3D ICs Process Technology》", 31 December 2008 *
LI LI ET AL.: ""Cu/Sn Isothermal Solidification Technology for Hermetic Packaging of MEMS"", 《CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS》 *
YIBO RONG ET AL.: ""Low Temperature Cu-Sn Bonding by Isothermal Solidification Technology"", 《INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING》 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105358473A (zh) * 2013-07-11 2016-02-24 雷神公司 用作真空吸气剂的晶片级封装焊料阻挡物
CN105358473B (zh) * 2013-07-11 2020-02-14 雷神公司 用作真空吸气剂的晶片级封装焊料阻挡物
CN103434998A (zh) * 2013-08-29 2013-12-11 上海宏力半导体制造有限公司 晶圆级气密性的测试结构及测试方法
CN103434998B (zh) * 2013-08-29 2016-04-20 上海华虹宏力半导体制造有限公司 晶圆级气密性的测试结构及测试方法
CN105517947A (zh) * 2013-09-13 2016-04-20 Ev集团E·索尔纳有限责任公司 用于施加接合层的方法
US10438925B2 (en) 2013-09-13 2019-10-08 Ev Group E. Thallner Gmbh Method for applying a bonding layer
CN105826243A (zh) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 晶圆键合方法以及晶圆键合结构

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