CN101114630A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN101114630A
CN101114630A CNA2007101384263A CN200710138426A CN101114630A CN 101114630 A CN101114630 A CN 101114630A CN A2007101384263 A CNA2007101384263 A CN A2007101384263A CN 200710138426 A CN200710138426 A CN 200710138426A CN 101114630 A CN101114630 A CN 101114630A
Authority
CN
China
Prior art keywords
circuit board
semiconductor device
splicing ear
connection terminals
external connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101384263A
Other languages
English (en)
Inventor
青仓勇
福田敏行
太田行俊
三木启司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN101114630A publication Critical patent/CN101114630A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

本发明的半导体器件，包括第1布线基板1，该第1布线基板1具有：将焊接凸点(24)(凸起电极)形成于电极焊点上的IC芯片(半导体元件)(2、3、4)；以及与IC芯片(2、3、4)的各焊接凸点(24)所连接的连接端子(7)、用于与外部设备问连接的外部连接端子(8)、及设置在形成于基板表面的沟槽部内并具有与所述连接端子(7)等连接的导体布线(9)。即使在按照狭窄的间距配置导体布线9时，由于沟部的存在仍能增大截面积，因此能降低布线电阻。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，具体的说明涉及由形成凸起电极的半导体元件(以后简称为IC芯片)和布线基板组成的半导体器件及其制造方法。
背景技术
随着半导体器件功能日趋增多、处理速度加快，与外部电路连接的IC芯片的电极焊点(以后简称为IC焊点)的数量也增多，在IC焊点周围形成IC焊点通过引线和外部电路连接的引线接合方式存在极限。因此，为了使IC芯片的尺寸尽量小而同时增加IC焊点的数量，所以就采用倒装片方式，通过凸点(凸起电极)和外部电路连接。
但是，在用倒装片方式将IC焊点众多的IC芯片安装在电子设备的主板(安装基板)上时，要使IC焊点的焊点间距与主板的焊盘间距一致，所以必须在主板上采用能形成精细布线的高价的布线基板，因此很不经济。
因此，通过采用按照IC焊点的焊点间距和廉价的主板的布线路径(日文：ル-ル)之间的中间的布线路径生成的树脂基板(例如加高布线基板)或陶瓷布线基板作为中间基板(插入基板)，从而力求缓解对布线路径(日文：ル-ル)间距的要求。
插入基板的主要作用为，缓解施加于IC芯片的IC焊点(实际上形成于其上的凸点)和主板的安装焊盘间的焊接连接部的热应力，即因IC芯片和主板间线膨胀系数之差产生的热应力(例如，参照日本特開平9-64236号公报、特開2001-102492号公报)。
但是，在树脂布线基板上，利用称为加成法的电镀技术形成布线，但是从衬底基板平整度的角度考虑，在布线间距上有极限存在。在陶瓷布线基板上由于采用使用导电糊的印刷法形成布线，所以无法形成精细的布线。
因此，为了适应IC焊点间距进一步变窄的趋向，现提出一种采用硅布线基板作为第1插入基板使焊点间距加宽，并与第2插入基板(例如，树脂布线基板)连接的方案。
但是，由于硅布线基板利用蒸镀方法等形成布线，所以布线截面积无法加大，在作为有高速信号或大电流流动的IC芯片和外部电路之间的插入基板使用上，连接布线的布线电阻是个问题。
作为一种与此对应的处置方法，曾提出以下一种方案，即在输出用信号线等有较大电流流动的布线层上一体地形成低熔点的金属层的结构(例如，参照特開昭61-194744号公报)。该方案如图7所示，在硅布线基板101的铝布线102等的选好的布线上经蒸镀工序，形成低熔点金属层103，通过使该低熔点金属层103熔融，利用表面张力隆起让其成为一体，从而增大布线截面积。低熔点金属层103部分的截面形状如图中所示呈半园形。
但是，在以狭窄的间距布线的情况下，因要求布线自身的宽度收窄，所以在这一点上，即便如上所述地使低熔点金属层隆起，也难以具有较大的截面积。
发明内容
本发明为解决上述问题而提出，其目的在于将安装有形成凸起电极的半导体元件的布线基板作为即使间距狭窄但布线仍具有低电阻的基板，以此构成半导体器件。
为了达到上述目的，本发明的半导体器件，包括第1布线基板，该第1布线基板具有：将凸起电极形成于电极焊点上的半导体元件；以及与所述半导体元件的凸起电极所连接的内部连接端子、用于与外部设备间连接的外部连接端子、及设置在形成于基板表面的沟槽部内并具有与所述内部连接端子连接的导体布线。通过这样，在按照狭窄的间距布置导体布线时，也能利用沟槽部的存在而增大截面积，减小布线电阻。
第1布线基板的导体布线可以是直接连接外部连接端子和内部连接端子的第1导体布线。另外，可以是内部连接端子彼此之间互相连接的第2导体布线。此外，可以是直接连接外部连接端子和内部连接端子的第1导体布线和内部连接端子彼此之间互相连接的第2导体布线。
还可以包括第2布线基板，该第2布线基板具有：与安装着第1布线基板的安装部、与所述第1布线基板的外部连接端子间连接用的第2内部连接端子、与外部设备间连接用的第2外部连接端子、及所述第2内部连接端子与第2外部连接端子等连接的导体部；连接所述第1布线基板的外部连接端子与所述第2布线基板的第2内部连接端子的引线；以及设置在所述第2布线基板上的密封树脂，使其覆盖所述半导体元件、第1布线基板、及引线。
可以在第1布线基板的外部连接端子上形成焊接的外部连接电极。此外，可以利用焊接形成半导体元件的凸起电极。
本发明的半导体器件的制造方法，包括以下工序：准备具有凸起电极的半导体元件与安装所述半导体元件用的第1布线基板的工序；以及将所述半导体元件安装在所述第1布线基板上的工序，在所述第1布线基板的表面形成与所述半导体元件的凸起电极对向配置的内部连接端子、以及与外部设备之间连接用的外部连接端子，同时形成与所述内部连接端子连接的沟槽部，在所述沟槽部内形成导体布线。
最好半导体元件的凸起电极由焊接形成。最好在沟槽部内形成由与内部连接端子及外部连接端子相同的材料构成的底层。
具体为，在准备第1布线基板的工序中，从内部连接端子开始形成遍及外部连接端子的沟槽部，在所述外部连接端子上形成焊接的外部连接电极，在安装半导体元件的工序中，使所述第1布线基板上的内部连接端子和所述半导体元件的凸起电极互相连接的同时，还使所述凸起电极及所述外部连接电极的电极材料的部分熔融物流入所述沟槽部，在所述第1布线基板上形成至少表面层由所述电极材料组成的、连接所述内部连接端子与所述外部连接端子的第1导体布线。
另外，在准备第1布线基板的工序中，从规定的内部连接端子开始形成遍及其它规定的内部连接端子的沟槽部，在用印刷法向所述沟槽部供给焊接糊后，通过反流焊接，形成所述规定的内部连接端子彼此之间互相连接的第2导体布线。
再有，在上述各构成的半导体器件中，最好第1布线基板的内部连接端子及外部连接端子分别设置在形成于基板表面的凹部中。另外，最好第1布线基板的内部连接端子分别设置在形成于基板表面的凹部中。这是因为能利用自行对准效果防止凸起电极和布线基板内部连接端子间位置偏移、或布线基板的外部连接端子和外部连接电极间的位置偏移。
第1布线基板的内部连接端子及外部连接端子分别设置在形成于基板表面的凹部中，所述凹部与设置有第1导体布线的沟槽部连接，而且更加理想的是形成得比所述沟槽部更浅。第1布线基板的内部连接端子及外部连接端子分别设置在形成于基板表面的凹部中，所述凹部与分别设置着第1导体布线及第2导体布线的沟槽部连接，而且最好形成得比所述沟槽部浅。第1布线基板的内部连接端子分别设置在形成于基板表面的凹部中，所述凹部与设置着第2导体布线的沟槽部连接，而且最好形成得比所述沟槽部浅。这是因为能限制凸起电极及外部连接电极在焊接时熔融焊锡的流出方向，使其容易流入沟槽部。
在第1布线基板的外部连接端子上形成外部连接电极，最好所述外部连接电极和半导体元件的凸起电极由同一焊接材料组成。
第1布线基板的导体布线的至少表面层可以由与凸起电极及外部连接电极相同的焊接材料形成。
第1布线基板的导体布线的至少表面层是焊锡层，该焊锡层的底层最好包括：具有形成于有沟槽部的基板表面的、用于确保与绝缘膜间粘附性的最底层的粘接层；以及确保焊锡浸润性用的最上层的焊锡浸润层的多层结构。粘接层可以由Cr、Ti、TiW、TiN组成，焊锡浸润层可以由Au、Ni、Pt、Cu组成。底层可以由与第1布线基板的内部连接端子及外部连接端子相同的材料组成。
第1布线基板可以是硅布线基板。另外，硅布线基板可以是在单晶硅布线基板上形成半导体电路的电路形成基板。只要是电路形成基板，则可以减少装在硅布线基板上的IC芯片的电路数量，同时能提高布置的自由度。
第1布线基板的导体布线最好在半导体元件附近的位置有宽度加宽的部分。在通过凸起电极(即利用倒装片方式)半导体元件与布线基板连接后，如通常所做的那样，在注入不充满的树脂之际，利用宽度加宽的部分能防止该树脂流向半导体元件周围。
附图说明
图1A为表示本发明的半导体器件全体概要构成的俯视图。
图1B为同上的半导体器件的图1A中沿A-A线剖断的剖视图。
图2A为同上的半导体器件的图1B中B部的放大图。
图2B为构成同上半导体器件的布线基板的布线部分的俯视图。
图2C为同上的半导体器件的图2B中沿C-C线剖断的剖视图。
图3为说明制造同上半导体器件的前半道工序用的剖视图。
图4为说明制造同上半导体器件的后半道工序用的剖视图。
图5为本发明实施方式2的半导体器件的构成图。
图5A为表示本发明其它半导体器件的局部放大剖视图。
图5B为将同上的半导体器件之部分局部剖开的上视图。
图6A为表示本发明的另外其它的半导体器件的构成的俯视图。
图6B为同上的半导体器件的图6A中沿D-D线剖断的剖视图。
图7为现有半导体器件布线层的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
图1及图2示出的半导体器件具有：布线基板1；IC芯片2、3、4；以及作为外部连接电极用的焊接球5(IC芯片的数量、或布线基板的连接端子数量等为便于理解所示出的比实际的少)。
布线基板1的结构为，在硅布线基板6一侧的面上具有：设置在中央区域的多个连接端子7、设置在外围区域的多个外部连接端子8、以及与连接端子7和外部连接端子8连接的导体布线9。多个连接端子7配置在布线基板1上规定的3个区域，IC芯片2、3及4安装在上述各区域。在外部连接端子8上形成上述焊接球5。
这里，布线基板(以后称硅布线基板)如图所示，以只在表面形成导体布线的单层布线结构为例进行说明，但也可以用Al层形成内部布线的多层布线结构。再有，硅布线基板1可以为在单晶硅基板上形成半导体电路的电路形成基板(即半导体元件)。通过这样做，从而能减少装在硅布线基板1上的IC芯片的电路数量，同时提高布置的自由度，并力图能降低半导体器件的成本。
如图2中详细地示出的那样，在硅布线基板1上，例如利用光刻工序或蚀刻工序在硅基板6上形成沟槽部11及凹部12。然后，在有沟槽部11及凹部12的基板表面上例如形成SiO2作为绝缘膜，在绝缘膜13所覆盖的沟槽部11和凹部12内形成金属薄膜层14，焊锡层15形成于沟槽部11内金属薄膜层14之上。上述的连接端子7及外部连接端子8是指该凹部12内的金属薄膜层14，并且导体布线9是指沟槽部11内金属薄膜层14和焊锡层15。
IC芯片2形成保护膜22(例如聚酰亚胺)使其在该IC焊点21(Al电极)上开口，在该开口部上形成底部(日文：ァンダ)凸点金属23，在底部凸点金属23上形成焊接凸点24，并通过焊接凸点24与连接端子7连接。IC芯片3、4也是同样地构成，通过焊接凸点24与连接端子7连接。
焊锡层15用与焊接凸点24及焊接球5相同的材料(分别为Sn系或Pb系等)构成。焊锡层15下的金属薄膜层14虽然图中省略未示出，但为两层结构(或更多层的结构)，在下层有确保与绝缘膜13的粘接性用的粘接层，上层有确保焊锡浸润性用的焊锡浸润层。作为粘层例如可以由Cr、Ti、TiW、TiN等组成，作为焊锡浸润层例如可以由Au、Ni、Pt、Cu等组成。
焊接凸点24之下的底部凸点金属23也与金属薄膜层14一样为两层结构(或更多层结构)，在下层有确保与IC焊点的粘接性用的粘接层，上层有确保焊锡浸润性用的焊锡浸润层。与金属薄膜层14一样，作为粘层例如可以由Cr、Ti、TiW、TiN等组成，作为焊锡浸润层例如可以由Au、Ni、Pt、Cu等组成。
以下，利用图3及图4说明上述半导体器件的制造方法。实际上，在硅晶片上呈矩阵状地形成多条电路布线，通过逐个分割制作硅布线基板1，但为便于理解，将成为硅布线基板1的部分区域再加以放大，以图的形式示出。
首先，在硅基板6的整个面上涂布光刻胶16，形成与上述导体布线9、外部连接端子8、以及连接端子7的部分相当的布线图案，例如利用蚀刻工序在硅基板6上形成深10～20μm的凹部(图3A)。在蚀刻工序中，可以采用利用HF+HNO3的混合酸的湿蚀法或CF4、CHF3、Ar等气体的等离子刻蚀等干蚀法。
接着，再次在硅基板6的整个面上涂布光刻胶16，形成布线图案，使得仅与导体布线9的部分相当的凹部外露，通过利用所述的蚀刻工序再次进行蚀刻，从而在硅基板6上形成深20～50μm的沟槽部11(图3B)。
此时，沟槽部11和凹部12的接合点(用虚线围成的部分)最好为锥形。由此，后述的熔融的焊锡就容易流入。为了形成锥形，在只对前述的沟槽部11进行蚀刻的蚀刻工序中，可以用氟酸、硝酸等腐蚀液进行各向同性的蚀刻，也可以用CF4进行各向同性的干蚀。
也可用激光代替蚀刻工序，通过控制输出及照射时间，形成与用蚀刻工序形成的相同形状的凹部12、沟槽部13。
沟槽部11形成结束后，在整个晶片面上例如用CVD法形成SiO2之类的绝缘膜(参照上述图2C)，在其上例如用溅射法依次堆积金属薄膜层14(粘接层及焊锡浸润层)，利用光刻胶(图中未示出)将沟槽部11、凹部12掩模后，利用湿蚀法等蚀刻金属薄膜层14。在该阶段完成外部连接端子8及连接端子7(图3C)。
此时，金属薄膜层14是为了确保熔融焊锡的浸润性而用的，因此不会出现阶梯状敷层(日文1：ステツプカバレッジ)(阶梯状薄膜)的问题，只要形成于沟槽部11、凹部12的底面便可，能容易地制作。与此相反，当考虑采用现有的Cu线织(日文：ダマシン)工序时，就将金属薄膜层14作为籽晶层进行电解电镀。因此，金属薄膜层14的阶梯状敷层相当重要，在整个晶片上形成金属薄膜层14时不仅只在沟槽部11、凹部12的底面而且在侧面上也要形成薄膜。要在长宽比大的沟槽部11上找到无裂纹地形成金属薄膜层14的最佳条件是件非常困难的事。
在金属薄膜层14的蚀刻结束后，在晶片整个面上涂布焊剂，安装IC芯片2、3、4使其焊接凸点24与连接端子7对准位置。另外将焊接球5放在外部连接端子8上(图4A)。此时，外部连接端子8及连接端子7通过用金属薄膜层14覆盖凹部12而形成所以表面为凹状，焊剂就汇集于此，利用它的粘接力焊接凸点24或焊接球5的位置不易偏移。
然后进行反流焊接。借助于此，焊接凸点24和焊接球5熔融，在各自的熔融部分被焊接的同时，熔融焊锡由于其表面张力部分向沟槽部11流出，形成焊锡层15。因该熔融焊锡从焊接凸点24和焊接球5双方同时流出，又因形成于沟槽部11内的金属薄膜层14如上所述地焊锡浸润性良好的金属位于其表面，所以沟槽部11完全被焊锡埋没。迅速地形成由金属薄膜层14和焊锡层15组成的截面积大的导体布线9。焊接凸点24、连接端子7、导体布线9、外部连接端子8、焊接球5就能用同一组分的焊接材料连接(图4B)。
这时也利用外部连接端子8及连接端子7为凹状，而且还利用沟槽部11比该凹状深，从而与外部连接端子8及连接端子7做成平的情形时相比，熔融焊锡的流出方向能被限定。因而，易流入沟槽部11，能防止熔融焊锡向沟槽部11以外流出，也具有利用熔融焊锡的表面张力IC芯片2、3、4、焊接球5自行对准效果良好的优点。由于焊接球5和焊接凸点24由相同组分的焊接材料组成，所以也有能在相同的温度分布下进行焊接的优点。是一种高效率、低成本的生产工序。但凹部12可以为与沟槽部11相同的深度，再有，也可以在平面上不设凹部12而设外部连接端子8等。
此后，经过清洗工序，在IC芯片2、3、4和布线基板1的间隙中注入不充满的填充材料17(例如双酚F等热固化环氧树脂)，通过加热使其固化，制成半导体器件(图4C)。焊接球5就与安装基板连接。
如图5A、图5B所示，在硅布线基板1的导体布线9的各根布线上，可形成宽度加宽的部分18。在形成导体布线9时，为了能形成该宽度加宽的部分18而形成上述的沟槽部11、金属薄膜层14、焊锡层15。
此时，通过适当选定成为宽度加宽的部分的沟槽部11的深度或形状(例如可为波浪形、矩形、弧形、弓形)，能获得各种效果。图中示出的宽度加宽的部分18在IC芯片2的附近在沿其下面的四边各条边的方向上延伸，互相稍微空出几分间隔在所述方向上如相连接的那样并排。至于IC芯片3、4上也一样。
以往，如上所述，将不充满的填充材料17注入IC芯片2和布线基板1之间的间隙中，但此时，在芯片周围有不充满的填充材料17流出，无法控制边缘形状。由此，当在IC芯片2四边的各条边缘上出现差异时，在温度周期性地变化等可靠性试验中，会发生应力集中，影响焊接凸点24的连接可靠性，此外，因流出的不充满的填充材料17的流出物等一直到外部连接端子8，造成安装不良。
对此，在图5A、图5B示出的半导体器件中，因如上所述地形成导体布线9的宽度加宽的部分18，所以能如图所示，流出的不充满的填充材料17被宽度加宽的部分18挡住，由此阻止向外侧流出。通过这样进行控制，使得边缘形状在IC芯片2的四条边上变得均匀。借助于此，能避免应力集中、提高焊接凸点24的连接可靠性。另外，不充满的填充材料17不会到达外部连接端子8，能防止安装不良现象的发生。
图6A、图6B所示的半导体器件为将IC芯片2、3、4按倒装片法安装在和参照图1A、1B说明过的相同的硅布线基板1上，再将该硅布线基板1安装在树脂布线基板31上。但该硅布线基板1具有多层布线结构，在与连接端子7电气连接的Al外部连接端子8上没有图1A、图1B示出的焊接球5存在。
树脂布线基板3 1在基材32上可以采用各种基材，这些基材可以用在由玻璃纤维或开普勒(日文：ケプラ-)等有机物质组成的纤维中浸入环氧树脂、苯酚树脂、聚酰亚胺树脂等并使其固化后的固化物、或BT树脂。在树脂布线基板31的IC芯片安装面上形成小片(日文：ダイ)布线图案33、多个焊盘34、与各焊盘34连接的贯穿导体35，在背面形成与贯穿导体连接的导体布线图案36。在上述各个表面上例如形成Ni、Au的金属膜(图中未示出)。导体布线图案36与焊接球5连接。
在该树脂布线基板31的小片布线图案33上利用导电粘接剂(图中未示出)粘接上述硅布线基板1，硅布线基板1的Al外部连接端子8和树脂布线基板31的焊盘34用引线37连接，在树脂布线基板31的IC芯片安装面一侧设置密封树脂38，将硅布线基板1、IC芯片2、3、4、及引线37覆盖起来。
即，是这样一种结构，要适应IC芯片2、3、4的IC焊点间距变窄，将硅布线基板1作为第1插入基板用，扩大焊点间距，与用作第2插入基板的树脂布线基板31连接。
在硅布线基板1上，在IC芯片2、3、4之间的布线中收发高速信号的导体布线9与上述相同(参照先前的图2A)，其结构做成，在形成沟槽部11及金属薄膜层14后，在沟槽部11的金属薄膜层14上形成焊锡层15。
但是，在用印刷法供给焊接糊(Sn系或Pb系等)后，通过反流焊接形成焊锡层15。这种方法由于能对整片晶片一并供给焊锡形成导体布线9，因此生产过程效率高、成本低。由此形成的导体布线9截面积增大、布线电阻降低，所以能作为IC芯片2、3、4之间高速信号传输用的布线使用，能消除信号延迟的问题。
如上所述，根据本发明，容易使布线基板的表面具有即使在间距狭窄时截面积依旧大，而电阻低的导体布线。在这种布线基板上安装半导体元件构成的半导体器件，能在半导体元件之间或半导体元件与外部电路之间流动高速信号或大电流，并能防止信号延迟。即，利用本发明能廉价地实现高可靠性的半导体器件。所述的半导体器件能适用于各种电子设备，尤其是适用于便携式电子设备。

Claims (25)

1.一种半导体器件，其特征在于，
包括第1布线基板，该第1布线基板具有：
将凸起电极形成于电极焊点上的半导体元件；以及
与所述半导体元件的凸起电极所连接的内部连接端子、用于与外部设备连接的外部连接端子、及设置在形成于基板表面的沟槽部内并具有与所述内部连接端子连接的导体布线。
2.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的导体布线是直接连接内部连接端子和外部连接端子的第1导体布线。
3.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的导体布线是互相连接内部连接端子的第2导体布线。
4.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的导体布线是互相连接直接连接外部连接端子和内部连接端子的第1导体布线、和内部连接端子的第2导体布线。
5.如权利要求1所述的半导体器件，其特征在于，还包括：
第2布线基板，该第2布线基板具有：安装着第1布线基板的安装部、与所述第1布线基板的外部连接端子间连接用的第2内部连接端子、与外部设备间连接用的第2外部连接端子、及连接所述第2内部连接端子与第2外部连接端子的导体部；
连接所述第1布线基板的外部连接端子与所述第2布线基板的第2内部连接端子的引线；以及
设置在所述第2布线基板上的密封树脂，使其覆盖所述半导体元件、第1布线基板、及引线。
6.如权利要求1所述的半导体器件，其特征在于，
在第1布线基板的外部连接端子上形成焊接的外部连接电极。
7.如权利要求1所述的半导体器件，其特征在于，
利用焊接形成半导体元件的凸起电极。
8.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的内部连接端子及外部连接端子分别设置在形成于基板表面的凹部中。
9.如权利要求2所述的半导体器件，其特征在于，
第1布线基板的内部连接端子及外部连接端子分别设置在形成于基板表面的凹部中，所述凹部与设置有第1导体布线的沟槽部连接，而且形成得比所述沟槽部更浅。
10.如权利要求4所述的半导体器件，其特征在于，
第1布线基板的内部连接端子及外部连接端子分别设置在形成于基板表面的凹部中，所述凹部与分别设置着第1导体布线及第2导体布线的沟槽部连接，而且形成得比所述沟槽部浅。
11.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的内部连接端子分别设置在形成于基板表面的凹部中。
12.如权利要求3所述的半导体器件，其特征在于，
第1布线基板的内部连接端子分别设置在形成于基板表面的凹部中，所述凹部与设置着第2导体布线的沟槽部连接，而且形成得比所述沟槽部浅。
13.如权利要求1所述的半导体器件，其特征在于，
在第1布线基板的外部连接端子上形成外部连接电极，所述外部连接电极和半导体元件的凸起电极由同一焊接材料组成。
14.如权利要求13所述的半导体器件，其特征在于，
第1布线基板的导体布线的至少表面层由与凸起电极及外部连接电极相同的焊接材料形成。
15.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的导体布线的至少表面层是焊锡层，该焊锡层的底层包括；具有形成于有沟槽部的基板表面的、用于确保与绝缘膜间粘附性的最底层的粘接层；以及确保焊锡浸润性用的最上层的焊锡浸润层的多层结构。
16.如权利要求15所述的半导体器件，其特征在于，
粘接层由Cr、Ti、TiW、TiN组成，焊锡浸润层由Au、Ni、Pt、Cu组成。
17.如权利要求15所述的半导体器件，其特征在于，
底层由与第1布线基板的内部连接端子及外部连接端子相同的材料组成。
18.如权利要求1所述的半导体器件，其特征在于，
第1布线基板是硅布线基板。
19.如权利要求18所述的半导体器件，其特征在于，
硅布线基板是在单晶硅布线基板上形成半导体电路的电路形成基板。
20.如权利要求1所述的半导体器件，其特征在于，
第1布线基板的导体布线在半导体元件附近的位置有宽度加宽的部分。
21.一种半导体器件的制造方法，其特征在于，包括以下工序：
准备具有凸起电极的半导体元件与安装所述半导体元件用的第1布线基板的工序；以及
将所述半导体元件安装在所述第1布线基板上的工序，
在所述第1布线基板的表面形成与所述半导体元件的凸起电极对向配置的内部连接端子、以及与外部设备之间连接用的外部连接端子，同时形成与所述内部连接端子连接的沟槽部，在所述沟槽部内形成导体布线。
22.如权利要求21所述的半导体器件的制造方法，其特征在于，
半导体元件的凸起电极由焊接形成。
23.如权利要求21所述的半导体器件的制造方法，其特征在于，
在沟槽部内形成由与内部连接端子及外部连接端子相同的材料构成的底层。
24.如权利要求22所述的半导体器件的制造方法，其特征在于，
在准备第1布线基板的工序中，从内部连接端子开始形成遍及外部连接端子的沟槽部，在所述外部连接端子上形成焊接的外部连接电极，
在安装半导体元件的工序中，使所述第1布线基板上的内部连接端子和所述半导体元件的凸起电极互相连接的同时，还使所述凸起电极及所述外部连接电极的电极材料的部分熔融物流入所述沟槽部，在所述第1布线基板上形成至少表面层由所述电极材料组成的、连接所述内部连接端子与所述外部连接端子的第1导体布线。
25.如权利要求21所述的半导体器件的制造方法，其特征在于，
在准备第1布线基板的工序中，从规定的内部连接端子开始形成遍及其它规定的内部连接端子的沟槽部，在用印刷法向所述沟槽部供给焊接糊后，通过反流焊接，形成所述规定的内部连接端子彼此之间互相连接的第2导体布线。
CNA2007101384263A 2006-07-28 2007-07-27 半导体器件及其制造方法 Pending CN101114630A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006205463A JP4916241B2 (ja) 2006-07-28 2006-07-28 半導体装置及びその製造方法
JP2006205463 2006-07-28

Publications (1)

Publication Number Publication Date
CN101114630A true CN101114630A (zh) 2008-01-30

Family

ID=39022859

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101384263A Pending CN101114630A (zh) 2006-07-28 2007-07-27 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US7728429B2 (zh)
JP (1) JP4916241B2 (zh)
CN (1) CN101114630A (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102362187A (zh) * 2009-03-27 2012-02-22 爱德万测试株式会社 制造装置、制造方法及封装器件
CN103098191A (zh) * 2010-12-01 2013-05-08 松下电器产业株式会社 电子元器件安装体、电子元器件及基板
CN103241702A (zh) * 2012-02-09 2013-08-14 精工爱普生株式会社 电子器件及其制造方法、以及电子设备
CN103295998A (zh) * 2012-02-28 2013-09-11 台湾积体电路制造股份有限公司 具有中介框架的封装件及其形成方法
CN104925735A (zh) * 2014-03-18 2015-09-23 精工爱普生株式会社 电子装置、电子模块、电子设备以及移动体
CN104925736A (zh) * 2014-03-18 2015-09-23 精工爱普生株式会社 电子装置、电子设备以及移动体
CN106992157A (zh) * 2015-11-27 2017-07-28 富士电机株式会社 半导体装置
CN112635501A (zh) * 2019-10-08 2021-04-09 佳能株式会社 半导体装置和设备

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007038514A1 (de) * 2007-08-16 2009-02-19 Robert Bosch Gmbh Elektrische Schaltungsanordnung und Verfahren zur Herstellung einer elektrischen Schaltungsanordnung
JP5106460B2 (ja) * 2009-03-26 2012-12-26 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
US20100289129A1 (en) * 2009-05-14 2010-11-18 Satya Chinnusamy Copper plate bonding for high performance semiconductor packaging
US8766460B2 (en) 2012-02-02 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package with interposer frame and method of making the same
US8946072B2 (en) * 2012-02-02 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. No-flow underfill for package with interposer frame
US9691636B2 (en) * 2012-02-02 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer frame and method of manufacturing the same
DE102017212796A1 (de) * 2017-07-26 2019-01-31 Robert Bosch Gmbh Elektrische Baugruppe

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194744A (ja) * 1985-02-25 1986-08-29 Hitachi Ltd 半導体装置
JP2591499B2 (ja) * 1994-10-21 1997-03-19 日本電気株式会社 半導体装置
JP3726318B2 (ja) 1995-08-22 2005-12-14 株式会社日立製作所 チップ サイズ パッケージとその製造方法及びセカンド レヴェル パッケージング
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
JPH10270496A (ja) * 1997-03-27 1998-10-09 Hitachi Ltd 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法
JPH11177020A (ja) * 1997-12-11 1999-07-02 Oki Electric Ind Co Ltd 半導体実装構造およびその実装方法
JP3055619B2 (ja) * 1998-04-30 2000-06-26 日本電気株式会社 半導体装置およびその製造方法
JP2001102492A (ja) 1999-09-30 2001-04-13 Kyocera Corp 配線基板およびその実装構造
JP3822040B2 (ja) * 2000-08-31 2006-09-13 株式会社ルネサステクノロジ 電子装置及びその製造方法
US6507119B2 (en) * 2000-11-30 2003-01-14 Siliconware Precision Industries Co., Ltd. Direct-downset flip-chip package assembly and method of fabricating the same
US6744135B2 (en) * 2001-05-22 2004-06-01 Hitachi, Ltd. Electronic apparatus
JP2002353398A (ja) * 2001-05-25 2002-12-06 Nec Kyushu Ltd 半導体装置
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
EP1489657A4 (en) * 2002-02-06 2011-06-29 Ibiden Co Ltd SEMICONDUCTOR CHIP MOUNTING PLATE, METHOD FOR THE PRODUCTION THEREOF AND SEMICONDUCTOR MODULE
SG121707A1 (en) * 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
JP3922977B2 (ja) * 2002-06-19 2007-05-30 三菱樹脂株式会社 半導体装置内蔵多層配線基板
JP4138529B2 (ja) * 2003-02-24 2008-08-27 浜松ホトニクス株式会社 半導体装置、及びそれを用いた放射線検出器
US7239024B2 (en) * 2003-04-04 2007-07-03 Thomas Joel Massingill Semiconductor package with recess for die
JP4489393B2 (ja) * 2003-08-21 2010-06-23 オリンパス株式会社 半導体装置
JP4236664B2 (ja) * 2003-09-01 2009-03-11 富士通株式会社 集積回路部品及び実装方法
US7528473B2 (en) * 2004-03-19 2009-05-05 Renesas Technology Corp. Electronic circuit, a semiconductor device and a mounting substrate
JP4558413B2 (ja) * 2004-08-25 2010-10-06 新光電気工業株式会社 基板、半導体装置、基板の製造方法、及び半導体装置の製造方法
JP4759981B2 (ja) * 2004-11-02 2011-08-31 大日本印刷株式会社 電子部品内蔵モジュールの製造方法
JP4409455B2 (ja) * 2005-01-31 2010-02-03 株式会社ルネサステクノロジ 半導体装置の製造方法
US7323675B2 (en) * 2005-09-21 2008-01-29 Sigurd Microelectronics Corp. Packaging structure of a light-sensing device with a spacer wall

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102362187A (zh) * 2009-03-27 2012-02-22 爱德万测试株式会社 制造装置、制造方法及封装器件
US8667669B2 (en) 2009-03-27 2014-03-11 Advantest Corporation Apparatus and method for manufacturing a packaged device
CN103098191A (zh) * 2010-12-01 2013-05-08 松下电器产业株式会社 电子元器件安装体、电子元器件及基板
CN103098191B (zh) * 2010-12-01 2015-08-19 松下电器产业株式会社 电子元器件安装体、电子元器件及基板
CN103241702B (zh) * 2012-02-09 2016-08-24 精工爱普生株式会社 电子器件及其制造方法、以及电子设备
CN103241702A (zh) * 2012-02-09 2013-08-14 精工爱普生株式会社 电子器件及其制造方法、以及电子设备
CN103295998A (zh) * 2012-02-28 2013-09-11 台湾积体电路制造股份有限公司 具有中介框架的封装件及其形成方法
CN103295998B (zh) * 2012-02-28 2015-12-23 台湾积体电路制造股份有限公司 具有中介框架的封装件及其形成方法
CN104925736A (zh) * 2014-03-18 2015-09-23 精工爱普生株式会社 电子装置、电子设备以及移动体
CN104925735A (zh) * 2014-03-18 2015-09-23 精工爱普生株式会社 电子装置、电子模块、电子设备以及移动体
CN106992157A (zh) * 2015-11-27 2017-07-28 富士电机株式会社 半导体装置
CN106992157B (zh) * 2015-11-27 2021-10-26 富士电机株式会社 半导体装置
CN112635501A (zh) * 2019-10-08 2021-04-09 佳能株式会社 半导体装置和设备
CN112635501B (zh) * 2019-10-08 2023-08-15 佳能株式会社 半导体装置和设备

Also Published As

Publication number Publication date
JP4916241B2 (ja) 2012-04-11
JP2008034570A (ja) 2008-02-14
US20080087993A1 (en) 2008-04-17
US7728429B2 (en) 2010-06-01

Similar Documents

Publication Publication Date Title
CN101114630A (zh) 半导体器件及其制造方法
US11999001B2 (en) Advanced device assembly structures and methods
US8222749B2 (en) Wiring substrate and semiconductor device
KR100938408B1 (ko) 배선 기판 및 반도체 장치
US5907903A (en) Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
US5715144A (en) Multi-layer, multi-chip pyramid and circuit board structure
KR101388538B1 (ko) 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리
JP2825083B2 (ja) 半導体素子の実装構造
JP4870584B2 (ja) 半導体装置
US8125789B2 (en) Wiring substrate and electronic device
CN102208388B (zh) 半导体装置以及半导体装置的制造方法
JP4813255B2 (ja) 配線基板及びその製造方法ならびに半導体装置
KR101008891B1 (ko) 배선 기판, 전자 부품의 실장 구조 및 반도체 장치
KR20120109309A (ko) 반도체 장치, 반도체 장치의 제조 방법 및 배선 기판의 제조 방법
Ebersberger et al. Cu pillar bumps as a lead-free drop-in replacement for solder-bumped, flip-chip interconnects
JP5765981B2 (ja) 発光装置
CN100505196C (zh) 芯片电性连接结构及其制法
US8889483B2 (en) Method of manufacturing semiconductor device including filling gap between substrates with mold resin
JP2000340712A (ja) ポリマ補強カラム・グリッド・アレイ
CN100580894C (zh) 形成有预焊锡材料的半导体封装基板制法
CN102202463A (zh) 侧边封装型印刷电路板
JP2008124363A (ja) 半導体装置
JP2006196560A (ja) 半導体装置
CN100452329C (zh) 可供形成预焊锡材料的半导体封装基板及其制法
JPH11135567A (ja) 異方性導電膜、半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20080130