CN101069280A - 一种在集成电路管芯上形成互连结构的方法 - Google Patents
一种在集成电路管芯上形成互连结构的方法 Download PDFInfo
- Publication number
- CN101069280A CN101069280A CNA200580041139XA CN200580041139A CN101069280A CN 101069280 A CN101069280 A CN 101069280A CN A200580041139X A CNA200580041139X A CN A200580041139XA CN 200580041139 A CN200580041139 A CN 200580041139A CN 101069280 A CN101069280 A CN 101069280A
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- Prior art keywords
- dielectric
- barrier
- layer
- deposition
- copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04300831 | 2004-12-01 | ||
EP04300831.7 | 2004-12-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101069280A true CN101069280A (zh) | 2007-11-07 |
CN100580904C CN100580904C (zh) | 2010-01-13 |
Family
ID=36218493
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200580041139A Expired - Fee Related CN100580904C (zh) | 2004-12-01 | 2005-11-24 | 一种集成电路管芯及在其上形成互连结构的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7867889B2 (zh) |
EP (1) | EP1820214A2 (zh) |
JP (1) | JP2008522423A (zh) |
CN (1) | CN100580904C (zh) |
WO (1) | WO2006059261A2 (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101326630B (zh) * | 2005-12-07 | 2011-07-20 | Nxp股份有限公司 | 在用于半导体器件的结构中的第二材料中嵌入的第一材料的表面上形成层的方法 |
CN103828046A (zh) * | 2011-09-30 | 2014-05-28 | 英特尔公司 | 用于3d集成电路层叠的层间通信 |
CN105870050A (zh) * | 2015-01-19 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
US10950548B2 (en) | 2017-02-24 | 2021-03-16 | Murata Manufacturing Co., Ltd. | Semiconductor device |
CN113130384A (zh) * | 2020-01-16 | 2021-07-16 | 中芯国际集成电路制造(天津)有限公司 | 半导体结构的形成方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2064737A1 (en) * | 2006-09-04 | 2009-06-03 | Nxp B.V. | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES |
US7863176B2 (en) * | 2008-05-13 | 2011-01-04 | Micron Technology, Inc. | Low-resistance interconnects and methods of making same |
US8393286B2 (en) * | 2009-09-18 | 2013-03-12 | Raytheon Company | Hull robot garage |
US8404582B2 (en) | 2010-05-04 | 2013-03-26 | International Business Machines Corporation | Structure and method for manufacturing interconnect structures having self-aligned dielectric caps |
KR20120138875A (ko) * | 2011-06-16 | 2012-12-27 | 삼성전자주식회사 | 배선 구조물 및 이의 제조 방법 |
US8754527B2 (en) | 2012-07-31 | 2014-06-17 | International Business Machines Corporation | Self aligned borderless contact |
US9837306B2 (en) | 2015-12-21 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and manufacturing method thereof |
US9865538B2 (en) | 2016-03-09 | 2018-01-09 | International Business Machines Corporation | Metallic blocking layer for reliable interconnects and contacts |
US9735103B1 (en) | 2016-07-20 | 2017-08-15 | International Business Machines Corporation | Electrical antifuse having airgap or solid core |
US9793207B1 (en) | 2016-07-20 | 2017-10-17 | International Business Machines Corporation | Electrical antifuse including phase change material |
US10770286B2 (en) * | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US10381315B2 (en) | 2017-11-16 | 2019-08-13 | Samsung Electronics Co., Ltd. | Method and system for providing a reverse-engineering resistant hardware embedded security module |
CN112928061A (zh) * | 2019-12-05 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US11227794B2 (en) * | 2019-12-19 | 2022-01-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US121616A (en) * | 1871-12-05 | Improvement in burial-cases | ||
DE4213179A1 (de) * | 1992-02-26 | 1993-12-02 | Deutsche Aerospace | Kabel für EMV-sichere Übertragung |
JP3179212B2 (ja) * | 1992-10-27 | 2001-06-25 | 日本電気株式会社 | 半導体装置の製造方法 |
US6077771A (en) | 1998-04-20 | 2000-06-20 | United Silicon Incorporated | Method for forming a barrier layer |
US6204204B1 (en) * | 1999-04-01 | 2001-03-20 | Cvc Products, Inc. | Method and apparatus for depositing tantalum-based thin films with organmetallic precursor |
US6391785B1 (en) | 1999-08-24 | 2002-05-21 | Interuniversitair Microelektronica Centrum (Imec) | Method for bottomless deposition of barrier layers in integrated circuit metallization schemes |
US6114243A (en) | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
US6451685B1 (en) * | 2001-02-05 | 2002-09-17 | Micron Technology, Inc. | Method for multilevel copper interconnects for ultra large scale integration |
US6927159B2 (en) * | 2003-05-27 | 2005-08-09 | Texas Instruments Incorporated | Methods for providing improved layer adhesion in a semiconductor device |
US7071100B2 (en) * | 2004-02-27 | 2006-07-04 | Kei-Wei Chen | Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process |
US7148089B2 (en) * | 2004-03-01 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper fuse links |
-
2005
- 2005-11-24 CN CN200580041139A patent/CN100580904C/zh not_active Expired - Fee Related
- 2005-11-24 JP JP2007543949A patent/JP2008522423A/ja not_active Withdrawn
- 2005-11-24 US US11/720,748 patent/US7867889B2/en active Active
- 2005-11-24 WO PCT/IB2005/053892 patent/WO2006059261A2/en active Application Filing
- 2005-11-24 EP EP05824862A patent/EP1820214A2/en not_active Withdrawn
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101326630B (zh) * | 2005-12-07 | 2011-07-20 | Nxp股份有限公司 | 在用于半导体器件的结构中的第二材料中嵌入的第一材料的表面上形成层的方法 |
CN103828046A (zh) * | 2011-09-30 | 2014-05-28 | 英特尔公司 | 用于3d集成电路层叠的层间通信 |
CN103828046B (zh) * | 2011-09-30 | 2018-05-22 | 英特尔公司 | 用于3d集成电路层叠的层间通信 |
CN105870050A (zh) * | 2015-01-19 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN105870050B (zh) * | 2015-01-19 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
US10950548B2 (en) | 2017-02-24 | 2021-03-16 | Murata Manufacturing Co., Ltd. | Semiconductor device |
CN108511520B (zh) * | 2017-02-24 | 2021-09-28 | 株式会社村田制作所 | 半导体装置 |
CN113130384A (zh) * | 2020-01-16 | 2021-07-16 | 中芯国际集成电路制造(天津)有限公司 | 半导体结构的形成方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2008522423A (ja) | 2008-06-26 |
WO2006059261A2 (en) | 2006-06-08 |
EP1820214A2 (en) | 2007-08-22 |
WO2006059261A3 (en) | 2006-08-31 |
CN100580904C (zh) | 2010-01-13 |
US20100013098A1 (en) | 2010-01-21 |
US7867889B2 (en) | 2011-01-11 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20080516 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20080516 Address after: Holland Ian Deho Finn Applicant after: Koninkl Philips Electronics NV Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100113 Termination date: 20151124 |