CN1575515A - 利用电介质阻挡层实施金属镶嵌的方法 - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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Abstract
本发明通过电介质阻挡层(50，90，91)完成金属镶嵌过程以改善台阶覆盖并降低接触电阻。实施例包括利用两种不同的电介质层(50，31)避免定位不准的问题。实施例更进一步包括利用铜类金属物质(100)来完成双层金属镶嵌(100A，100B)的过程。
Description
技术领域
本发明涉及以阻挡层构成内部连接(interconnection)结构的半导体装置。本发明特别适用于具有深亚微米领域(deep sub-micron regime)特征的超大规模集成电路(ULSI)装置。
背景技术
当集成电路的几何结构不断向深亚微米领域发展时，集成技术在数量及严格性上所面临的问题也随之增加。由于狭细导线间距离的最小化，使得超大规模集成电路半导体的布线需要越来越密集的配置。当采用约在0.13微米及以下的设计标准时，制造半导体装置的方法即成为问题了。
通常的半导体装置包括一个半导体基板，典型为掺杂单晶硅，以及多个连续形成的电介质间层及导电结构。集成电路包含有许多导电结构，该导电结构包括有由内部布线间距分隔的导电线路和许多内部连接的线路，例如，总线线、位线、字符线及逻辑互连线。典型地，位于不同层中的导电结构，如上层和下层，由导电栓填充导孔以形成电连接，此时导电栓销填充在导孔与半导体基板上的作用区建立电连接，例如源/漏极区域。典型地，导电线路是形成于相对于半导体基板实质上水平延伸的沟槽内。当特征尺寸(feature sizes)缩小至深亚微米领域，包含5层或更多层金属敷层的半导体″芯片″变得更流行起来。
典型地，填充导孔的导电栓是由电介质间层(interlayerdielectric，ILD)在包含至少一个导电特征的图案化的传导层上沉积形成的，利用传统的照像光刻技术通过该ILD形成开孔，并以导电材料填充该开孔。典型地，利用化学机械抛光(chemical-mechanicalpolishing，CMP)除去ILD表面积留的过多的导电材料。一种已知的镶嵌方法基本包含在ILD上形成开孔并以金属填充该开孔。双层金属镶嵌(Dual damascene)技术包含形成具有低接触或导孔部份的开孔以连通上方沟槽部份，该开孔以导电材料填充，典型为金属，同时形成导电栓以沟通传导线路的电连接。
在用于内部连接的金属敷层方面，铜及铜合金已经比铝(Al)获得更大的关注。铜相对而言便宜，易于加工，以及比铝的电阻要低。此外，铜通过钨(W)改良了其电特性，使得铜成为用作导电栓及导电线路的令人满意的金属。然而，由于铜会在电介质材料(如二氧化硅)上扩散，必须借助扩散阻挡层(barrier layer)将铜内部连接机结构封于内部。典型的扩散阻挡材料包括钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钨化钛(TiW)、钨(W)、氮化钨(WN)、钛-氮化钛(Ti-TiN)、氮硅化钛(TiSiN)、氮硅化钨(WSiN)、氮硅化钽(TaSiN)、以及氮化硅(silicon nitrid)用以将铜封包其中。这类用来封包铜的阻挡材料的用途并不局限于铜与ILD的界面，同样地包括与其它金属的界面。
基本上，铜内部连接技术使用了镶嵌技术来实现，其中第一电介质层(如氧化硅层等)来自于四乙基原硅酸盐(TEOS)或硅烷化物或低电介质常数材料，亦即电介质常数不大于4(以真空表示电介质常数为1)的材料，形成在下层线路结构之上的盖层，例如带有氮化硅覆盖层的铜或铜合金线路结构。然后通过电沉积或非电沉积的方式进行铜沉积，以沉积出阻挡层和可选择的种晶层(seedlayer)。
常规的内部连接技术，例如金属镶嵌技术，尤其使用敷铜法时，当特征尺寸越来越进入深亚微米领域时，多方面的问题变得特别严重。例如，使用常规金属阻挡层，如钽、氮化钽、氮化钛、氮化钨、及钨，会因各种原因产生成问题。这些金属阻挡层的电阻都大于铜、铝或银。此外，各种不同的阻挡金属层，尤指选择的钽及氮化钽阻挡金属层，只能利用物理气相沉积(physical vapor deposition，PVD)技术，例如溅镀(sputter)来沉积。此种常规的溅镀层呈现出不良的共形台阶覆盖(conformal step coverage)。此外，随着特征尺寸的降低，则电子迁移及电容与台阶覆盖及电阻率问题将一起变得严重。使得于多层内部连接技术中调节定位误差也变得很困难。
因此，因为特征尺寸的减少而产生的问题，如不良的台阶覆盖、接触电阻率、电子迁移、电容及对位误差，导致改善内部连接技术的需求，特别是铜镶嵌技术。存在着特殊需求以改善对于铜镶嵌工艺中包含具有小于约0.13微米特征尺寸的超微型电路的内部连接技术。
发明内容
本发明的优点是提供一种深亚微米领域中具有高可靠性内部连接电路结构的半导体装置。
本发明的另一个优点是提供一种深亚微米领域中具有高可靠性内部连接电路结构的半导体装置制造方法。
本发明的其它优点及特征将在接下来的部分描述中提出，本发明及其实施例对于本领域的普通技术人员来讲，是明显易懂的。本发明的优点由权利要求的要点所特别指出加以了解或获得。
依据本发明，前述的及其它的优点通过一种半导体装置的制造方法部分地得以体现，该方法包含：在基板上形成第一电介质层；在该第一电介质层上，形成包含第一电介质阻挡材料的第一阻挡层；利用蚀刻技术生成由第一电介质层侧表面及底部所界定的第一开孔；在第一电介质层上的第一阻挡层的上表面，在界定第一开孔的第一电介质层侧表面及第一开孔底部，形成包含第二电介质阻挡层材料的第二阻挡层，其与第一电介质阻挡材料是不同的；对第一阻挡层进行选择性蚀刻以移除第二阻挡层，并停止于第一阻挡层上表面，并自第一开孔底部移除第二阻挡层，该第一开孔留下第二阻挡层的一部份以作为在限定第一开孔的第一电介质层侧表面的衬里；以及用金属填充该开孔形成下部金属特征。
本发明的另一个方面是一个包含有铜或铜合金金属特征的半导体装置，形成具有第一阻挡层的第一电介质层侧表面所界定的开孔，该第一阻挡层包含其上的第一电介质阻挡材料；第一阻挡衬里包含不同于第一电介质阻挡材料的第二电介质阻挡材料，位于下部金属特征与第一电介质层之间，第一电介质层侧表面上，其中第一阻挡衬里有一上部表面延伸至第一电介质层上表面下方的一段距离。
本发明实施例包含双层金属镶嵌技术以执行形成具有传导线及导孔以电性连接至下部金属特征的双层金属镶嵌结构。该双层金属镶嵌结构是通过形成双层金属镶嵌开孔，然后在形成该双层金属镶嵌开孔的电介质层侧表面形成电介质衬里来完成的。所述阻挡层的使用，可在不同的电介质材料中选择，如氮化硅、氮氧化硅、及碳化硅，以及可以沉积至一适当厚度，如大约50至500埃。本发明实施例进一步包含铜金属的双层金属镶嵌结构。
对于本领域的普通技术人员，以下详细说明将使本发明的其它优点变得容易明白，其中以通过图示介绍实施本发明的最佳模式的方法对本发明的实施例做简单陈述。必须认识到，本发明适用于其它及不同的实施例，并且其多个细节能适用于不同的显而易见的修正，均不违反本发明。因此，附图及描述只是用于说明性本质而非用于限制。
附图说明
图1至图10概要性的说明了本发明的实施例所包含方法的连续阶段。在图1至图10中，相同的特征或单元以相同的参考数字表示。
具体实施方式
本发明提供一种构成具有内部连接线路结构的半导体装置的方法，以改进台阶覆盖、降低接触电阻、加强电子迁移阻抗、减小电容及定位误差。这些目标的达成关键在于使用电介质阻挡层代替含金属的或金属的阻挡层。有益的是，依照本发明的实施例，电介质阻挡层由化学气相沉积法(CVD)沉积而成，因此，特别是对于常规溅镀方法沉积金属阻挡层，表现出较好的台阶覆盖。此外，电介质阻挡层能够比常规的含金属阻挡层更均匀地沉积。在本发明的不同的实施例中，电介质阻挡层可包含适当的电介质阻挡材料，例如氮化硅、碳化硅或氮氧化硅。此外，当金属阻挡层不沉积于导孔及传导线时，接触电阻明显由于使用电介质阻挡层而降低。进一步地，铜导孔/传导线的直接接触提高了电子迁移率。本发明的实施例也可降低寄生电容。有益的是，依照本发明的实施例，利用二种不同的电介质阻挡层增加了对定位误差的宽容度。
在本发明的不同实施例中，电介质层可由常规用于制造半导体装置的各种电介质材料所组成，特别指低初值(lower values of primitivity)电介质材料，如″低k″电介质材料。″低k″材料特别地表示电介质常数约小于3.9的材料(依据真空的之电介质常数值为1)。依照本发明的实施例所用的合适的电介质材料包括：可流动氧化物，如倍半硅氧烷氢(hydrogen silsesquioxane，HS Q)及倍半硅氧烷甲基(methylsilsesquioxane，MS Q)，及不同的有机″低k″材料，典型上具有约2.0至3.8的电介质常数，例如FLARE 20
TM电介质，一种聚(芳基)醚(poly(arylene)ethers)，可获自Allied Signal，Advanced MicromechanicMaterials，桑尼维耳市，美国加利福尼亚州。Black-Diamond
TM电介质，可获自Applied Materials，圣克拉拉市，美国加利福尼亚州。BCB(二乙烯硅氧烷双苯并环丁烷divinylsiloxane bis-benzocyclobutene)及SilkTM电介质，一种类似BCB有机聚合物，同时可由Dow Chemical公司，米德兰市，美国密歇根州得到。其它适合低k电介质包含聚(芳基)醚(poly(arylene)ethers)、聚(芳基)醚氮杂茂环系(poly(arylene)ethers azoles)、聚对亚苯基二甲基N(parylene-N)、聚硫亚氨(polyimides)、聚N(polynapthalene-N)、聚苯基对二氮(polyphenyl-quinoxalines)(PPQ)、聚亚苯基氧化物(polyphenyleneoxide)、聚乙烯(polyethylene)及聚丙烯(polypropylene)。其它适合用作本发明实施例之低k介电材料包含FOx
TM(HSQ基)、XLKTM(HSQ基)、及SILK
TM、芳香族碳氢化合物聚合物(aromatichydrocarbon polymer)(各别可获自Dow Chemical公司，米德兰市，美国密歇根州)；Coral
TM，碳掺杂硅氧化物(可由Novellus System，圣何塞市，美国加利福尼亚州获得)；Flare
TM，有机聚合物，HOSP
TM，混合硅氧烷有机聚合物(hybrid-siloxane-organic polymer)，及NanoglassTM，非多孔硅土(各别可获自Honeywell Electronic Materials)；以及来自四乙基原硅酸盐(tetraethyl orthosilicate)(TEOS)和氟掺杂硅酸盐玻璃(fluorine-doped silicate glass)(FSG)之卤素掺杂(halogen-doped)(即氟掺杂fluorine-doped)二氧化硅。
本发明特别应用于包括金属镶嵌技术的内部连接技术。因此，本发明的实施例包含具有低k材料的沉积层，并通过金属镶嵌技术在低k电介质层形成一个开孔，也包括双层金属镶嵌技术。形成于低k电介质层的开孔可以成为随后填充如铜或铜合金之类金属的导孔，以形成在上层及下层金属传导线或导孔的内部连接，铜或铜合金被填充到导孔以建立在半导体基板上的源/漏极区域与第一金属层的电连接。在低k电介质层的开孔也可以是沟槽，在此情况下该沟槽被填充形成内部连接传导线。该开孔也可通过双层金属镶嵌技术形成，其中导孔/接触孔同时由金属沉积形成传导线连通。
在铜金属镶嵌技术的实现中，阻挡层最初典型沉积在金属镶嵌开孔及在其上沉积的种晶层上。适当的种晶层包括含有适量(例如约0.3％到约12％)的镁、铝、锌、锆、锡、镍、钯、银或金的铜合金。
图1至图10概要性的说明了本发明的实施例所包含方法的连续阶段。在图1中，形成在半导体基板10的作用区由浅沟槽隔断11所隔开。此作用区包括带有氧化闸层12A和闸电极12B的晶体管12和源/漏极区域12C。电介质间层(ILD)13形成于基板上方，而例如碳化硅、氮氧化硅或氮化硅的阻挡层14形成在该ILD层13上，典型厚度为50到500埃。如图2所示，栓塞开孔形成于ILD13并填充例如钨之金属，以形成栓塞20连结至晶体管12及栓塞21连结至源/漏极区域12C。
在图3中，形成在阻挡层14上方的电介质层30覆盖ILD13，阻挡层31形成于电介质层30之上，金属镶嵌开孔32，例如一个沟槽，形成于由电介质层30的侧表面31A所界定的电介质层30内。如图4所示，然后通过化学气相沉积法沉积电介质阻挡层40于阻挡层31上并给开孔32衬里。阻挡层40呈现出高度的一致性并于沟槽32的边角形成圆角40A。阻挡层40包含不同于电介质阻挡层31的电介质材料，此阻挡层31在随后的蚀刻中作为蚀刻停止层。依照本发明的实施例沉积的各种阻挡层可包含如氮化硅、氮氧化硅或碳化硅等材料。
如图5所示，接下来进行非等向性蚀刻，自阻挡层31上表面及沟槽32底部移除阻挡层40，沟槽32留下电介质衬里50于界定沟槽32的电介质层30侧表面30A上。非等向性蚀刻后，该电介质衬里50的上部表面可延伸到电介质阻挡层31的上表面下方，如数字51所示。典型地，电介质衬里50的上部表面与电介质阻挡层31上表面之间的距离大约为50至500埃。
如图6所示，然后在沟槽32填充金属并通过化学机械抛光技术(CMP)形成金属传导线60。本发明的实施例包括用电沉积或无电沉积铜形成金属传导线60。在这种情况下，典型地，阻挡层及种晶层会先于填充开孔32沉积。
本发明的实施例中包含不同类型的双层金属镶嵌结构。包括先沟槽后导孔，及先导孔后沟槽双层金属镶嵌技术。双层金属镶嵌的过程如如图7至图10所示，建立于金属传导线60上。如图7所示，然后沉积与电介质阻挡层31的电介质阻挡材料不同的电介质阻挡层70。接着于电介质层71和73之间沉积电介质阻挡层72，并于电介质层73上形成电介质阻挡层74。然后形成包含由电介质层73侧表面73A所界定的沟槽76及相连结由电介质层71侧表面71A所界定的导孔75的双层金属镶嵌开孔。该双层金属镶嵌结构可由常规的先沟槽后导孔或先导孔后沟槽技术形成。
有益的是，本发明的实施例提供了对定位误差的宽容度。如图7所示，导孔75相对于下部金属特征60对位错误，如此导孔75底部一部份形成于金属传导线60上表面，及一部份形成于电介质阻挡层31上表面以策略性的预防值(spiking)。因此，导孔75自金属特征60侧表面偏移的一段距离″M″，将超过下部金属特征60填充沉淀所需的距离。
如图8所示，接着沉积电介质阻挡层80以衬里于双层镶嵌开孔及电介质阻挡层74上表面，并形成圆角80A。电介质阻挡层80包含不同于电介质阻挡层74、电介质阻挡层72及电介质阻挡层31所用的电介质材料，如此在双层金属镶嵌开孔形成电介质衬里期间，电介质阻挡层74、72及31的作用如同蚀刻停止层。接着利用非等向性蚀刻自电介质阻挡层74上表面，及位于导孔75和沟槽76之间电介质阻挡层72的裸露上表面移除电介质层80的一部分，并自导孔75底部移除电介质层80的一部分。最后结构如图9所示，包含有一微小缺口90A位于形成在电介质层71侧表面的电介质衬里90上表面与电介质阻挡层72上表面之间，以及一微小缺口91A位于电介质衬里91上表面与电介质阻挡层74上表面之间，同样约是50到500埃。该双层金属镶嵌开孔接着以金属填充，例如铜，且通过CMP技术使沉积金属100上表面基本上与阻挡层74的上表面同平面。接着沉积另一电介质阻挡层或顶盖层101，用以将包含金属传导线100B连接导孔100A以电性连结至下部金属特征60的金属化物质100包封在内。在完成敷铜时须先沉积阻挡层及种晶层。
有益的是，依照本发明的实施例加工的半导体装置，具有高可靠性的内部连接线路结构，表现为降低的电子迁移，降低的寄生电容及降低的接触电阻率。通过电介质阻挡层使台阶覆盖一致并提供较大的定位误差宽容度。
本发明在制造不同类型的半导体装置具有工业实用性。本发明特别适用于在深亚微米领域中以高电路速度设计为特征的半导体装置的制造。
在前面的详细描述中，本发明以特定的示范实施例为参考来加以陈述。然而，很明显的，在不违背本发明主要精神与范畴的情况下，如在权利要求书中所阐述的，不同的修正及改变是可以的。因此，本详述及图示只是用以说明而非用以限制本发明。必须了解的是，本发明可以应用各种其它的化合物和环境，并且可以在本发明于此所阐述的概念范围内加以改变或修正。
Claims (10)
1.一种制造半导体装置的方法，该方法包括：
于基板(10)上形成第一电介质层(30)；
于该第一电介质层(30)上形成包括第一电介质阻挡材料的第一阻挡层(31)；
蚀刻形成由该第一电介质层(30)之侧表面(30A)与底部所界定的第一开孔(32)；
在该第一电介质层(30)之上的该第一阻挡层上表面及界定该第一开孔的第一电介质层的侧表面以及该开孔底部，形成包括不同于该第一电介质阻挡材料(31)的第二电介质阻挡材料的第二阻挡层(40)；
对该第一阻挡层进行选择性蚀刻以从该第一阻挡层的上表面移除该第二阻挡层，并停止于该第一阻挡层上表面，并自该第一开孔的底部移除该第二阻挡层，剩下位于界定该第一开孔(32)的该第一电介质层(30)的该侧表面(30A)上衬里(50)的该第二阻挡层部分；以及
以金属填充该开孔以形成下部金属特征(60)。
2.根据权利要求1所述的方法，其特征在于该第一(31)和第二电介质阻挡层(40)选自一组包括氮化硅、氮氧化硅和碳化硅的化合物，该方法包含由化学气相沉积法分别沉积该第一及第二阻挡层。
3.根据权利要求1所述的方法，包含用铜或铜合金(60)填充该开孔(32)。
4.根据权利要求1所述的方法，进一步包含：
在该第一阻挡层(31)及该下部金属特征(60)的上表面之上形成包含不同于该第一电介质阻挡材料的第三介电质阻挡材料的第三阻挡层(70)；
在该第三阻挡层(70)上形成第二电介质层(71)；
在该第二电介质层(71)上形成包含有第四电介质阻挡材料之第四阻挡层(72)；
在该第四阻挡层(72)上形成第三电介质层(73)；
在该第三电介质层(73)上形成包含有第五电介质阻挡材料的第五阻挡层(74)；
蚀刻形成包含由该第三电介质层(73)的侧表面(73A)所界定的上沟槽部份(76)的双层金属镶嵌开孔，该双层金属镶嵌开孔与由该第二电介质层(71)的侧表面(71A)所界定的较低导孔(75)，以及位于该下部金属特征(60)的至少部分上表面的底部相连通；
形成包含不同于该第一(31)、第四(72)及第五(74)电介质材料的第六电介质阻挡材料的第六阻挡层(80)，其位于该第三电介质层(73)上的第五阻挡层(74)上，位于界定该沟槽(76)的该第三电介质层侧表面(73A)上，位于界定该导孔(75)的该第二电介质层(71)的侧表面(71A)上，位于介于该沟槽(76)与导孔(75)之间的该第四阻挡层(72)的一部分上，以及位于该导孔的底部；
对该第五及第四阻挡层进行蚀刻以移除该第六阻挡层，并停止于该第五及第四阻挡层上，对导孔底部进行蚀刻以移除该第六阻挡层，剩下位于界定该沟槽的该第三电介质层(73)的侧表面(73A)及界定导孔(75)的该第二电介质层(71)的侧表面(71A)，如衬里(91，90)的一部分第六阻挡层；以及
以金属填充该双层金属镶嵌开孔以形成金属传导线(100B)连接下面的金属导孔(100A)。
5.根据权利要求4所述的方法，包含以铜或铜合金(100)填充该双层金属镶嵌开孔以形成铜或铜合金传导线(100B)连接铜或铜合金导孔(100A)，该铜或铜合金导孔(100A)用来电连接至下部金属特征(60)。
6.根据权利要求4所述的方法，进一步包含在该第六阻挡层(74)上表面及该金属传导线(100B)的上表面沉积包括第七电介质阻挡材料的第七阻挡层(101)。
7.一种半导体装置，包含：
包括铜或铜合金的下部金属特征(60)，该特征(60)形成于带有第一阻挡层(31)的第一电介质层(30)的侧表面(30A)所界定的开孔中，该阻挡层(31)包含有第一电介质阻挡材料；
包含不同于该第一电介质阻挡材料(31)的第二介电质阻挡材料的第一阻挡衬里(50)，该衬里(50)位于下部金属特征(60)与第一电介质层(30)之间的第一介电质层(30)侧表面(30A)上，该第一阻挡衬里(50)有一个上部表面延伸一段距离至该第一电介质层(30)的上表面下方。
8.根据权利要求7所述的半导体装置，进一步包含：
具有不同于该第一电介质阻挡材料的第三电介质阻挡材料的第二阻挡层(70)，该第二阻挡层位于该第一电介质层(30)上方的该第一阻挡层(31)之上；以及
双层金属镶嵌结构，其形成并电连结至该下部金属特征(60)，该双层金属镶嵌结构包含：
形成于该第二阻挡层(70)之上的第二电介质层(71)；
形成于该第二电介质层(71)之上的包含第四电介质阻挡材料的第三阻挡层(72)；
形成于该第三阻挡层(72)之上的第三电介质层(73)；
形成于该第三电介质层(73)之上的包含第五电介质阻挡材料的第四阻挡层(74)；
包含由该第三电介质层(73)的侧表面(73A)所界定的沟槽(76)，并连接至由该第二电介质层(71)的侧表面(71A)所界定的导孔(75)和下部金属特征(60)的至少一部分上表面的底部的双层金属镶嵌开孔；
包含不同于第一、第四及第五电介质阻挡材料的第六电介质阻挡材料的第二阻挡衬里(90，91)，该第二阻挡衬里(90，91)位于界定导孔(75)的该第二电介质层(71)的侧表面(71A)及界定沟槽(76)的第三电介质层(73)的侧表面(73A)上；以及
用铜或铜合金(100)填充该双层金属镶嵌开孔，在该第三电介质层(73)中形成铜或铜合金传导线(100B)，与位于该第二介电质层(71)内的导孔(100A)连接，并依序与该下部金属特征(60)电连接。
9.根据权利要求8所述的半导体装置，其特征在于：
位于该第二电介质层(71)的侧表面(71A)上的该第二阻挡衬里(90)的上部表面，延伸一段距离至该第三阻障层(72)的上表面下方；以及
位于该第三电介质层(73)的侧表面(73A)上的该第二阻挡衬里(91)的上部表面，延伸一段距离至该第四阻障层(74)的上表面下方。
10.根据权利要求8所述的半导体装置，其特征在于该第一(30)、第二(50)、第三(70)、第四(72)、第五(74)及第六电介质阻挡(90，91)材料选自一组包含氮化硅、碳化硅及氮氧化硅的化合物组。
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| US09/817,056 US7132363B2 (en) | 2001-03-27 | 2001-03-27 | Stabilizing fluorine etching of low-k materials |
| US09/817,056 | 2001-03-27 |
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| US (2) | US7132363B2 (zh) |
| EP (1) | EP1374300A2 (zh) |
| JP (1) | JP2004527909A (zh) |
| KR (1) | KR100774601B1 (zh) |
| CN (1) | CN100449730C (zh) |
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- 2001-12-19 JP JP2002575997A patent/JP2004527909A/ja active Pending
- 2001-12-19 KR KR1020037012634A patent/KR100774601B1/ko not_active IP Right Cessation
- 2001-12-19 CN CNB018230911A patent/CN100449730C/zh not_active Expired - Lifetime
- 2001-12-19 EP EP01998081A patent/EP1374300A2/en not_active Ceased
- 2001-12-19 WO PCT/US2001/049825 patent/WO2002078060A2/en active Application Filing
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Also Published As
| Publication number | Publication date |
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| US7132363B2 (en) | 2006-11-07 |
| WO2002078060A2 (en) | 2002-10-03 |
| JP2004527909A (ja) | 2004-09-09 |
| CN100449730C (zh) | 2009-01-07 |
| TW533535B (en) | 2003-05-21 |
| EP1374300A2 (en) | 2004-01-02 |
| KR20030087653A (ko) | 2003-11-14 |
| US20070035025A1 (en) | 2007-02-15 |
| KR100774601B1 (ko) | 2007-11-09 |
| AU2002249838A1 (en) | 2002-10-08 |
| WO2002078060A3 (en) | 2003-02-06 |
| US20020140101A1 (en) | 2002-10-03 |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090107 |