CN101038907A - 形成互连结构的方法及其形成的互连结构 - Google Patents
形成互连结构的方法及其形成的互连结构 Download PDFInfo
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- CN101038907A CN101038907A CNA2007101359577A CN200710135957A CN101038907A CN 101038907 A CN101038907 A CN 101038907A CN A2007101359577 A CNA2007101359577 A CN A2007101359577A CN 200710135957 A CN200710135957 A CN 200710135957A CN 101038907 A CN101038907 A CN 101038907A
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- seed layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/308,284 US7276796B1 (en) | 2006-03-15 | 2006-03-15 | Formation of oxidation-resistant seed layer for interconnect applications |
US11/308,284 | 2006-03-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101038907A true CN101038907A (zh) | 2007-09-19 |
CN100495698C CN100495698C (zh) | 2009-06-03 |
Family
ID=38516962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2007101359577A Expired - Fee Related CN100495698C (zh) | 2006-03-15 | 2007-03-13 | 形成互连结构的方法及其形成的互连结构 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7276796B1 (zh) |
JP (1) | JP2007251164A (zh) |
CN (1) | CN100495698C (zh) |
Cited By (7)
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---|---|---|---|---|
CN102341903A (zh) * | 2009-05-19 | 2012-02-01 | 国际商业机器公司 | 用于互连应用的冗余金属阻挡结构 |
CN102437144A (zh) * | 2011-12-06 | 2012-05-02 | 西安交通大学 | 一种Ru-RuO/Ru-Ge-Cu自形成双层非晶扩散阻挡层及其制备方法 |
CN102576603A (zh) * | 2010-03-31 | 2012-07-11 | 日东电工株式会社 | 永久磁铁及永久磁铁的制造方法 |
CN103855131A (zh) * | 2012-11-30 | 2014-06-11 | 财团法人工业技术研究院 | 自我生长的阻挡层结构及使用该结构的沟槽式半导体结构 |
CN104377162A (zh) * | 2013-08-13 | 2015-02-25 | 朗姆研究公司 | 用于穿硅通路金属化的粘合层 |
CN106057772A (zh) * | 2015-04-16 | 2016-10-26 | 台湾积体电路制造股份有限公司 | 互连结构及其形成方法 |
CN110137135A (zh) * | 2019-05-30 | 2019-08-16 | 上海华虹宏力半导体制造有限公司 | 形成导电层的方法 |
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US7122898B1 (en) * | 2005-05-09 | 2006-10-17 | International Business Machines Corporation | Electrical programmable metal resistor |
US7276796B1 (en) * | 2006-03-15 | 2007-10-02 | International Business Machines Corporation | Formation of oxidation-resistant seed layer for interconnect applications |
JP2007258390A (ja) * | 2006-03-23 | 2007-10-04 | Sony Corp | 半導体装置、および半導体装置の製造方法 |
KR100790452B1 (ko) * | 2006-12-28 | 2008-01-03 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법 |
JP2008300652A (ja) * | 2007-05-31 | 2008-12-11 | Toshiba Corp | 半導体装置の製造方法 |
US8058164B2 (en) * | 2007-06-04 | 2011-11-15 | Lam Research Corporation | Methods of fabricating electronic devices using direct copper plating |
US7867895B2 (en) * | 2007-09-20 | 2011-01-11 | International Business Machines Corporation | Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric |
JP5285898B2 (ja) * | 2007-12-17 | 2013-09-11 | Jx日鉱日石金属株式会社 | 銅拡散防止用バリア膜、同バリア膜の形成方法、ダマシン銅配線用シード層の形成方法及びダマシン銅配線を備えた半導体ウェハー |
KR100924865B1 (ko) * | 2007-12-27 | 2009-11-02 | 주식회사 동부하이텍 | 반도체 소자의 금속배선 형성방법 |
EP2237312B1 (en) * | 2008-03-19 | 2015-08-19 | JX Nippon Mining & Metals Corporation | Electronic member wherein barrier-seed layer is formed on base |
CN101911265B (zh) * | 2008-03-19 | 2012-07-04 | 日矿金属株式会社 | 在基材上形成有阻挡层兼种子层的电子构件 |
US7951414B2 (en) * | 2008-03-20 | 2011-05-31 | Micron Technology, Inc. | Methods of forming electrically conductive structures |
US8679970B2 (en) * | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
KR100978859B1 (ko) * | 2008-07-11 | 2010-08-31 | 피에스케이 주식회사 | 할로우 캐소드 플라즈마 발생장치 및 할로우 캐소드플라즈마를 이용한 대면적 기판 처리장치 |
KR101046335B1 (ko) * | 2008-07-29 | 2011-07-05 | 피에스케이 주식회사 | 할로우 캐소드 플라즈마 발생방법 및 할로우 캐소드플라즈마를 이용한 대면적 기판 처리방법 |
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US10381266B2 (en) | 2012-03-27 | 2019-08-13 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
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US8871639B2 (en) | 2013-01-04 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
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US9953984B2 (en) | 2015-02-11 | 2018-04-24 | Lam Research Corporation | Tungsten for wordline applications |
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-
2006
- 2006-03-15 US US11/308,284 patent/US7276796B1/en active Active
-
2007
- 2007-03-08 JP JP2007058015A patent/JP2007251164A/ja active Pending
- 2007-03-13 CN CNB2007101359577A patent/CN100495698C/zh not_active Expired - Fee Related
- 2007-08-15 US US11/839,260 patent/US7585765B2/en not_active Expired - Fee Related
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102341903A (zh) * | 2009-05-19 | 2012-02-01 | 国际商业机器公司 | 用于互连应用的冗余金属阻挡结构 |
US8592306B2 (en) | 2009-05-19 | 2013-11-26 | International Business Machines Corporation | Redundant metal barrier structure for interconnect applications |
CN102341903B (zh) * | 2009-05-19 | 2014-10-29 | 国际商业机器公司 | 用于互连应用的冗余金属阻挡结构 |
CN102576603A (zh) * | 2010-03-31 | 2012-07-11 | 日东电工株式会社 | 永久磁铁及永久磁铁的制造方法 |
CN102437144A (zh) * | 2011-12-06 | 2012-05-02 | 西安交通大学 | 一种Ru-RuO/Ru-Ge-Cu自形成双层非晶扩散阻挡层及其制备方法 |
CN103855131A (zh) * | 2012-11-30 | 2014-06-11 | 财团法人工业技术研究院 | 自我生长的阻挡层结构及使用该结构的沟槽式半导体结构 |
CN104377162A (zh) * | 2013-08-13 | 2015-02-25 | 朗姆研究公司 | 用于穿硅通路金属化的粘合层 |
CN104377162B (zh) * | 2013-08-13 | 2017-05-10 | 朗姆研究公司 | 用于穿硅通路金属化的粘合层 |
CN106057772A (zh) * | 2015-04-16 | 2016-10-26 | 台湾积体电路制造股份有限公司 | 互连结构及其形成方法 |
CN106057772B (zh) * | 2015-04-16 | 2018-11-30 | 台湾积体电路制造股份有限公司 | 互连结构及其形成方法 |
CN110137135A (zh) * | 2019-05-30 | 2019-08-16 | 上海华虹宏力半导体制造有限公司 | 形成导电层的方法 |
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US20070275557A1 (en) | 2007-11-29 |
JP2007251164A (ja) | 2007-09-27 |
US7585765B2 (en) | 2009-09-08 |
CN100495698C (zh) | 2009-06-03 |
US20070216031A1 (en) | 2007-09-20 |
US7276796B1 (en) | 2007-10-02 |
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