CN100568533C - 双栅场效应晶体管及其形成方法 - Google Patents
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Abstract
本发明公开了具有亚光刻源区和漏区的横向双栅FET结构。亚光刻源区和漏区被牺牲间隔件所限定。使用传统的硅工艺对亚光刻源区和漏区制造自对准金属半导体合金和金属接触。
Description
技术领域
[0001]本发明涉及半导体器件的接触，更确切地说，涉及具有亚光刻尺度(sub-lithographic dimension)的金属半导体合金(诸如，比如，硅化物或锗化物)接触，其用于金属氧化物半导体场效应管(MOSFET)的源区和漏区。本发明还涉及制造用于MOSFET的源区和漏区的亚光刻接触的方法。
背景技术
[0002]双栅MOSFET比传统单栅MOSFET具有更好的等比例缩放特性。两个栅极优选地由自对准工艺来限定以最小化寄生电容。这样的结构的例子被描述于，比如，Solomon等人的名为“Method formaking single and double gate field effect transistors with sidewallsource-drain contacts”的美国专利5,773,331中，以及Cohen等人的名为“Double-gate FET with planarized surfaces and self-alignedsilicides”的美国专利6,642,115中。
[0003]附图1显示了一般的双栅MOSFET结构其包含背栅A103、背栅电介质A104、一般为硅的半导体、沟道A105、顶栅电介质A107，以及顶栅A108。硅化物A109和A114被形成于顶栅A108以及源区和漏区A115上方。背栅A103的有用部分是与沟道区A105重叠的那段。该段的长度在附图1中被标注为Lbg。该段中在背栅A103和沟道A105之间的电容为Cbg。这是有用电容，因为它使得背栅能够控制沟道中的电荷。背栅A103横向延伸两段长度Lext_s和Lext_d。长度Lext_s(以及类似地Lext_d)主要由源区/漏区A115的横向延伸的尺寸加上等于间隔件(spacer)A111的印迹(footprint)的少量增量所确定。背栅A103与源区和漏区A115之间的电容分别为Cext_s和Cext_d。该电容，也被认为是背栅到源/漏的重叠电容，是寄生电容并且需要被最小化以提高半导体器件的总体速度。
[0004]为了减少对背栅的重叠电容，源区和漏区的横向尺度需要被最小化。比如，在Solomon等人的专利中，硅加高源-漏(siliconraised source-drain)间隔件被形成使得重叠面积被减少为间隔件印迹的重叠面积。
[0005]然而，难以通过后续的金属化来与亚光刻源区和漏区接触。“亚光刻”，是指尺度其小于能被传统光刻限定的最小特征尺寸。
[0006]由于前述原因，所以需要提供具有减小的源/漏到背栅重叠电容的双栅MOSFET。本发明提供一种方法，其可以通过使源区和漏区的尺寸像间隔件的印迹一样小来减少重叠电容。另外，本发明还提供一种对这些亚光刻区形成金属半导体合金(诸如，例如硅化物或锗化物)并金属化的技术。
发明内容
[0007]本发明提供具有亚光刻尺寸(约0.1微米量级或更少)的源区和漏区的平面双栅FET，对于该具有亚光刻尺寸的源区和漏区制造了自对准金属半导体合金(诸如，例如硅化物或锗化物)和金属接触。
[0008]本发明的结构和方法相对于现有技术具有若干优点。第一，本发明最小化了源区、漏区与背栅之间电容的寄生分量。第二，本发明提供了自对准硅化物(SALICIDE)工艺，用于在源区、漏区和顶栅上方形成硅化物(或者其它金属半导体合金)区，其避免了光刻。第三，本发明的方法将金属接触形成到源区和漏区的金属半导体合金(诸如，例如硅化物或锗化物)区而无需使用光刻。
[0009]在本发明的第一方面中，提供一种半导体结构诸如双栅场效应晶体管(FET)，包括：
单晶半导体沟道；
位于半导体沟道两侧上的顶栅和背栅，用于控制通过半导体沟道的电流；
半导体沟道邻接的源区和漏区，所述源区和漏区具有由间隔件印迹限定的横向尺寸；
金属半导体合金区，位于源区、漏区、以及非必要地、顶栅上方；以及
连接到所述金属半导体合金区边缘的掩埋金属线(buried metalline)。
本发明还提供另一种双栅场效应晶体管，包括：单晶Si沟道；Si沟道两侧上的顶栅和背栅，用于控制通过Si沟道的电流；Si沟道邻接的源区和漏区，所述源区和漏区具有由间隔件印迹限定的横向尺寸；形成于所述源和漏的顶上的加高源和加高漏；在源区、漏区、以及顶栅上方的硅化物区；连接到所述硅化物区的边缘的掩埋金属线；以及连接到掩埋金属线的金属短截线。
[0010]在一些实施方案中，本发明结构还包括连接到掩埋金属线的金属短截线(metal stud)。
[0011]在本发明的第二方面，描述了用于制造半导体结构诸如具有亚光刻源区和漏区的双栅FET的方法。本发明的方法中所采用的初始结构包括单晶半导体(优选地含Si)沟道，其具有位于沟道顶面和底面上的栅电介质。底栅电介质下方的导电膜形成了器件的背栅。另一个位于顶栅电介质上的导电膜被图案化以形成器件的顶栅。与顶栅邻接地形成侧壁间隔件。源区和漏区于是由与顶栅邻接地形成的侧壁间隔件的印迹所界定。这通过从除了顶栅和侧壁间隔件掩蔽蚀刻的地方外对半导体沟道材料的各处进行覆盖式蚀刻(blanket etch)来实现。然后通过氧化物沉积并接着化学机械抛光(CMP)将氧化物的顶面与顶栅的顶面对齐，将该结构平坦化。氧化物被凹进(recess)到顶栅的上表面下方。侧壁间隔件随后被区除以暴露出器件源区和漏区的顶面。
[0012]在本发明的优选实施方案中，源区和漏区通过选择性外延被增厚。利用最初在半导体沟道被覆盖式蚀刻修整(trim)之前限定了半导体沟道的掩模(这一般是被用于限定浅槽隔离的掩模)，来沉积和图案化覆盖式金属膜。然后，结构通过第二氧化物沉积和CMP被平坦化使得顶栅的上表面被CMP工艺暴露。退火使金属膜与源区和漏区(以及栅的顶面)反应而形成金属半导体合金诸如硅化物或锗化物。未反应的金属留在平坦化氧化物下方和顶栅电介质的侧壁上。顶栅侧壁上的未反应的金属相对于金属半导体合金被选择性地蚀刻。掩埋在平坦氧化物下面的未反应的金属被保护不受蚀刻，并与金属半导体合金在源区和漏区上方保持接触。然后对未反应的金属使用通孔短截线(vias stud)(CA掩模)制作源/漏接触。
[0013]概括地说，如上所述的本发明形成双栅场效应晶体管的方法，包括以下步骤：形成包括在其顶面和底面上具有栅电介质的单晶半导体膜、底栅、以及具有电介质侧壁间隔件的顶栅的结构；形成与所述顶栅邻接的牺牲间隔件；通过蚀刻所述单晶半导体膜的未掩蔽区域来限定亚光刻源区和漏区；在所述结构上配备第一平坦化电介质；将所述第一平坦化电介质凹进到所述顶栅的上表面下方；去除所述牺牲间隔件以暴露出所述亚光刻界定的源区和漏区的顶面；利用金属膜在所述源区和漏区的所述暴露表面上形成金属半导体合金，其中所述金属膜的未形成金属半导体合金的部分位于第一平坦化电介质的顶上以及电介质侧壁间隔件上方；将第二平坦化电介质至少沉积在所述金属半导体合金上方；以及选择性地蚀刻所述电介质侧壁间隔件上方的所述金属。
附图说明
[0014]附图1为表示了现有技术的双栅FET(横截面视图)，其中显示了背栅到沟道的电容和背栅到源/漏的寄生电容。
[0015]附图2到9为表示本发明的用于制造具有亚光刻源区和漏区的双栅FET的基本处理步骤的示意图。
[0016]附图10为表示用于制造本发明的具有亚光刻源区和漏区的双栅FET的基本掩模组(basic mask set)的示意图(俯视图)。
具体实施方式
[0017]本发明提供了具有亚光刻源区和漏区的双栅FET及其制造方法，现在将通过下列讨论进行更详细地描述。在该讨论中，将参考表示本发明实施方案的多个附图。因为本发明实施方案的附图是用于图解目的，所以其中所含结构不是按比例绘制。
[0018]在下列描述中，提出了很多具体细节，诸如特定结构、组件、材料、尺寸、处理步骤和技术，以为本发明提供更透彻的理解。然而，本领域普通技术人员将知道本发明可以用没有这些特定细节的可行的替代工艺来实现。在其它实例中，众所周知的结构或处理步骤没有被详细描述以避免对本发明造成妨碍。
[0019]要理解的是当要素如层、区域、或衬底被称为位于其它要素“上”或“上方”时，它可以直接在其它要素上或者可以也存在居间要素。相反，当要素被称为“直接”在另一个要素“上”或“上方”时，不存在居间要素。也要理解当要素被称为在另一个要素“下”或“下方”时，它可以直接在其它要素下或下方，或者也可以存在居间要素。相反，当要素被称为“直接”在另一个要素“下”或“下方”，则不存在居间要素。
[0020]如上所述，本发明提供具有亚光刻尺寸(为大约0.1微米量级或更少)的源和漏区的平面双栅MOSFET其，对该源和漏区制造了自对准金属半导体合金(诸如，例如硅化物或锗化物)和金属接触。本发明最小化了源区、漏区与背栅之间电容的寄生分量，它提供了自对准金属-半导体合金硅化物(SALICIDE)工艺，用于在源区、漏区和顶栅上方形成硅化物(或者其它金属半导体合金)区，其避免了光刻，并且它对源区和漏区的金属半导体合金(诸如，比如，硅化物或锗化物)区形成金属接触而不用光刻。
[0021]本发明的方法的基本处理步骤如附图2到9中所示，而附图10显示了被用在本发明的用于制造本发明平面双栅FET的方法中的掩模组。参考附图2，表示了本发明中所采用的初始结构。附图2中所示的初始结构包括衬底，该衬底包括半导体晶片101、掩埋绝缘体102、具有背栅电介质膜104的背栅膜103、以及单晶半导体膜(SOI)105。衬底一般通过众所周知的晶片结合(wafer bonding)和层转移(layer transfer)技术来制造。
[0022]根据本发明，半导体晶片101和单晶半导体膜105由相同或不同的、优选相同的半导体材料组成。术语“半导体材料”是指任何具有半导体特性的材料，其包括例如Si、SiGe、SiC、SiGeC、Ge、GaAs、InAs、InP以及其它III/V或II/VI族化合物半导体。优选地，半导体晶片101和单晶半导体膜105的半导体材料为含Si半导体，最优选Si。
[0023]在附图2中所示初始结构中，掩埋绝缘体102包括氧化物、氮化物、氮氧化物或者其任意组合，最优选氧化物。背栅电介质104包括绝缘材料，包括氧化物、氮化物、氮氧化物或者它们的组合和多层。一般来说，背栅电介质104包括SiO2。背栅103包括任何导电材料，其包括用n或p型杂质掺杂为大于或等于约5E19原子/cm3的掺杂浓度的多晶硅或SiGe、诸如例如Al、W、Mo的金属、金属合金、金属硅化物、或者金属氮化物。
[0024]膜103到105通过使用传统的浅槽隔离(STI)工艺被图案化为被隔离区域(其中之一如附图2所示)。通过浅槽隔离区106将每个被隔离区域和与其相邻的被隔离区域隔离开。浅槽隔离区106一般用槽电介质材料诸如例如氧化物来填充。
[0025]使用众所周知的工艺，在单晶半导体膜105上方制造包括顶栅电介质107、顶栅108、栅帽层(gate cap)120和侧壁间隔件110的顶栅叠层。顶栅108两侧的源区和漏区通过向单晶膜105中进行自对准离子注入而被形成。注意，顶栅108可以包括与背栅薄膜103相同或不同的导电材料。同样，顶栅电介质107可以包括与背栅电介质膜104相同或不同的绝缘体。
[0026]栅帽层120包括绝缘材料，其包括例如氧化物、氮化物、氮氧化物或者它们的多层。一般来说，栅帽层120包括氧化物诸如SiO2。根据本发明，侧壁间隔件110包括氧化物诸如SiO2。
[0027]参考附图3，包括氮化硅的牺牲间隔件111被形成于栅叠层两侧的每一侧上。牺牲间隔件111通过沉积和蚀刻来形成。每个牺牲间隔件111的印迹的宽度稍后将限定源区和漏区的横向尺寸。如附图4中所示，反应离子蚀刻(RIE)被用于从未被栅叠层或牺牲间隔件111掩蔽的区域蚀刻掉单晶半导体膜105。在附图4中，附图标记122是被蚀刻区域。半导体蚀刻对于电介质诸如二氧化硅(SiO2)和氮化硅(Si3N4)是选择性的。比如，利用HBr化学的RIE可以具有一般大于1∶100的蚀刻选择性(即，氧化物蚀刻比半导体蚀刻慢100倍)。高选择性还使得区域122中的蚀刻能够止步于背栅电介质104上。
[0028]参考附图5，绝缘体112诸如氧化物或硅酸盐玻璃被覆盖式沉积，并且应用化学机械抛光(CMP)来平坦化表面。绝缘体112被向下抛光到栅帽层120的上表面。然后绝缘体112被进一步凹进到栅帽层120的上表面下方。栅帽层120也被去除以暴露出顶栅108的顶面。
[0029]参考附图6，通过蚀刻选择性地去除牺牲间隔件111以暴露出残留单晶半导体膜105的顶面。因为单晶半导体膜105一般被制造得较薄(大约小于或等于30nm量级)以实现双栅操作，所以暴露的单晶半导体一般必须在硅化物形成(silicide formation)之前被增厚。单晶半导体膜105的暴露部分通过选择性外延被增厚(即，只在半导体薄膜105的暴露表面之上而不在电介质表面上方沉积附加的半导体材料150)。附加的半导体材料150有时候被称为加高源/漏区，因为它延伸(增厚)了器件源区和漏区。离子注入一般被用于掺杂加高源区和漏区。
[0030]能够与半导体150反应而形成金属半导体合金(比如，当使用硅时为硅化物，或者当使用锗时为锗化物)的金属113被覆盖式地沉积于该结构上方。这种能与半导体150反应而形成硅化物(或锗化物)的金属的例子包括，例如，Ni、Ti、Pt、W、Co或者它们的多层或组合。一般来说，金属113为Ni、Pt和Co中的一种。利用稍大于限定被隔离区域的掩模201的掩模202(见附图10)将金属113图案化，或者只用STI掩模201将金属113图案化。附图10显示了覆盖于顶栅掩模203、底栅掩模204、和STI掩模201上方的掩模202的布图。
[0031]参考附图7，通过使金属113与半导体150、半导体105的顶部(非必需的)以及顶栅108(假设为含Si栅)的顶面发生反应来形成金属半导体合金114。金属113的未与半导体表面相接触的部分、比如间隔件110上方和绝缘体112上方的部分不被转化为金属半导体合金。在本发明的优选实施方案中，金属半导体合金114为NiSi、TiSi2、CoSi2和PtSi2中的一种。金属与半导体表面的反应一般通过晶片的快速热退火(RTA)来完成。绝缘体115诸如例如氧化物或硅酸盐玻璃被覆盖式地沉积于该结构之上。该结构通过CMP来抛光，使得位于顶栅108顶上的金属半导体合金114被暴露。还可以在金属113与半导体表面反应之前沉积绝缘体115，然后在电介质115覆盖着金属113的状态下执行RTA步骤。
[0032]参考附图8，间隔件110上方的未反应的金属113相对于金属半导体合金114和绝缘体被选择性蚀刻。绝缘体112上方的未反应的金属113不被蚀刻，因为它被绝缘体115保护。残留的未反应的金属113在结构内形成被连接到源区和漏区的边缘的掩埋金属线。
[0033]参考附图9，绝缘体117诸如氧化物或硅酸盐玻璃被覆盖式地沉积于结构之上。绝缘体117也填充由被蚀刻金属113留下的间隙116。CMP被用来平坦化结构。到源、漏和栅的接触通孔被光刻和RIE限定，并被用形成金属短截线118的金属填充。金属短截线118包括Al、W、Cu、AlCu或其它类似导电金属。
[0034]为了完成器件制造，金属线126和128被形成以分别接触源区/漏区和顶栅。
[0035]虽然本发明已就其优选实施方案被具体地显示和描述，但是本领域技术人员会理解可以在不离开本发明的精神和范围下作出前述和其它在形式和细节上的改变。因此要注意本发明不限于所示和所述的具体形式和细节，而是属于所附权利要求的范围。
Claims (20)
1.一种双栅场效应晶体管，包括：
单晶半导体沟道；
位于半导体沟道两侧上的顶栅和背栅，用于控制通过半导体沟道的电流；
半导体沟道邻接的源区和漏区，所述源区和漏区具有由间隔件印迹限定的横向尺寸；
至少位于源区、漏区上方的金属半导体合金区；以及
连接到所述金属半导体合金区边缘的掩埋金属线。
2.如权利要求1所述的双栅场效应晶体管，还包括连接到掩埋金属线的金属短截线。
3.如权利要求1所述的双栅场效应晶体管，其中，所述半导体沟道包括含Si半导体，所述金属半导体合金包括硅化物。
4.如权利要求1所述的双栅场效应晶体管，其中，所述顶栅和所述背栅由掺杂的多晶硅或掺杂的SiGe组成。
5.如权利要求1所述的双栅场效应晶体管，还包括，位于所述顶栅与所述半导体沟道之间的顶栅电介质，以及位于所述背栅与所述半导体沟道之间的背栅电介质。
6.如权利要求1所述的双栅场效应晶体管，其中，所述掩埋金属线包括Ni、Ti、Pt、W和Co中的一种。
7.如权利要求1所述的双栅场效应晶体管，其中，所述金属半导体合金是NiSi、CoSi2、TiSi2和PtSi2中的一种。
8.如权利要求1所述的双栅场效应晶体管，还包括形成于所述源和漏的顶上的加高源和加高漏。
9.如权利要求2所述的双栅场效应晶体管，其中，所述金属短截线包括Al、W、Cu或AlCu。
10.一种双栅场效应晶体管，包括：
单晶Si沟道；
Si沟道两侧上的顶栅和背栅，用于控制通过Si沟道的电流；
Si沟道邻接的源区和漏区，所述源区和漏区具有由间隔件印迹限定的横向尺寸；
形成于所述源和漏的顶上的加高源和加高漏；
在源区、漏区、以及顶栅上方的硅化物区；
连接到所述硅化物区的边缘的掩埋金属线；以及
连接到掩埋金属线的金属短截线。
11.如权利要求10所述的双栅场效应晶体管，其中，所述顶栅和所述背栅包括掺杂的多晶硅或掺杂的SiGe。
12.如权利要求10所述的双栅场效应晶体管，还包括：位于所述顶栅与所述Si沟道之间的顶栅电介质，以及位于所述背栅与所述Si沟道之间的背栅电介质。
13.如权利要求10所述的双栅场效应晶体管，其中，所述掩埋金属线包括Ni、Ti、Pt、W和Co中的一种。
14.如权利要求10所述的双栅场效应晶体管，其中，所述硅化物为NiSi、CoSi2、TiSi2、和PtSi2中的一种。
15.如权利要求10所述的双栅场效应晶体管，其中，所述金属短截线包括Al、W、Cu或AlCu。
16.一种形成双栅场效应晶体管的方法，包括以下步骤：
形成包括在其顶面和底面上具有栅电介质的单晶半导体膜、底栅、以及具有电介质侧壁间隔件的顶栅的结构；
形成与所述顶栅邻接的牺牲间隔件；
通过蚀刻所述单晶半导体膜的未掩蔽区域来限定亚光刻源区和漏区；
在所述结构上配备第一平坦化电介质；
将所述第一平坦化电介质凹进到所述顶栅的上表面下方；
去除所述牺牲间隔件以暴露出所述亚光刻界定的源区和漏区的顶面；
利用金属膜在所述源区和漏区的所述暴露表面上形成金属半导体合金，其中所述金属膜的未形成金属半导体合金的部分位于第一平坦化电介质的顶上以及电介质侧壁间隔件上方；
将第二平坦化电介质至少沉积在所述金属半导体合金上方；以及
选择性地蚀刻所述电介质侧壁间隔件上方的所述金属。
17.如权利要求16所述的方法，还包括形成到被所述第二平坦化电介质覆盖的所述金属的通孔。
18.如权利要求16所述的方法，还包括将所述源区和所述漏区增厚以形成加高源和漏。
19.如权利要求18所述的方法，其中，所述增厚步骤是由选择性外延提供的。
20.如权利要求16所述的方法，其中，所述金属膜的未转化为所述金属半导体合金、且被第二平坦化电介质所保护的部分形成被连接到所述源区和漏区的边缘的掩埋金属线。
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Also Published As
| Publication number | Publication date |
|---|---|
| US7888742B2 (en) | 2011-02-15 |
| CN101221985A (zh) | 2008-07-16 |
| US20080164528A1 (en) | 2008-07-10 |
| US8557665B2 (en) | 2013-10-15 |
| TW200908331A (en) | 2009-02-16 |
| US20100047984A1 (en) | 2010-02-25 |
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