CN100559562C - 使用干式刻蚀工艺以有效率地图案化凸块下金属化层的技术 - Google Patents

使用干式刻蚀工艺以有效率地图案化凸块下金属化层的技术 Download PDF

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CN100559562C
CN100559562C CNB2006800278504A CN200680027850A CN100559562C CN 100559562 C CN100559562 C CN 100559562C CN B2006800278504 A CNB2006800278504 A CN B2006800278504A CN 200680027850 A CN200680027850 A CN 200680027850A CN 100559562 C CN100559562 C CN 100559562C
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layer
patterning
technology
underbump metallization
etch process
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CN101248521A (zh
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F·屈兴迈斯特
A·普拉茨
G·容尼克尔
K·修瑞
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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Abstract

藉由以干式刻蚀工艺(111)为基础图案化凸块下金属化层(underbump metallization layer)堆栈(105)，与涉及高度复杂的湿式化学刻蚀工艺之传统技术相比可达到显著的优点。在特定的具体例中，凸块下金属化层堆栈(105)的钛钨层或任何其它适当最后层(last layer)(105B)可以使用基于氟(fluorine-based)的化学及作为物理成分的氧之等离子体刻蚀工艺(107)为基础加以刻蚀。再者，适当的清洁工艺(110、113)可在该基于等离子体(107)的图案化工艺之前或之后执行以去除粒子(109)及残余物(112)。

Description

使用干式刻蚀工艺以有效率地图案化凸块下金属化层的技术
技术领域
本发明大体上系有关集成电路的形成，且更特定的是，有关用于形成包括凸块的接触层之工艺流程，其中该接触层系配置以提供接触区域，以用于使适当形成的封装件或载体基片直接地附接于承载一个或多个集成电路之晶粒(die)。
背景技术
在制造集成电路时，通常必须封装芯片并且提供用于连接芯片电路与周边的导脚(lead)及端子(terminal)。在某些封装技术中，芯片、芯片封装件或其它适当单元可藉由焊球(solder ball)(由所谓的焊料凸块(solder bump)形成)连接，该等焊球形成于该等单元中之至少一者的对应层上，本文中将该对应层称之为接触层，例如形成于微电子芯片的介电钝化层(dielectric passivation layer)上。为了连接该微电子芯片与对应的载体(carrier)，要连接的两个各别单元(亦即，包含例如多数集成电路的微电子芯片、与对应的封装件)的表面上都形成有适当的垫(pad)配置以便在该等单元中之至少一者上，例如在该微电子芯片上，所设置的焊料凸块经回焊(reflowing)之后使该两个单元电性连接。在其它技术中，可能必须形成欲连接至对应配线(wire)的焊料凸块，或可使该等焊料凸块与作为散热件(heat sink)的另一基片之对应垫区域接触。因此，可能必须形成可分布于整个芯片区域上的大量焊料凸块，藉以提供，举例来说，现代微电子芯片所需的I/O能力，该等微电子芯片通常包括复杂的电路，例如微处理器及储存电路等，及/或包括形成完整复杂电路系统的多数集成电路。
为了在对应垫上设置数百个或数千个机械上固定良好的焊料凸块，该等焊料凸块的附接程序需要细心的设计，因为整个装置可能只因为其中一焊料凸块失效而变成无用。因为这个理由，一般都在该等焊料凸块与包括该垫配置的下方基片或芯片之间设置一个或多个细心选择的层。除了此重要的角色以外，这些界面层，在此亦称为凸块下金属化层，可在赋予该焊料凸块的充分机械黏着力给下方的垫及周围的钝化材料时担任一角，该凸块下金属化必须符合有关扩散特性与电流传导性的进一步必备条件。有关前面的议题，凸块下金属化层必须提供适当的扩散阻障物(diffusion barrier)以防止焊料(经常为铅(Pb)与锡(Sn)的混合物)攻击该芯片的下方金属化层并且藉以破坏或负面地影响彼等的功能性。再者，焊料(例如铅)迁移至其它敏感的装置区域，例如进入介电质，其中铅的放射性衰变也可能显著地影响该装置效能，必须藉由该凸块下金属化而有效地予以抑制。有关电流传导性，该凸块下金属化，其担任该焊料凸块与该芯片的下方金属化层之间的互连件(interconnect)，必须展现不会不当地提高该金属化垫/焊料凸块系统的整体电阻之厚度及指定电阻。此外，该凸块下金属化将担任该焊料凸块材料电镀期间的电流分布层。电镀为目前较佳的沉积技术，因为焊料凸块材料的物理气相沉积，其在此技艺中也有使用，需要复杂的掩模技术以避免当掩模接触到热金属蒸气时该掩模的热膨胀所引起的任何失准(misalignment)。再者，在该沉积工艺完成以后很难去除该金属掩模而不损及该等焊垫(solder bad)，特别是当加工大片芯片或相邻焊垫之间的间距(pitch)减小时。
尽管掩模亦用于电镀沉积方法中，但是此技术与气化(evaporation)方法不同之处在于该掩模系使用光微影法(photolithography)产生，藉以避免由物理气相沉积技术引发之以上确认的问题。然而，电镀需要黏附于(除了其上必须形成焊料凸块的垫以外)主要为绝缘性的基片之连续及均匀的电流分布层。由此，该凸块下金属化也必须符合有关均匀电流分布的严苛设定束缚，因为在该镀覆工艺的期间任何不均匀度都可能影响焊料凸块及回焊该等焊料凸块之后所得焊球的最终结构就例如高度不均匀性来看，其遂可转变成最终获得的电连接及其机械整合度的波动。
在该等焊料凸块形成之后，该凸块下金属化必须被图案化以便电性绝缘个别的焊料凸块彼此。凸块下金属化所得的岛(island)，典型地藉由高度复杂的等向性(isotropic)刻蚀工艺获得(该等刻蚀工艺包括利用复杂化学的湿式化学及/或电化学刻蚀程序)，也显著地决定该等焊球的功能性及结构，因为该刻蚀化学可能导致该等焊料凸块的底刻蚀(under-etching)，该等焊料凸块在该湿式化学刻蚀工艺的期间作为掩模。因此，不同程度的底刻蚀可能导致与各焊料凸块相关联之所得凸块下金属化岛的不同大小，藉以显著地影响回焊之后的焊球结构，因为该高度可湿性(highly wettable)凸块下金属化实质上决定该焊料的流动性质，并且从而决定该焊球之最终获得的大小及因而其高度。再者，用于图案化该凸块下金属化之一个或多个次层(sub-layer)，例如钛钨(TiW)层(由于就阻障及黏着的观点来看有优异的特性所以其经常用作为形成于该介电材料上的第一层)，的湿式化学刻蚀工艺可展现与凸块图案有关的刻蚀速率。也就是说，该刻蚀速率可取决于各晶粒内的凸块配置方式及在该基片上的个别晶粒之间的X-方向与Y-方向的距离。由此，有关实际上可用的凸块配置方式，该与图案有关的刻蚀速率可能加诸严苛的限制，藉以可能限制有关实际上可用的晶粒面积之晶粒的I/O能力及/或散热。
再者，有些湿式化学刻蚀工艺倾向与凸块材料发生显著地交互作用，其中该凸块材料可能被去除及/或化学反应可能使凸块材料转变成不欲的化合物。因而，在该湿式化学刻蚀工艺之后、在该湿式化学刻蚀工艺的期间、或在用于去除任何不欲化合物的后继清洁工艺的期间，可能损失显著量的凸块材料，此可能造成提高的制造成本，尤其是在使用昂贵的焊料时，例如具有低α衰变速率的锡/铅。
再者，由于该湿式刻蚀化学及刻蚀调制法(recipe)的复杂度，在该凸块下金属化之图案化的期间可能需要先进的终点(endpoint)探测程序，因此额外地造成工艺复杂度。在有些例子中，该化学与该湿式化学刻蚀工艺所需的添加物之提供，及该湿式化学副产物的处理，也可能使整个图案化工艺增加相当多成本，其中专用工艺工具的保养及占地面积(floor space)也可能代表重要的成本因子。
综观以上说明的情况，就形成包括焊料凸块的接触层来说需要改良的技术，其中避免以上确认的问题之一者或多者或至少显著地降低其效应。
发明内容
下列代表本发明的简化概要，为的是提供本发明部分形态的基本认识。此概要并非本发明的彻底概观。其并非意欲确认本发明的关键或重要组件或描叙本发明的范围。其唯一的目的在于以简化的形态呈现一些概念，当作后续讨论的更详细说明的开头。
一般而言，本发明系关于形成微电子芯片的接触层之技术，其适于藉由回焊(reflowing)形成于该接触层上及中的凸块，例如焊料凸块(solder bump)，而直接地附接于对应的载体基片，其中用于图案化凸块下金属化的工艺包含干式刻蚀工艺，藉以提供用以避免经常用于传统工艺流程的湿式化学刻蚀工艺中涉及的问题之一者或多者的潜力(potential)。再者，用于设计该接触层的弹性的提高程度系藉由独创性技术来提供，因为该图案化工艺对于该等凸块之图案密度的依赖性由于基于等离子体之干式刻蚀工艺所提供的优点而显著地降低。因此，本发明提供用于节省制造成本及/或提高生产量及/或增进装置效能的潜力。
根据本发明之一个例示性具体例，一种方法包含在凸块下金属化层堆栈上所形成的多数凸块存在的情况下，藉由电化学刻蚀工艺图案化该凸块下金属化层堆栈的第一层。再者，藉由干式刻蚀工艺图案化该凸块下金属化层堆栈的第二层。
根据本发明的另一个例示性具体例，一种方法包含提供基片，该基片具有形成于其上之至少有第一层与第二层的凸块下金属化层堆栈及形成于该凸块下金属化层堆栈上方的多数凸块。再者，图案化该凸块下金属化层堆栈的该第一层以暴露出该第二层，并且接着清洁该暴露的第二层。最后，该方法包含干式刻蚀该暴露的第二层，同时用该等凸块当作刻蚀掩模。
附图说明
本发明可参照下列说明加上随附的图式而得到理解，其中相似的组件符号识别相似组件，而且其中：
第1a至1f图概略地显示根据本发明的例示性具体例之用于图案化凸块下金属化层的不同制造阶段中的半导体装置之断面图；及
图1g概略地显示其上形成有多数晶粒的基片之顶视图，彼等晶粒各自包含根据提高的设计弹性所引致的装置特定要求而设置之多数焊料凸块，该提高的设计弹性系由根据本发明的例示性具体例的干式刻蚀工艺为基础的图案化工艺提供。
尽管本发明易于实施各种不同的修饰及替代性形态，但是其具体例已藉由实例方式显示于该等图式中并且在本文中详细地加以说明。然而，要了解特定具体例在此的说明并非意欲将本发明限于所揭示的特定形态，而是相对地，本发明在于涵盖落在后附申请专利范围所界定之本发明的精神与范围以内的所有修饰、等效例及替代例。
具体实施方式
本发明的例示性具体例说明于下。为求明确起见，本说明书中并未说明实际实施方式的所有特征。当然咸明白在任何此实际具体例的发展过程中，必须做许多特定实施的决定以达到开发者的指定目标，例如遵守系统相关及商业相关的限制，彼等都将随一个个实施方式而改变。再者，咸明白此开发的努力成果可能复杂并且耗时，尽管如此也都是单方面认知本揭示内容之普通熟悉此技艺者的日常工作。
现在本发明将参照随附的图式加以说明。该等图式中概略地描述各种的结构、系统及装置仅为了达到解释的目的且以便不致混淆本发明与熟于此技艺者众所周知的细节。尽管如此，包括随附的图式系为了说明并且解释本发明的例示性实施例。本文所用的单字及词组应理解并且解释为具有与熟悉相关技艺者所理解的那些单字及词组一致的意义。本文中的术语及词组前后一致的用途意欲暗示术语或词组没有特殊定义，亦即，与熟于此技艺者所了解的普通及惯用意义不同的定义。要是术语或片语意欲具有特殊的意义，亦即，熟于此技艺者所了解以外的意义，此特殊的意义将以直接地且明确地提供该术语或词组的特殊意义的定义方式在本说明书中做明确地说明。
大体上，本发明预期接触层的形成，也就是说，在其中及上形成有多数凸块(例如焊料凸块)的层，该多数凸块用于直接连接到适当的载体基片，藉由适当设计的干式刻蚀工艺来代替凸块下金属化层图案化期间的复杂湿式化学刻蚀工艺，藉以增进装置效能并且降低制造成本。
参照第1a至1g图，现在将更详细地说明本发明的进一步例示性具体例。图1a概略地显示进步制造阶段中的半导体装置100。该半导体装置100包括基片101，其可代表主体(bulk)硅基片、绝缘体上覆硅(SOI)基片、或其上已形成有用于在其中及其上形成电路组件之一个或多个适当半导体层的任何其它载体。举例来说，该基片101可代表其上已形成有硅/锗层的适当载体、在指定位置具有不同结晶顺向(crystalline orientation)的硅层，或该基片101可包含任何类型的II-VI族或III-V族半导体化合物。在特定的具体例中，该基片101可代表基于硅(silicon-based)的基片，因为其可用于高度复杂集成电路的形成，例如进步的微处理器、储存装置、ASIC(特殊应用IC)及可能包括用于电力应用的电路之组合式数字与模拟电路等。为求方便起见，图1a中并未显示任何此等电路组件或其它微结构特征。该基片101可包含接触垫102，其可由任何适合金属形成，例如铜、铜合金、铝或任何彼等的组合。该接触垫102代表提供电性及/或热接触给该基片101内设在下方的装置区域之导热及电区域。也就是说，该半导体装置100可包含一个或多个「配线(wiring)」层或金属化层，该等层提供个别电路组件的电与热互连，其中设置该接触垫102以扮作该一个或多个金属化层与载体基片之间的「界面(interface)」，该界面提供连到该半导体装置100之周边的电性连接。
形成于基片101及接触垫102上方的为接触层108，在此制造阶段中该接触层108包含可形成在该金属化层的介电覆盖层104上之图案化的钝化层103。该钝化层103与该覆盖层104可由任何适当的介电材料形成，其中在一特定具体例中，该钝化层103可包含聚醯亚胺(polyimide)，然而，在其它例示性具体例中，可使用例如苯并环丁烯(benzocyclobutene)等的其它介电材料。形成于钝化层103上方的为凸块下金属化层堆栈105，其在凸块106(例如焊料凸块、及导电性或非导电性黏着剂之凸块等)存在的情况下被图案化。为求方便起见，将该等凸块106称之为焊料凸块，因为在许多例子中，该等凸块106包含焊料。由此，在该凸块下金属化层堆栈105图案化之后，将设置形成在个别凸块下金属化岛上的多数电性绝缘焊料凸块106。该凸块下金属化层堆栈105可包含具有不同材料组成的多数个别层，其中该层堆栈105至少包含形成在第二层105b上的第一层105a，该第二层105b依序地至少形成在该钝化层103、该覆盖层104及该接触垫102的暴露部分上。
如先前解释的，就黏着力、扩散阻障效应、导热性及导电性来看，该层堆栈105可包含多数个别层以提供所需的特性。因此，包括金、银、铜、铬、钯、铂及钨等各式各样的材料组成物可用于各种不同的组合中并且设置于不同的化合物中，其中个别层厚度也适当地适于装置要求。在一个特定具体例中，该凸块下金属化层堆栈105的第二层105b包含钛与钨的组成物，就其优异的黏着力与扩散阻断特性来看经常选用该组成物。在其它例示性具体例中，该第二层105b可包含钛、钽、钨及这些金属的任何合金，或这些金属及其合金与氮及/或硅的任何化合物。该第一层105a可包括二个或更多个次层，该等次层具有结合该凸块106的焊料而提供预期效应之材料组成物。在先进的应用中，经常可使用铜或铜合金(例如铜/铬)充当一层或多层个别层以提供高的导热性及导电性，然而，在一例示性具体例中，可额外地于该层105a中设置实质上纯的铜层，以便在该焊料凸块106当包括铅与锡的混合物时回焊之后形成铜/锡相(phase)。然而，要明白该第一层105a可由任何其它适当的导电性材料形成，取决于该焊料凸块106的组成以提供预期的热与电性特性。例如，金与其合金、银与其合金、铂与其合金、及其与氮及/或硅的化合物也都可使用。
如图1a所示用于形成该半导体装置100的典型工艺流程可包含下列工艺。根据已被接受的(well-established)工艺技术形成任何电路组件及其微结构特征之后，可形成任何金属化层以提供至各自个别的电路组件所需的层间(inter-level)与层内(intra-level)连接。在先进的应用中，可以埋在用于降低寄生电容的低-k介电材料中的高导电性金属，例如铜或铜合金，为基础来形成一个或多个金属化层。接下来，可以已被接受的工艺技术为基础在对应介电层中形成接触垫102，例如充当最后金属化层的组件，其中如先前解释的，可使用众所周知用于金属化层之形成的相似工艺技术。举例来说，可以已被接受的金属镶嵌(damascene)技术为基础形成该接触垫102，当该接触垫102实质上包含铜或铜合金时。之后，可在该铜或铜合金之顶部上形成最终或最后的金属层(未显示)，例如铝。
之后，该覆盖层104可以已被接受的等离子体强化化学气相沉积(PECVD)技术为基础而沉积并且可被图案化，接着沉积及图案化该最后金属。然后，该钝化层103的沉积可以旋涂(spin-on)技术及化学气相沉积(CVD)技术等为基础而执行。之后，该钝化层103可藉由使用已被接受的光微影及刻蚀技术加以图案化而形成暴露该接触垫102的开口。接下来，该凸块下金属化层堆栈105可以已被接受的溅镀沉积技术为基础而形成。例如，该第二层105b可沉积为钛钨组成物，因为包含钛及钨之合金已被广泛地用作为阻障层以保护各式各样应用中的芯片部件。由于钛钨的性质，亦即，其导电性及有关例如铅(Pb)及锡(Sn)原子扩散至该钛钨层下方区域的优异阻障性质，所以其为形成于该钝化层103上的第二层105b之可行的候选物。在其它的具体例中，如以上解释的其它材料可藉由溅镀沈积或任何其它适当的沉积技术，例如CVD，而形成。
之后，该第一层105a可例如以溅镀沉积及电化学沉积(例如无电镀覆)等为基础而沉积。举例来说，该第一层105a可包含形成于该第二层105b上的铬/铜层，接着为实质上纯的铜层。然而，应明白任何其它层组成及各种其它材料都可选用于该第一层105a。在凸块下金属化层堆栈105形成之后，藉由施加光阻层并且藉由已被接受的光微影及刻蚀技术图案化该光阻层以形成开口而形成阻剂掩模(未显示)，该开口的尺寸实质上相当于该焊料凸块106的大小及形状。
之后，对该基片101进行电化学沉积工艺以形成具有指定材料组成的焊料凸块106。举例来说，可使用以含有硫酸铅及硫酸锡的电解浴为基础的电镀工艺而在该阻剂掩模的开口中沉积铅及锡。应明白该阻剂掩模中的开口内沉积的焊料量实质上决定最终获得的焊球大小，所以在该凸块下金属化层堆栈105之后继图案化的期间此材料的任何去除都可能由于传统湿式化学刻蚀工艺之横跨基片的不均匀性而负面地影响最终获得的焊球之均匀性。再者，在先进的应用中，可使用昂贵的铅材料，其展现减少的放射性同位素(radioactive isotope)数目，其可能导致敏感半导体装置(例如储存芯片及微处理器等)中非所欲的软性错误(soft error)。因此，在后继湿式化学工艺期间的显著材料去除也可能造成制造成本，因为传统技术中该焊料凸块106之电化学沉积的期间最初提供的材料量可能必须列入考虑。以下将解释，根据本发明藉由基于等离子体的干式刻蚀技术之图案化工艺，尤其是该第二层105b的图案化工艺，可显著地缓和传统图案化机构中焊料凸块106之任何材料损失所加诸的任何限制。
在该焊料凸块106沉积之后，去除该阻剂掩模并且对该装置100进行图案化工艺107，在一个例示性具体例中，该图案化工艺107系设成在该焊料凸块106存在的情况下用于图案化该第一层105a的电化学去除工艺。举例来说，该第一层105a，其可包含二个或更多个次层，可由铜、铬或其任何组成物形成，可用于彼之已被认可的电化学刻蚀工艺为此技艺中众所周知者。为达此目的，可使该装置100与适当的电解液接触，该电解液包括，除了其它成分及添加物以外，第一层105a的对应金属硫酸根离子，以便在该第一层105a的暴露部分(扮作阳极)到阴极(未显示)之间建立电流，同时实质上避免焊料凸块106的材料去除，因为此金属比该第一层105a的金属更不贵重。在其它的具体例中，该图案化工艺107可以适当的湿式化学为基础而执行为湿式化学刻蚀工艺。在又其它的具体例中，该图案化工艺107可包括基于等离子体的刻蚀工艺，该基于等离子体的刻蚀工艺利用适用于去除该第一层105a的材料或诸材料的化学来执行。
图1b概略地显示在制造阶段中的半导体装置100，其中该图案化工艺107可已从该装置100的暴露部分去除该第一层105a的重要部分，其中，取决于该工艺107，个别的底刻蚀(under-etch)区域105u可能已形成为该第二层105b与在其周围的焊料凸块106之间的间隙(gap)。再者，在该图案化工艺107的期间，呈粒子等形式的污染物可形成或沉积在该层105a及/或105b上，取决于该图案化工艺107的过程。如图1b所示，该第一层105a的暴露部分系实质上被去除，同时粒子109可能已形成或可能已沉积在暴露的第二层105b之部分上。该等粒子109，其可能例如包含铅或锡及其可能典型地在该第一层105a图案化完成之后仍留在该第二层105b上，可能导致后继干式刻蚀工艺中的阴影效应(shadowing effect)。因为这些粒子109的去除可能在用于图案化第二层105b的后继干式刻蚀图案化工艺之基于等离子体的刻蚀化学中不被有效地达成，所以执行额外的清洁工艺110以去除该等粒子109或至少显著地降低其数目。否则，相邻焊料凸块106之间的绝缘距离可能被缩减，因而提高该装置100之凸块短缺及功能失效之可能性。再者，当该装置100系以该等焊料凸块106为基础附接于对应的载体基片且其余空间系实质上用底部填充(underfill)材料填充时，该等粒子109可能不利地影响任何底部填充材料对该钝化层103的黏着力。然而，该个别的底部填充材料对该下方钝化层103的黏着力降低可能造成该等焊料凸块106的疲乏裂损(fatigue crack)并且因此导致该装置100的功能失效。再者，如图1b可见到的，该等底刻蚀区域105u可能已在该图案化工艺107的期间形成，由于例如电化学刻蚀工艺的等向性本质，所以任何残余物，例如在此间隙中第二层105b上的粒子109，都可在该凸块106形成为对应焊球的回焊工艺期间扮作用于该焊料凸块材料的额外润湿区域(wetting area)，其中该第一层105a，亦即，其未被去除的部分，扮作实质上决定要形成的焊球的最终尺寸之润湿层(wettinglayer)。由此，该等底刻蚀区域105u中的任何残余物都可能导致不均匀性并且从而导致个别焊球的非圆形形状，因而危害个别晶粒区域内及横跨整个基片101的共平面及凸块高度分布。该等焊球的高度的任何显著不均匀性都可能造成对该载体基片的对应接触垫降低的接触，或降低高度的焊球可能甚至无法形成与个别接触垫的接触。
因此，清洁工艺110系设计以有效地去除或至少显著地降低该等粒子109的数目。为达此目的，在一个例示性具体例中，该清洁工艺110可包含呈原地清洁程序的方式在该图案化工艺107期间或结束时执行的一个或多个次步骤。举例来说，在例示性具体例中，该图案化工艺107系设计成电化学刻蚀工艺，并且该图案化工艺107可接着对应地被修饰而包括藉由个别手段，如传统电镀及电刻蚀工具中经常设置的，例如刷子等，之横跨该基片表面的快速清扫(sweep)。该快速清扫操作可在维持用于去除该第一层105a的材料之电化学刻蚀工艺之电流的情况下执行。再者，可利用不连续的电流流动执行一个或多个清扫操作，藉以亦有效地去除可能已沉积在相邻焊料凸块106之间的粒子109。在一个例示性具体例中，额外地或替代性地，执行至少一个进一步的清洁步骤，其中去离子水在适当高压下导向该装置100以进一步增进该清洁工艺110的效率。应明白任何其它的清洁步骤，例如在任何适当液体(例如去离子水等)存在的情况下刷洗或清扫该装置100的暴露表面，都可使用。再者，施加去离子水可藉由加入适当设计配置的喷嘴(jet)之任何适当的装置来执行，以便以高效率的方式释放及/或去除该等粒子109。在一个例示性具体例中，该清洁工艺110可包含可在原地与该图案化工艺107的一个或多个清洁步骤，例如有及没有电流的清扫操作，并且也可包含一个或多个进一步的清洁步骤，例如高压去离子水程序，其可在单独的工艺工具中执行。
图1c概略地显示在该清洁工艺110的此种单独清洁步骤期间的半导体装置100，在彼期间将去离子水供应至该装置100的暴露表面部分。在此制造阶段中，执行高压去离子水冲洗程序110a，所以，结合例如在前述图案化工艺107的期间可能已经视需要地执行的任何前述清洁步骤，该等粒子109系实质上被去除，藉以制备用于第二层105b的基于等离子体的图案化工艺之装置100。
图1d概略地显示在更进步的制造阶段中(亦即，在第二层105b的图案化期间)的半导体装置100。在此制造阶段中，对该装置100进行干式刻蚀工艺111，其系设成有效地去除第二层105b的材料，在一个例示性具体例中，该第二层105b的材料包含钛及钨，而在其它的具体例中，可使用如上指定的其它材料组成物。该基于等离子体的刻蚀工艺111可以含氟的化学为基础而执行，其中可使用前驱物气体，例如SF6、CF4、CHF3及NF3等以提供用于与该第二层105b的材料起反应之刻蚀工艺111的个别化学成分。在一个例示性具体例中，该工艺111的刻蚀环境(ambient)系建立以亦包含物理成分，亦即与该层105b的材料产生交互作用的成分及/或与实质上由离子轰击及溅镀效应引发之基于氟的化学反应之任何副产物，藉以实质上避免该第二层105b的任何自身钝化作用，若该图案化工艺111中只使用化学成分，亦即基于氟的化学，就可能发生该作用。在一个例示性具体例中，添加氧至该反应性基于氟的气氛以提供该图案化工艺111的物理成分。举例来说，该图案化工艺111的适合环境可在使用流速分别地为大约50至200sccm及100至300sccm之基于氧及氟的前驱物，例如以上确认的气体中之一者，配合流速为大约700至1500sccm之例如氢及氮等的载体气体之任何适当的传统刻蚀工具中建立。在此，可使用标准工艺室设计用之大约300至2000瓦的射频功率，其中该基片101的温度可维持在大约100至300℃而且该刻蚀环境的总压可在大约0.1至5.0托尔(Torr)的范围。然而，其它工艺参数可依以上的教导为基础，根据该第二层105b的指定材料组成，而建立。
应明白该基于等离子体的图案化工艺111与用于图案化该第二层105b的传统湿式化学刻蚀工艺相比，显然与焊料凸块106的图案密度及几何配置较不相关。因此，在去除该层105b时获得该工艺111之高度横跨基片的均匀性，藉以缓和与该接触层108的设计有关而且与该配置(亦即在该基片101上形成的整个晶粒区域之x与y方向的距离)有关的任何限制，如将参照图1g所作的更详细解释。再者，由于该基于等离子体的刻蚀工艺111的适度地高方向性，所以获得高的刻蚀精确度(fidelity)并且图案化该第二层105b至实质上对应于该焊料凸块106，该焊料凸块106扮作刻蚀掩模藉以避免该焊料凸块106的过度底刻蚀。此外，该图案化工艺111对该焊料凸块106的材料展现显著降低的去除速率，如同先前参照该清洁工艺110所指示的，因为该基于氟的化学可能无法有效地去除基于铅及锡的焊料。因此，与传统技术相比可增进回焊之后该焊料凸块106的高度均匀性，因而改良该装置100的可靠度及生产量。
在该图案化工艺111的最后阶段时，该钝化层103逐渐地暴露出来，其中在该工艺111的沉积气氛中可能逐渐地遇到从该钝化层103释放的副产物。在一个例示性具体例中，该钝化层103可包含聚醯亚胺，其可能导致挥发性成分产生，例如氰化物(CN)，其可作为有效的终点探测指示剂，因为激发的(excited)氰化物分子具有在386/388奈米(nm)显著的放射波长。这些波长可藉由如传统刻蚀工具中典型装设的光学终点探测系统(未显示)而有效地加以探测且监视。因此，该图案化工艺111可根据从氰化物分子获得的终点探测讯号而予以停止，藉以实质上避免从该钝化层103之任何过度的材料去除。在其它的具体例中，该钝化层103可使用不同的材料，例如苯并环丁烯，所以可识别其它的光学波长来用于适当的终点探测讯号。对应的光学终点探测讯号可以多数试验(test run)为基础而加以识别，其中可藉由该工艺111刻蚀一个或多个材料层，并且可监视光学讯号的特定带宽(bandwidth)，其可能包括红外线及紫外线波长，以便从彼识别一个或多个适当的个别波长或识别适当的波长范围。在其它的具体例中，在该工艺111的期间可监视指定的波长区域，例如大约500至800奈米的区域，其中在此波长间隔中显著的强度下降可能指示该钝化层103逐渐暴露出来。在其它的例子中，可识别且可追踪在以上指定的波长范围内的显著射线(line)，以便可靠地探测强度的显著下降，然后可使用彼来判定该图案化工艺111的适当终点。
如图1d所示，在该工艺111的期间及之后，该钝化层103的暴露区域上可形成一层或多数区域的碳雾(carbon haze)112。图1e概略地显示在用于去除该碳雾112的等离子体处理113期间的半导体装置100。该等离子体处理113可被设计成基于氧的等离子体处理，其可根据用于在钛钨凸块下金属化层的湿式化学图案化之后去除碳雾的传统工艺流程中所使用的工艺调制法。在一个例示性具体例中，该等离子体处理113可结合该图案化工艺111，所以这两个工艺步骤可在原地执行，其中在探测并且判定该图案化工艺111的终点之后，修改对应的刻蚀环境以便呈现该等离子体处理113的环境。也就是说，在判定该图案化工艺111的终点之后，就可中断不再需要的那些前驱物气体的供应，同时伴随适当的射频功率而提供例如氧及任何载体气体等的其它气体。再者，可调整其它的工艺参数，例如基片温度及压力等，以可靠地去除该碳雾112，同时避免在该焊料凸块106与该钝化层103处的过度材料去除。为达此目的，在一个例示性具体例中，可导入进一步的终点探测程序以可靠地识别用于中断该等离子体处理113的适当点。例如，可使用一氧化碳或二氧化碳的一个或多个显著的放射波长来识别该等离子体处理113的终点。例如，只要从该装置100的暴露区域有效地去除碳雾，在氧等离子体处理的期间就可形成碳氧化物。在一个或多个指定波长的强度有显著的下降之后，就可选择适当的时间点来终止该等离子体处理113。然而，在其它的例子中，可识别其它的挥发性材料，其使得可进行该等离子体处理113的有效光学终点探测。举例来说，用于有效地去除该碳雾112之利用氧或任何其它物种的轰击期间所产生的其它挥发性副产物可以对应的放射射线为基础而加以识别，然后可以该放射射线当作适当的终点探测讯号。对应的终点探测讯号可以就该钝化层103及/或就该等离子体处理113的不同工艺条件，利用不同材料执行的试验为基础而加以识别。
在图1f中，显示在更进步的制造阶段中的半导体装置100。在此，对该装置100进行进一步的清洁程序114，其系设计以便去除来自利用基于氟的化学而执行的前述图案化工艺111之残余物。为达此目的，该装置100可利用适当的湿式化学品化学而洗净，例如稀释的酸等，其中在一个例示性具体例中，该工艺114可执行为在任何适当传统工艺工具的湿式剥除(strip)工艺室中在原地的工艺，而在其它的具体例中可在用于施加一种或多种适当化学品的喷洒或浸渍工具中执行对应的工艺顺序，其中可执行一个或多个冲洗工艺。
之后，可依传统的方式持续进行进一步的加工，也就是说，必要的话，该焊料凸块106可藉由回焊该焊料而形成为焊球，其中该焊料凸块106的材料可藉由在该第一层105a上的表面张力而缩回(retract)，该层也可与该回焊的焊料形成化合物或合金。因为前述的图案化工艺，也就是说，特别是该基于等离子体的图案化工艺111，对于该焊料凸块106的材料展现显著降低的去除速率，所以可显著地降低制造成本，特别是在使用非常昂贵的辐射降低的铅(lead)时，同时另一方面可达成所得焊料凸块的改良高度均匀性。
图1g概略地显示该基片101的顶视图，其包含多数晶粒120，彼等各自可包括一个或多个半导体装置100，该半导体装置100的形成参照第1a至1f图加以说明。由此，该等晶粒区域120，以格栅状数组(grid-like array)配置并且标示在x-方向与y-方向具有相邻晶粒区域120之间的对应距离，各自包含多数焊料凸块106。该多数焊料凸块106可根据装置特定要求而非湿式化学图案化工艺加诸的任何限制而分布于各晶粒区域120上，如同以上说明的传统技术之例子一样。如先前解释的，该基于等离子体的图案化工艺113实质上与该多数焊料凸块106配置所用的图案类型无关，并且实质上与该等焊料凸块106的指定大小及形状无关。因此，该多数焊料凸块106的配置可根据有关电性、热及机械考量的限制而选择，所以就设计该接触层108的结构来说获得增进的弹性。因此，除了增进的设计弹性以外还可获得增进的装置效能，因为设计者可配置该等焊料凸块，所以，例如，讯号出错可被改善及/或在高开关活动部分的散热得藉由提供提高密度的焊料凸块等而增进。再者，在x-方向与y-方向个别晶粒区域120之间的距离可根据其它装置及工艺的要求而选择，藉以可能能提高每个基片的晶粒数目。
结果，本发明提供用于图案化凸块下金属化层堆栈的改良技术，其中至少藉由干式刻蚀工艺来图案化接触该钝化层的层，藉以避免用于图案化该对应凸块下金属化层的高度复杂湿式化学刻蚀工艺中涉及的许多问题。在例示性具体例中，此层经常以钛钨层的形式设置，其可能需要高度复杂的湿式化学刻蚀工艺，该工艺由于刻蚀残余物(例如传统湿式化学刻蚀工艺所产生的分离钛钨环)而导致提高的制造成本并且普通的生产量，该刻蚀残余物遂可能造成降低的焊球高度均匀性。用于最后凸块下金属化层之基于等离子体的图案化工艺对于图案密度及凸块大小展现显著降低的相依性，藉以能有增进的设计弹性而更有效地将装置的特定要求列入考量，例如该等焊料凸块的电性、热及机械特性。另一方面，该基于等离子体的刻蚀工艺的任何面积相依效应(area dependent effect)，例如暴露的钛/钨材料或该最后凸块下金属化层之任何其它材料的量，都可藉由对应地调整该基于等离子体的刻蚀调制法(例如藉由对应地调整总工艺时间)而轻易地列入考量，其中可使用高效率终点探测程序来可靠地终止该基于等离子体的图案化工艺。由此，就通常控制及监视传统刻蚀工艺所涉及的分析程序来看，结合降低效力有关之高度复杂湿式化学刻蚀工艺习惯上所需的化学品可获得显著的成本节省。再者，藉由使用该基于等离子体的图案化工艺获得大体上减短的工艺时间。再者，由于在传统技术中可能取决于凸块结构及凸块大小之刻蚀速率变化的降低，一般可更精确地形成焊料凸块，因而最终导致焊球对于晶粒有更可操控的黏着力。再者，因为该基于等离子体的图案化工艺实质上与凸块大小、配置及凸块间距无关，所以可达成进一步的装置尺寸缩放(scaling)，其中该凸块间距及该凸块大小可被缩小，以便适用于未来的装置世代。
以上所揭示的特定具体例仅为例示性，因为本发明可以对单方面认知本文教导之熟于此艺者为显而易见之不同但等效的方式作修改并实施。举例来说，以上说明的工艺步骤可依不同的顺序而执行。再者，除了以下申请专利范围所说明的以外，不欲限制本文所示的结构或设计之细节。因此显然地以上所揭示的特定具体例可加以改变或修饰，而且所有此等变化都视为在本发明的范围与精神以内。因此，本文寻求保护的部分如以下申请专利范围所提出。

Claims (10)

1、一种方法，包含：
在凸块下金属化层堆叠上所形成的多个凸块存在的情况下，通过电化学刻蚀工艺图案化所述的凸块下金属化层堆叠的第一层；
通过干式刻蚀工艺图案化所述的凸块下金属化层堆叠的第二层；以及
在所述的电化学刻蚀工艺期间、图案化所述的第二层之前，清洁所述的第二层；
其中，清洁所述的第二层包括：通过执行第一清除作业，同时维持在所述的电化学刻蚀工艺时使用的电流以从所述的第二层去除粒子，以及在所述的电流中断时执行第二清除作业。
2、如权利要求1所述的方法，其中，清洁(110)所述的第二层(105B)包含从所述的第二层(105B)去除粒子(109)。
3、如权利要求2所述的方法，其中，清洁(110)所述的第二层(105B)至少包含在所述的电化学刻蚀工艺(107)的期间执行的第一清洁工艺(110)及在所述的电化学刻蚀工艺(107)之后执行的第二湿式清洁工艺(110A)。
4、如权利要求1所述的方法，其中，图案化所述的第二层(105B)包含建立等离子体环境，所述的等离子体环境包含用于轰击所述的第二层的化学反应性成分及物理成分。
5、如权利要求1所述的方法，进一步包含在图案化所述的第二层(105B)之后执行等离子体清洁工艺(113)，以从所述的凸块下金属化层堆叠(105)下方的钝化层(103)去除碳残余物(112)。
6、如权利要求5所述的方法，进一步包含光学地探测所述的等离子体清洁工艺(113)的终点。
7、如权利要求1所述的方法，进一步包含执行用于去除前述干式刻蚀工艺(111)的副产物的湿式化学清洁工艺(114)。
8、如权利要求1所述的方法，其中，图案化所述的第二层(105B)进一步包括：
当使用所述的凸块(106)作为刻蚀掩模时，干式刻蚀(111)所述的暴露的第二层(105B)。
9、如权利要求5所述的方法，进一步包含干式刻蚀(111)的光学探测。
10、如权利要求9所述的方法，进一步包含确定通过刻蚀进入钝化层(103)所形成的至少一个挥发性成分的适当监视波长。
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CN101248521A (zh) 2008-08-20
WO2007015938A2 (en) 2007-02-08
WO2007015938A3 (en) 2007-03-29
TW200713444A (en) 2007-04-01
DE102005035772A1 (de) 2007-02-01
DE602006019266D1 (de) 2011-02-10
US7585759B2 (en) 2009-09-08
US20070023928A1 (en) 2007-02-01
TWI397957B (zh) 2013-06-01
EP1915776A2 (en) 2008-04-30
KR20080038199A (ko) 2008-05-02
KR101186347B1 (ko) 2012-09-26
EP1915776B1 (en) 2010-12-29
JP2009503852A (ja) 2009-01-29

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