CN100452318C - 用于产生栅极叠层侧壁隔片的方法 - Google Patents

用于产生栅极叠层侧壁隔片的方法 Download PDF

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CN100452318C
CN100452318C CNB2006100005104A CN200610000510A CN100452318C CN 100452318 C CN100452318 C CN 100452318C CN B2006100005104 A CNB2006100005104 A CN B2006100005104A CN 200610000510 A CN200610000510 A CN 200610000510A CN 100452318 C CN100452318 C CN 100452318C
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carborundum
dielectric constant
silicon
nitrating
layer
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蕾扎·阿嘎娃尼
迈克尔·丘·宽
夏立群
尹康素
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Abstract

本发明公开了一种用于通过利用PECVD工艺在栅极结构上沉积一个或多个含硅材料层以产生总k值在约3.0到约5.0之间的隔片，从而在栅极叠层上形成侧壁隔片的方法。含硅材料可以是碳化硅、掺氧的碳化硅、掺氮的碳化硅、掺碳的氮化硅、掺氮的碳氧化硅或其组合。沉积在等离子体增强化学气相沉积室中执行，并且沉积温度小于450℃。这样产生的侧壁隔片提供了好的容性电阻以及优秀的结构稳定性和密封性。

Description

用于产生栅极叠层侧壁隔片的方法
技术领域
本发明的实施例一般地涉及用于产生半导体衬底上的栅极叠层的侧壁隔片的方法。
背景技术
超大规模集成(ULSI)电路一般包括多于一百万个晶体管，这些晶体管形成在半导体衬底上，并且在电子器件内协同操作来执行各种功能。这种晶体管可以包括互补金属氧化物半导体(CMOS)场效应晶体管。
CMOS晶体管包括放置在半导体衬底内限定的源极区域和漏极区域之间的栅极结构。栅极结构(叠层)通常包括形成在栅极介电材料上的栅极电极。栅极电极控制电介质下方的电荷载流子在形成在漏极区域和源极区域之间的沟道区域中的流动，从而导通或截止晶体管。一般来说，紧挨栅极叠层布置的是隔片层，隔片层在栅极叠层的每一侧上形成了侧壁。侧壁隔片有好几个功能，包括电隔离栅极电极与源极和漏极触点或互连，在后续处理步骤期间保护栅极叠层免受物理退化的影响，并且提供氧和水气阻挡层以保护栅极金属。这种侧壁隔片结构的一个示例在2003年3月25日提交的美国专利申请No.10/397,776中有所公开。
传统的栅极叠层以介电常数小于约5(k＜5)的材料形成，并且一般受氮化硅隔片保护。晶体管尺寸的进一步减小可能要求栅极层的介电常数大于10(k＞10)。如果随后以相对高k(k＞7)材料(如氮化硅)来制作侧壁隔片，则在使用包含完整的栅极电极的器件的期间可能发生相邻互连线之间的过量信号串扰。尽管可以采用超低k材料(k＜3)作为隔片层，但是这些材料通常缺乏必要的结构完整性以承受后续的处理步骤和/或必需的对氧和水气的不透过性以保护栅极金属免受腐蚀。
另外，用来制备氮化硅隔片的传统的热化学气相沉积(CVD)工艺要求高的沉积温度，该温度一般超过600℃。在高温下沉积的氮化物隔片有非常好的保形性(例如≥95％)；但是，高沉积温度导致栅极器件的大的热周期，并且不与用于0.09微米技术甚至更细的高级器件制造兼容。
因此，需要一种用于低k栅极叠层的低温和低k侧壁隔片，其中该侧壁隔片拥有在结构稳定性和密封性方面的期望物理性能。
发明内容
本发明提供了一种方法，该方法用于通过利用等离子体增强化学气相沉积(PECVD)工艺在等于或低于450℃的温度下在栅极叠层上沉积一个或多个含硅材料层以产生总介电常数在约3.0到约5.0之间的隔片，从而在栅极叠层上形成侧壁隔片。
在一个实施例中，一种用于形成栅极电极的侧壁隔片的方法包括：将具有栅极结构的衬底放置在等离子体处理室中；使一种或多种处理气体流入等离子体处理室；在等离子体处理室中产生等离子体；以及在等于或小于450℃的温度下，在栅极结构上沉积一个或多个含硅材料层，其中所述一个或多个含硅材料层具有约3.0到约5.0的总k值。
在另一个实施例中，一种用于形成栅极电极的侧壁隔片的方法包括：将具有栅极结构的衬底放置在等离子体处理室中；使一种或多种处理气体流入等离子体处理室；在等离子体处理室中产生等离子体；以及在栅极结构上沉积一个或多个含硅材料层，其中所述一个或多个含硅材料层具有约3.0到约5.0的总k值，并且所述一个或多个含硅材料层选自以下的组，所述组由碳化硅、掺氧的碳化硅、掺氮的碳化硅、掺碳的氮化硅、掺氮的碳氧化硅和其组合的组成。
在另一个实施例中，一种用于形成栅极电极的侧壁隔片的方法包括：将具有栅极结构的衬底放置在等离子体处理室中；使一种或多种处理气体流入等离子体处理室；在等离子体处理室中产生等离子体；以及在等于或小于450℃的温度下，在栅极结构上沉积一个或多个含硅材料层，其中所述一个或多个含硅材料层具有约3.0到约5.0的总k值，并且所述一个或多个含硅材料层选自以下的组，所述组由碳化硅、掺氧的碳化硅、掺氮的碳化硅、掺碳的氮化硅、掺氮的碳氧化硅和其组合组成。
附图说明
从而，通过参考实施例，可以知道可以详细理解本发明的上述特征的方式以及上述简要总结的本发明的更具体描述，在附图中示出了某些实施例。然而，应当注意，附图仅仅图示了本发明的典型实施例，因此并不应认为是对本发明范围的限制，因为本发明可以容许其他等同的实施例。
图1图示了包括根据本发明一个实施例形成的栅极结构的晶体管。
图2示出了PECVD室中薄膜沉积的工艺流程。
其中附图标记表示：
100：衬底
102：场隔离区域
103：阱
104：栅极介电层
106：电极层
124：栅极叠层
125：薄氧化物层
126：隔片层
140：尖端
148：源极/漏极区域
200：等离子体沉积工艺流程
201：将衬底放置在等离子体处理室中
202：使一种或多种处理气体流入等离子体室
203：在等离子体处理室中产生等离子体
204：在等离子体处理室中，在衬底上沉积薄膜
具体实施方式
本发明包括通过向栅极结构施加基于硅的膜来形成栅极叠层的侧壁隔片。在某些实施例中，隔片层通过沉积与栅极电介质紧邻的碳化硅、掺氧的碳化硅、掺氮的碳化硅、或者掺碳的氮化硅来形成。在另一个实施例中，隔片层通过沉积掺碳的氧氮化硅来形成。
图1图示了具有根据本发明一个实施例形成的栅极结构的晶体管。参考图1，在衬底100(例如硅晶片)中形成有多个场隔离区域102。该多个场隔离区域102将一种类型电导性(例如p型)的阱103与其他类型电导性(例如n型)的相邻阱(未示出)隔离开来。然后，在衬底100和隔离区域102上形成栅极介电层104。一般来说，栅极介电层104可以通过沉积或生长诸如氧化硅(SiOn)和/或氧氮化硅之类的材料层来形成，这些材料层形成了介电常数小于约5.0的层。近来栅极介电技术的进展表明较高的介电常数材料(K＞10)对于形成栅极介电层104来说是理想的。用于此的合适材料的示例包括但不限于金属氧化物(Al2O3、ZrO2、HfO2、TiO2、Y2O3和La2O3)、铁电体(锆钛酸铅(PZT)和钛酸锶钡(BST))、无定形金属硅酸盐(HfSixOy和ZrSixOy)、无定形硅酸盐氧化物(HfO2和ZrO2)和顺电体(BaxSr1-xTiO3和PbZrxTi1-xO3)。包含这些材料的高k层可以利用各种沉积工艺形成。
另外，导电的栅极电极层106毯覆沉积在栅极介电层104上。通常，栅极电极层106可以包括诸如但不限于掺杂多晶硅、非掺杂多晶硅、碳化硅、或硅锗化合物之类的材料。然而，在可预期的实施例中，栅极电极层106可以包含金属、金属合金、金属氧化物、单晶硅、无定形硅、硅化物或本领域中公知的用于形成栅极电极的其他材料。
诸如氮化物层之类的硬掩模层(未示出)经由CVD工艺沉积在导电层106上。然后，执行光刻工艺，其包括以下步骤：掩蔽、曝光和显影光刻胶层以形成光刻胶掩模(未示出)。通过使用光刻胶掩模来对齐刻蚀将硬掩模层刻蚀到栅极电极层106的顶部，从而在栅极电极层106上产生硬掩模(未示出)，使光刻胶掩模的图案转移到硬掩模层上。
通过移去光刻胶，并使用硬掩模来对齐刻蚀将栅极电极层106向下刻蚀到介电层104的顶部，从而产生包括硬掩模下方的栅极电极层106的剩余材料在内的导电结构，来进一步修饰结构。此结构由刻蚀栅极电极层106，而不刻蚀硬掩模或栅极介电层104而得到。继续处理工序，栅极介电层104被刻蚀到衬底100的顶部和隔离区域102的顶部。栅极电极106和栅极电介质104一起限定了集成器件(如晶体管)的复合结构124，有时也称为栅极叠层或栅极。
在晶体管的进一步处理中，通过采用尖端注入工艺来形成尖端或浅的源极/漏极延伸140。栅极电极106保护了栅极电介质104下方的衬底区域不被离子注入。然后，可以执行快速热处(RTP)退火，以将尖端140驱动到栅极电介质104的部分下方。
随后，保形的薄氧化物层125沉积在整个衬底表面上。该氧化物层被用来保护硅表面免受隔片层的影响，隔片层在传统工艺中是氮化硅层。保形的薄氧化物层一般以TEOS源气体在低压化学气相沉积室中在高温下(＞600℃)进行沉积。其松弛了硅衬底和氮化物隔片之间的应力，并且还保护了栅极角部免受氮化硅隔片的影响。如果使用低k和非氮化硅材料作为侧壁隔片，则该保形的薄氧化物层125可能被消除或被其他的低k材料取代。
然后，在本发明的一个实施例中，厚度在约200埃到约1000埃范围内，优选地在约400埃到约800埃之间的隔片层126毯覆沉积在栅极叠层124的顶部，并且沿着复合结构124的侧边的整个长度沉积，包括栅极电极106和栅极电介质104的侧壁的整个长度。同时，隔片层126沉积在衬底100或隔离区域102的任何暴露部分的顶部。传统的隔片层是通过热CVD沉积的氮化硅层。对于高级器件制造，氮化硅(k值约为7)的介电常数(k值)太高，这可能导致过量的信号串扰。另外，用来沉积氮化硅的热CVD工艺要求高的沉积温度(＞600℃)。高沉积温度导致高的热周期，并且可能改变尖端140的掺杂剂分布。因此，使隔片层沉积工艺具有更低的沉积温度是所希望的。等离子体增强化学气相沉积(PECVD)工艺一般具有更低的沉积温度。对于由等离子体工艺沉积的氮化硅层，沉积温度可以降低到450℃或更低。图2中示出了在等离子体处理室中沉积薄膜的工艺。该工艺开始于步骤201，在步骤201，将衬底放置在等离子体处理室中。随后在步骤202，使一种或多种处理气体流入等离子体处理室中。然后在步骤203，在等离子体处理室中产生等离子体。在步骤204，在等离子体处理室中在衬底上沉积薄膜。由等离子体工艺沉积的隔片层的保形性没有热CVD工艺沉积的那么好。以氮化硅作为示例，由热CVD沉积的氮化硅具有接近100％的保形性，而由PECVD沉积的氮化硅的保形性为约75％。尽管PECVD工艺沉积的隔片层的保形性比热CVD工艺沉积的低，但是低热周期(或热预算)的优点可以胜过低保形性的缺点。因此，采用由PECVD沉积的低k隔片层是理想的。
然后，刻蚀隔片层126和薄氧化物层125，以从栅极电极106的顶部，以及从隔离区域102的顶面和衬底100的大部分顶面(除了直接靠在栅极叠层124的任一侧边的以外)移去隔片层126和薄氧化物层125。然而，各向异性刻蚀留下了隔片层126和薄氧化物层125沿栅极电极106和栅极电介质104的侧壁的整个长度的一部分，从而形成了侧壁隔片126。或者，侧壁隔片126可以被沉积为单个层或两个或更多个顺序沉积的层。
随后，对衬底100进行深度高剂量注入处理，以在阱区域103中形成深结源极/漏极区域148。深度注入包括以用来形成尖端140的相同导电类型杂质注入离子。同时，如果导电栅极电极包括多晶硅，则可以使用深度注入工艺来掺杂栅极电极106中的多晶硅(如果先前未掺杂的话)。可以执行活化退火来活化尖端140和深度注入区148。可以用快速热处理(RTP)来执行退火。
晶体管结构和其形成方法的前述实施例仅是示例性的。可以采用栅极电极和其替换形成方法的另外实施例来实践本发明。关于用于形成栅极叠层的示例性方法和装置的进一步的细节在2003年7月1日提交的共同转让的美国专利申请No.10/612,642中有所公开，该申请要求了2002年7月2日提交的美国临时专利申请No.60/393,393的优先权，这里通过引用并入这两个申请的内容，只要其与本文内容不冲突。
在本发明的各种实施例中，隔片膜(层)126可以由碳化硅、掺氧的碳化硅、掺氮的碳化硅、掺碳的氮化硅、掺氮的碳氧化硅或其组合形成。在这些实施例中，所得到的隔片层126具有约3.0到约5.0的k值。另外，沉积由PECVD工艺在低于450℃的温度下进行。
在一个实施例中，通过使包括硅源、碳源和惰性气体在内的气体混合物在PEVCD室(如DxZTM室)中在等离子体条件下发生反应，由碳化硅形成了隔片层126。DxZTM室可以从位于California，Santa Clara的应用材料公司商业获得。在一个实施例中，处理温度在约200℃到约400℃之间。硅源和碳源可以是单个源，如具有通式SixCyHz的有机硅烷化合物。例如，可以使用甲基硅烷(SiH3CH3)、二甲基硅烷(SiH2(CH3)2)、三甲基硅烷(SiH(CH3)3)、四甲基硅烷(Si(CH3)4)、二乙基硅烷(SiH2(C2H5)2)和二(三甲基甲硅烷基)乙烯(C(Si(CH3)3)2)和其组合，以及其他化合物来提供硅和碳。或者，可以使用包括但不限于硅烷(SiH4)、乙硅烷(Si2H6)和其组合的化合物作为硅源，并且可以采用具有通式CxH2x+2的化合物(包括但不限于甲烷(CH4))、具有通式CxH2x的化合物(包括但不限于乙烯(C2H4))和其组合作为碳源。可以使用氦(He)、氩(Ar)、氮(N2)和其组合以及其他气体作为惰性气体。用于沉积碳化硅层的方法和其物理性能的进一步的细节在共同转让的美国专利No.6,465,366中有所公开，这里通过引用并入其内容，只要其与本文内容不冲突。
如前沉积的碳化硅层具有约3.0到约5.0的介电常数。碳化硅层的介电常数是可调节的，因为其可以作为混频RF功率的比率的函数变化。具体而言，随着低频RF功率对总混合RF功率的比率的减小，如前沉积的碳化硅层的介电常数也减小。碳化硅层的介电常数也可以作为层形成期间气体混合物的组分的函数来被调节。随着气体混合物中碳浓度的增加，如前沉积的碳化硅层的碳含量增加，减小了其介电常数。同样，随着如前沉积的碳化硅层的碳含量的增加，其疏水性增加。
在另一个实施例中，通过使包括一种或多种含氧有机硅化合物和一种或多种无氧有机硅化合物的处理气体发生反应，形成包括碳-硅键并且介电常数在约3.5到约5.0之间的介电层，来由掺氧的碳化硅形成隔片层126。含氧有机硅化合物具有通用结构SiwCxHyOz。无氧有机硅化合物具有通用结构SixCyHz。用于上述工艺的合适的有机硅化合物包括脂肪族有机硅化合物、环状有机硅化合物、或其组合。脂肪族有机硅化合物具有线性或枝化结构。商业可获得的脂肪族有机硅化合物包括无氧有机硅化合物(如烷基硅烷)和含氧有机硅化合物(如烷基硅氧烷)。
上述工艺优选地在适合于沉积有机硅材料同时施加RF功率的等离子体处理室中执行，如DxZTM等离子体增强化学气相沉积室。在一个实施例中，沉积温度在约250℃到约450℃之间。通常，有机硅化合物在包括惰性气体或不活泼气体的等离子体中反应，惰性气体例如是氦(He)或氩(Ar)，不活泼气体例如是氮(N2)。用于沉积掺氧的碳化硅层的方法和其物理性能的进一步的细节在2002年7月15日提交的共同转让的美国专利No.6,890,850中有所公开，该专利要求了2001年12月14日提交的美国临时专利申请No.60/340,615的优先权，这里通过引用并入这两个文件的内容，只要其与本文内容不冲突。
在另一个实施例中，通过沉积碳化硅层，然后在等离子体条件下通过提供含氧的气体来向该层引入氧，形成了掺氧的碳化硅层。以含氧的气体进行的等离子体处理可以在如DxZTM室的PECVD室中执行。在一个实施例中，等离子体处理温度维持在约0℃到约500℃之间的范围内，优选地在约100℃到约450℃之间的范围内。掺氧的碳化硅膜具有约1到约30原子百分比的氧含量和约3.5到约5.0的介电常数。在一个实施例中，一种或多种无氧有机硅化合物和一种或多种含氧有机硅化合物进行反应，以沉积具有约1到约30原子百分比的氧含量和约3.5到约5.0的介电常数的掺氧的碳化硅膜。在一个实施例中，沉积在PECVD室中执行，并且温度维持在约-20℃到约500℃之间，优选地在约170℃到约180℃之间。掺氧的碳化硅层的介电常数是可调节的，因为其可以作为所采用的反应物、反应物和惰性气体流率、室温度和施加的RF频率的函数而变化。用于通过碳化硅层的氧掺杂来产生掺氧的碳化硅层的方法的进一步的细节在1999年6月18日提交的共同转让的美国专利No.6,821,571和2003年3月7日提交的共同转让的美国专利No.6,913,992中有所公开，这里通过引用并入这两个文件的内容，只要其与本文内容不冲突。
在另一个实施例中，通过使包括硅源、碳源和氮源的气体混合物进行反应，由掺氮的碳化硅形成了隔片层126。这里，术语“掺氮的碳化硅”指包含硅、氮、碳和(可选的)氢的材料，其中氮含量小于碳含量。在一个实施例中，如前沉积的掺氮的碳化硅层包含约1到约30原子百分比的氮，并且具有约4.0到约5.0的介电常数。沉积可以在如DxZTM室的PECVD室中执行。在一个实施例中，衬底温度维持在约150℃到约450℃之间的范围内。掺氮的碳化硅层的介电常数是可调节的，因为其可以作为沉积工艺期间施加的RF功率的函数而变化。具体而言，随着RF功率的增大，如前沉积的掺氮的碳化硅层的介电常数也增大。另外，介电常数可以作为气体混合物中氮源和/或其浓度的函数而变化。具体而言，随着氮掺杂物的含量增加，沉积的掺氮的碳化硅层的介电常数减小。用于沉积掺氮的碳化硅层的方法和其物理性能的进一步的细节在2000年7月28日提交的共同转让的美国专利No.6,764,958和美国专利No.6,537,733中有所公开，这里通过引用并入这两个文件的内容，只要其与本文内容不冲突。
在另一个实施例中，掺氮的碳化硅层由碳化硅层的氮化来形成。其中，由等离子体工艺制备的碳化硅层被暴露于硝化气体的等离子体中，以在碳化硅层上形成富氮表面。以含氮气体进行的等离子体处理可以在PECVD室中执行，如DxZTM室或ProducerTM PECVD室，这两种室都可以从California，Santa Clara的应用材料公司获得。在一个实施例中，衬底温度维持在约100℃到约450℃之间的范围内。碳化硅层的富氮表面可以包括氮化硅或氮化碳硅，并且在这里被称为氮化表面。硝化气体选自下面的组，该组包括但不限于氨气(NH3)、氮气(N2)、一氧化二氮(N2O)和其组合。另外，氮化工艺可以包括惰性气体，如氩(Ar)和氦(He)。如前沉积的掺氮的碳化硅层包含约1到约30原子百分比的氮，并且具有约4.0到约5.0的介电常数。用于通过碳化硅层的氮化沉积掺氮的碳化硅层的方法的进一步的细节在2001年7月10日提交的共同转让的美国专利No.6,794,311中有所公开，这里通过引用并入该专利的内容，只要其与本文内容不冲突。
在另一个实施例中，通过使包括硅源、碳源和氮源的气体混合物进行反应，由掺碳的氮化硅形成了隔片层126。这里，术语“掺碳的氮化硅”指包含硅、氮、碳和(可选的)氢的材料，其中碳含量小于氮含量。这种层例如可以通过使一种或多种含氮化合物与一种或多种有机硅化合物发生反应来形成。沉积可以在如ProducerTM室的PECVD室中进行。在一个实施例中，沉积温度在约100℃到约500℃之间，优选地在约250℃到约450℃之间。如前沉积的掺碳的氮化硅层包含约1到约30原子百分比的碳，并且具有约4.0到约5.0的介电常数。掺碳的氮化硅层的介电常数是可调节的，因为其可以作为反应压强和气体混合物中氮源和/或其浓度的函数而变化。用于沉积掺碳的氮化硅层的方法和装置的进一步的细节在2004年4月19日提交的共同转让的美国专利申请No.10/828,023和2003年11月25日提交的美国临时专利申请No.60/525,241中有所公开，这里通过引用并入这两个申请的内容，只要其与本文内容不冲突。
在另一个实施例中，隔片层126由掺氮的碳氧化硅形成。这里，术语“掺氮的碳氧化硅”用来指包含硅、碳、氧和氮的化合物。在一个实施例中，本发明的掺氮的碳氧化硅通过使一种或多种有机硅源气体与一种或多种氧源气体和一种或多种氮源气体进行反应来形成。掺氮的碳氧化硅的介电常数在约3.0到约5.0之间。在一个实施例中，沉积工艺可以在PECVD室中进行，并且沉积温度在约-20℃到约500℃之间，优选地在约170℃到约180℃之间。在一个实施例中，在沉积后，沉积材料被在约100℃到约400℃之间的温度下退火，以减少水分含量并增大沉积材料的密实性和硬度。在一个实施例中，沉积材料被在约300℃到约450℃之间的温度下进行等离子体处理，以减少表面对后续沉积的材料的反应性。掺氮的碳氧化硅的介电常数是可调节的，因为其可以作为所采用的反应物和反应室温度的函数而变化。用于沉积掺氮的碳氧化硅的方法的进一步的细节在共同转让的美国专利No.6,656,837和美国专利No.6,627,532中有所公开，这里通过引用并入这两个专利的内容，只要其与本文内容不冲突。
尽管前述材料可以沉积为单个层以形成侧壁隔片，但是本发明不限于此。可以在等离子体增强化学气相沉积反应室中在等离子体条件下，在等于或小于450℃的温度下，顺序或同时沉积一个或多个材料层，以产生总k值在约3.0到约5.0之间的复合隔片层。这可以通过施加每层具有约3.0到约5.0之间的k值的一个或多个材料层来实现。或者，这可以通过施加这样的一个或多个材料层来实现，其中任何一层可以具有大于或小于约3.0到约5.0的k值，从而使复合隔片层具有约3.0到约5.0之间的k值。
尽管前述内容描述了本发明的实施例，但是在不脱离本发明基本范围的前提下可以设计出本发明的其他和另外的实施例，本发明的基本范围由所附权利要求确定。

Claims (19)

1.一种用于形成栅极电极的侧壁隔片的方法，包括：
将具有栅极结构的衬底放置在等离子体处理室中；
使一种或多种处理气体流入所述等离子体处理室；
在所述等离子体处理室中产生等离子体；以及
在等离子体的存在下，在等于或小于450℃的温度下，在所述栅极结构上沉积一个或多个含硅材料层，其中所述一个或多个含硅材料层具有3.0到5.0的总介电常数值，包含选自以下组的材料，所述组由碳化硅、掺氧的碳化硅、掺氮的碳化硅、掺碳的氮化硅、掺氮的碳氧化硅和其组合组成。
2.如权利要求1所述的方法，其中所述侧壁隔片形成为单个层。
3.如权利要求1所述的方法，其中所述侧壁隔片包括碳化硅。
4.如权利要求3所述的方法，其中通过改变沉积期间所述等离子体增强化学气相沉积室的混频功率的比率，来改变所述碳化硅的介电常数。
5.如权利要求3所述的方法，其中通过改变用来沉积碳化硅的气体混合物，来改变所述碳化硅的介电常数。
6.如权利要求1所述的方法，其中所述含硅材料包括掺氧的碳化硅。
7.如权利要求6所述的方法，其中通过改变所述等离子体增强化学气相沉积室的混频比率，来改变所述掺氧的碳化硅的介电常数。
8.如权利要求6所述的方法，其中通过改变所述处理气体或处理气体流率，来改变所述掺氧的碳化硅的介电常数。
9.如权利要求6所述的方法，其中通过改变沉积温度，来改变所述掺氧的碳化硅的介电常数。
10.如权利要求1所述的方法，其中所述含硅材料包括掺氮的碳化硅。
11.如权利要求10所述的方法，其中通过增加RF功率，来增大所述掺氮的碳化硅的介电常数。
12.如权利要求11所述的方法，其中通过调节沉积期间所使用的氮源和/或所述沉积气体混合物中氮源的浓度，来改变所述掺氮的碳化硅的介电常数。
13.如权利要求1所述的方法，其中所述含硅材料包括掺氮的碳化硅，并且所述掺氮的碳化硅由碳化硅的等离子体氮化形成。
14.如权利要求13所述的方法，其中所述等离子体氮化在100℃到450℃之间的温度下执行。
15.如权利要求1所述的方法，其中所述含硅材料包括掺碳的氮化硅。
16.如权利要求15所述的方法，其中所述掺碳的氮化硅具有小于30原子百分比的碳含量。
17.如权利要求15所述的方法，其中通过调节反应压强、沉积期间所使用的氮源和所述沉积气体混合物中气体的浓度，来改变所述掺碳的氮化硅的介电常数。
18.如权利要求1所述的方法，其中所述含硅材料层包括掺碳的氧氮化硅。
19.如权利要求18所述的方法，其中通过调节沉积温度或用来形成所述掺碳的氧氮化硅的反应物，来改变所述掺碳的氧氮化硅的介电常数。
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