CN100421352C - 高频功率放大器模块 - Google Patents

高频功率放大器模块 Download PDF

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CN100421352C
CN100421352C CNB03823274XA CN03823274A CN100421352C CN 100421352 C CN100421352 C CN 100421352C CN B03823274X A CNB03823274X A CN B03823274XA CN 03823274 A CN03823274 A CN 03823274A CN 100421352 C CN100421352 C CN 100421352C
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wiring layer
transistor
line
power amplifier
high frequency
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CN1685607A (zh
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杉浦政幸
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Toshiba Corp
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Abstract

在第一和第二布线层(LY1、LY2)之间设置一个接地层(GND1)。设置在所述第一布线层(LY1)的第一晶体管(Q1)放大所提供的高频信号。设置在所述第一布线层(LY1)的第二晶体管(Q2)放大所述第一晶体管的输出信号。在所述第一布线层(LY1)设置向第一晶体管(Q1)提供电源的第一电源线(ML1)。在所述第二布线层(LY2)设置向第二晶体管(Q2)提供电源的第二电源线(ML2)。

Description

高频功率放大器模块
技术领域
本发明涉及一种高频功率放大器，更具体地说，本发明涉及一种微型高频功率放大器模块，该模块用于例如在移动电话或者便携式终端中放大高频功率。
背景技术
随着对于终端的微型化和较长通话的需求，需要便携式终端的信号发射部分的最终级的高频功率放大器更小并且具有更高的效率。近年来，对于微型化的需求已经变得越来越强烈。为了满足这一需求，已经以把构成放大器的晶体管和外围部分压缩到一个小封装中的这样一种方式使功率放大器模块化，同时输入和输出阻抗匹配到50Ω。该模块的尺寸为4至5平方毫米。
该模块所需具备的性能特征之一是易于使用的特征。具体地说，需要该模块将其输入和输出与特定的阻抗匹配，并且具有优异的浪涌电阻(surge resistance)、温度特性以及对电压波动的稳定性。此外，需要该模块对于外部电路的波动是稳定的。具体地说，在靠近外部的地方通过一个无源元件例如开关或者收发转换开关设置一个功率放大器。为此，当外部情况存在预期的波动诸如负载波动、例如对天线造成的损坏或者天线变形时，需要该放大器不发生诸如击穿或者振荡等故障。
这种故障的一个典型例子是f0/2振荡。当在输入频率为f0的发射信号的状态下急剧改变负载时，在发射频率f0的一半频率上发生这种振荡。考虑了发生这种振荡的几个原因。下面将说明这些原因中的一个原因。
图1示意性地示出了构成功率放大器模块的两级放大器电路。该功率放大器模块包括作为放大器部分的GaAs芯片11、输入匹配电路12、输出匹配电路13、具有例如电感成分L1、L2的电流供应线(电源线)ML1、ML2构成芯片部件的电容器C1、C2。由异质结双极型晶体管(HBT)组成的GaAs芯片11包括构成第一级放大器的晶体管Q1、构成第二级放大器的晶体管Q2、MIM(金属绝缘体金属)电容器C3和偏置电路14。
输入匹配电路12连接在输入管脚Pin和晶体管Q1的基极之间。输出匹配电路13连接在晶体管Q2的集电极和输出管脚Pout之间。具有电感成分L1的线ML1连接在电源管脚Vcc1和晶体管Q1的集电极之间。具有电感成分L2的线ML2连接在电源管脚Vcc2和晶体管Q2的集电极之间。电容器C1连接在电源管脚Vcc1和地之间，而电容器C2连接在电源管脚Vcc2和地之间。负载Zout连接在输出管脚Pout和地之间。
最初将晶体管Q2的负载阻抗设计为在线性区或者轻饱和区工作。然而，例如，当与功率放大器模块连接的天线(未示出)损坏时，负载Zout的值严重波动。负载Zout中的波动致使晶体管的负载阻抗是一个与设计值不同的值。在这种情况下，如果在输出管脚Pout输出一个信号，则将在负载Zout处产生反射波，这将使大电流在晶体管Q2中流动或者在晶体管Q2中出现大电压幅度。结果，晶体管Q2非线性地工作，导致失真的波形。此时，晶体管Q2以等效于所谓的混频器的方式工作，因此具有频率转换增益。
如图1所示，当在该功率放大器模块中存在一个构成反馈回路LP1的电路时，对于频率为f0/2的信号来说，晶体管Q1、Q2具有的转换增益可以允许回路增益超过“1”。在这种状态下，即使在该f0/2频率信号中存在一个微小的噪声信号，信号电平也逐渐增加，并且最终出现振荡。这被称为f0/2振荡。
在大模块没有微型化的情况下，可以使如图1所示的具有电感成分L1、L2的线ML1、ML2之间的距离足够大。结果，形成回路LP1的的电感成分L1、L2之间的电磁耦合不存在，或者在其间仅存在非常微弱的电磁耦合。因此，在大模块的情况下，其回路增益不超过“1”，并且因此f0/2振荡不会发生。
然而，如上所述将模块微型化。结果，信号线被非常高密度地布置在该模块的一个狭窄区域中。因此，线之间的电磁耦合变得更强，这使回路增益超过“1”，并且使其更容易发生f0/2振荡。
特别设计用于晶体管Q2的电源线ML2使其具有如此高的阻抗，以至于对于输出匹配电路13来说可以将它忽略。为了得到高阻抗，线ML2需要非常长的线长度。线ML2的典型例子是具有λ/4长度的λ/4线。这里，λ是频率f0的信号波长。很难在其中设置了芯片元件的模块的表面上形成长线。为此，将模块基板设计成具有多层结构，并且使用多个布线层来实现长线。
另一方面，用于晶体管Q1的电源线ML1也起到如图1所示的电路中的匹配电路的作用。因此，该电源线需要长到一定程度。由于当频率特别低时需要长线，在小模块中，难以仅在基板的表面层形成该线。为此，在该基板内的一个层中形成该线。
如上所述，在常规的多层模块基板中，用于晶体管Q1、Q2的电源线ML1、ML2被复杂地布置在同一层中。因此，线ML1、ML2之间的电磁耦合不可避免。结果，形成了如图1所示的回路LP1，这导致了一个问题：当如上所述负载波动时，将发生f0/2振荡。
此外，除了图1所示的回路LP1之外，还可能出现回路LP2。通过构成输入匹配电路12的线ML3和用于晶体管Q1的电源线ML1之间的电磁耦合形成回路LP2。构成输入匹配电路12的线也需要长到一定的程度。因此，也可以在内层中形成这些线。结果，在这种情况下，也会发生f0/2振荡。
如上所述，使用常规的多层结构基板的小模块具有下列问题：当晶体管由于干扰例如负载波动而非线性地工作时，回路增益超过“1”，这引起f0/2振荡。
涉及该技术的一篇专利参考文献是日本专利申请公开公布No.2000-357771。在该参考文献中，在接地层39和接地层40之间的一个层中设置用于给有源元件提供直流电源的电源线25。然而，在该专利参考文献中公开的技术是用于防止由高频电路引起的交流噪声分量进入该直流电源。因此，该参考文献既不意味着回路增益的降低，也不意味着防止了f0/2振荡。
因此，需要一种能够防止f0/2振荡的高频功率放大器模块。
发明内容
根据本发明的一个方案，提供一种高频功率放大器，包括：包含至少第一和第二布线层以及至少一个设置在所述第一和第二布线层之间的接地层的基板；设置在第一布线层，并且放大所提供的高频信号的第一晶体管；设置在第一布线层，并且放大所述第一晶体管的输出信号的第二晶体管；向第一晶体管提供电源，并且设置在第一布线层的第一电源线；以及向第二晶体管提供电源，并且设置在第二布线层的第二电源线。
根据本发明的另一个方案，提供一种高频功率放大器，包括：包含至少第一、第二和第三布线层以及至少一个设置在第二和第三布线层之间的接地层的基板；设置在第一布线层，并且放大所提供的高频信号的第一晶体管；设置在第一布线层，并且放大所述第一晶体管的输出信号的第二晶体管；向第一晶体管提供电源，并且设置在第三布线层的第一电源线；以及向第二晶体管提供电源，并且设置在第二布线层的第二电源线。
附图简述
图1是示出了在高频功率放大器中形成回路的位置的实例的电路图；
图2是根据本发明第一实施例的高频功率放大器模块的基板表面的平面图；
图3是沿着图2的线3-3截取的剖面图；
图4A至4E是示出了图3的各层的平面图；
图5是根据本发明第二实施例的高频功率放大器模块的第一布线层的平面图；
图6是沿着图5的线6-6截取的截面图；以及
图7A至7E是示出了图6的各层的平面图。
实施本发明的最佳模式
下面将参考附图说明本发明的实施例。
第一实施例
图2至4E示出了本发明的第一实施例。
应用于第一实施例、与图1所示电路相同的电路是用于例如1900MHz频带中的CDMA(码分多址)信号的功率放大器。在图2至4E中，与图1中的相同的部分用相同的参考编号来表示。
在图2和3中，高频功率放大器模块21包含多层介电层和布线层。具体地说，模块21具有多个陶瓷薄膜基板彼此层叠的结构。该薄膜基板的主要成份例如是氧化铝。在每个基板21A的正面和背面上形成布线层。具体地说，从模块21的顶部向下依次设置第一、第二和第三布线层LY1、LY2、LY3。在第一和第二布线层LY1、LY2之间设置第一接地层GND1。在第二和第三布线层LY2、LY3之间设置第二接地层GND2。在最下层的基板的背面上设置第三接地层GND3。第一、第二和第三接地层GND1、GND2和GND3中的每一个的大部分表面覆盖有导电膜，例如金属接地图形，如图4A、4C和4E中的斜线所示。基板之间的布线通过通路孔VH连接。
在第一实施例中，模块21的每一侧的长度例如是5mm。设置在最下层的基板上的第三接地层GND3和焊盘图形连接到其上安装了模块21的板(未示出)。
在最高层(或者第一布线层LY1)上，设置如图1所示的GaAs芯片11、输入匹配电路12、输出匹配电路13、具有电感成分L1的线ML1、用于将控制信号和其它信号提供给GaAs芯片(DC电路)的连线，以及各种芯片元件。线ML1连接在电源管脚Vcc1和GaAs芯片11中的晶体管Q1的集电极之间。在1900MHz频带中的功率放大器的情况下，用于获得特定阻抗的线长可以很短。这样，可以在第一布线层LY1中形成线ML1。在远离输入匹配电路12和输出匹配电路13的一个部分上形成线ML1。因此，线ML1不与输入匹配电路12和输出匹配电路13一起形成回路。GaAs芯片11和基板布线用金线(焊线)连接。
另一方面，在低于第一布线层的第二布线层LY2设置用于向晶体管Q2提供电流的线ML2，如图3和4B所示。第二布线层LY2具有用于将第一布线层LY1的布线连接到下面的布线的通路孔区。除通路孔区之外的大部分区域被用于向晶体管Q2提供电源的线ML2所占据。即，第二布线层LY2能够形成实现高阻抗所需的长线。
此外，主要在第二布线层LY2下面的第三布线层LY3形成延伸到该焊盘图形的线。在第一布线层LY1和第二布线层LY2之间，如图4A所示设置第一接地层GND1。此外，在第二布线层LY2和第三布线层LY3之间，如图4C所示设置第二接地层GND2。
采用上述结构，用于晶体管Q1的电源线ML1与用于晶体管Q2的电源线ML2通过设置在它们之间的第一接地层GND1完全分离。结果，在线ML1和线ML2之间不存在电磁耦合。因此，线ML1、ML2和晶体管Q2不形成回路LP1。因此，能够抑制f0/2振荡。
在上面的说明中，已经描述了晶体管Q2的非线性工作。晶体管Q1由于阻抗波动也会像晶体管Q2那样非线性工作。在这种情况下，通过用于晶体管Q1的电源线ML1、输入信号线ML3和输入匹配电路12形成回路LP2，如图1中的虚线所示。即使在这种情况下，在低于线ML1的第二布线层LY2形成输入信号线ML3，并且所述接地层GND1设置在线ML1、ML3之间，如第一实施例中的图4B所示。这使得能够抑制用于晶体管Q1的电源线ML1和输入信号线ML3之间的电磁耦合。结果，可以防止在输入端一侧形成回路LP2。因此，即使当晶体管Q1不仅由于输出端的阻抗波动，而且由于输入端的阻抗波动而落入非线性工作状态时，也能够抑制f0/2振荡。
第二实施例
图5至图6E示出了本发明的第二实施例。该第二实施例应用于比第一实施例中的频带低的例如900 MHz频带的CDMA信号的功率放大器。除了频率等于或者小于第一实施例中的频率的一半之外，第二实施例的主要结构与第一实施例相同。为此，为了实现与第一实施例相同的阻抗，必须将线长制做得比第一实施例中的更长。这样，通过象第一实施例中一样只使用作为第一布线层LY1的顶层区域不能形成用于晶体管Q1的电源线ML1。
为了避免该问题，如图6和7D所示，在第三布线层LY3形成用于晶体管Q1的电源线ML1。如图7B所示，在第二布线层LY2形成用于晶体管Q2的电源线ML2。在用于晶体管Q1的电源线ML1和用于晶体管Q2的电源线ML2之间形成第二接地层GND2。这样，第二接地层GND2把电源线ML1与电源线ML2断开，结果在线ML1和ML2之间不存在电磁耦合。结果，没有形成包含线ML1和ML2的回路，这抑制了f0/2振荡。
此外，采用第二实施例，能够避免输出匹配电路13和用于晶体管Q1的电源线ML1之间的电磁耦合。该电磁耦合可以为另外的回路作出贡献。具体地说，在如图5和6所示的第一布线层LY1形成输出匹配电路13。相反，在如图6和图7D所示的第三布线层LY3形成用于晶体管Q1的电源线ML1。在第一布线层LY1和第三布线层LY3之间，形成第一接地层GND1和第二接地层GND2。这使得能够避免输出匹配电路13和用于晶体管Q1的电源线ML1之间的电磁耦合。结果，能够防止包括输出匹配电路13和用于晶体管Q1的电源线ML1的回路的形成。因此，可以抑制f0/2振荡。
在电源线是在相同布线层形成的常规结构中，当模块输出端的阻抗在最大额定输出(或者28dBm输出)的情况下急剧变化时，观察到f0/2振荡。相反，在与常规结构相同的条件下，在第一和第二实施例中没有观察到f0/2振荡。具体地说，在常规结构中，当输出端子处的阻抗如此变化以至于超过VSWR＝5∶1时，观察到f0/2振荡。然而，在第一和第二实施例中，甚至于当VSWR变化到VSWR＝7∶1时，也没有观察到振荡。
本发明并不限于第一和第二实施例。例如，在电源线ML1和电源线ML2之间形成了一个接地层。然而，也可以在电源线ML1和电源线ML2之间形成两个或者多个接地层。
当然，在不脱离本发明的精神或者实质特征的情况下，仍然可以以其它方式实行或者实施本发明。
工业实用性
如上所述，在将模块微型化的情况下，即使晶体管由于干扰而非线性地工作，本发明也可以抑制f0/2振荡，并因此在高频功率放大器模块的技术领域是有效的。

Claims (20)

1. 一种高频功率放大器，包括：
包含至少第一和第二布线层以及至少一个接地层的基板，其中所述至少一个接地层中的一个设置在所述第一和第二布线层之间；
设置在所述第一布线层，并且放大所提供的高频信号的第一晶体管；
设置在所述第一布线层，并且放大所述第一晶体管的输出信号的第二晶体管；
向所述第一晶体管提供电源，并且设置在所述第一布线层的第一电源线；以及
向所述第二晶体管提供电源，并且设置在所述第二布线层的第二电源线。
2. 根据权利要求1所述的高频功率放大器，其中用导电膜覆盖所述至少一个接地层的大部分表面。
3. 根据权利要求1所述的高频功率放大器，进一步包括将高频信号导向所述第一晶体管，并且形成在所述第二布线层的第三条线。
4. 根据权利要求3所述的高频功率放大器，进一步包括连接在所述第三条线和第一晶体管之间的输入匹配电路，该输入匹配电路在第一布线层形成，并且远离所述第一电源线。
5. 根据权利要求1所述的高频功率放大器，进一步包括连接到所述第二晶体管的输出端的输出匹配电路，该输出匹配电路形成在所述第一布线层，并且远离所述第一电源线。
6. 一种高频功率放大器，包括：
包含至少第一、第二和第三布线层以及设置在所述第二和第三布线层之间的第一接地层的基板；
设置在所述第一布线层，并且放大所提供的高频信号的第一晶体管；
设置在所述第一布线层，并且放大所述第一晶体管的输出信号的第二晶体管；
向所述第一晶体管提供电源，并且设置在所述第三布线层的第一电源线；以及
向所述第二晶体管提供电源，并且设置在所述第二布线层的第二电源线。
7. 根据权利要求6所述的高频功率放大器，其中用导电膜覆盖所述第一接地层的大部分表面。
8. 根据权利要求6所述的高频功率放大器，进一步包括将高频信号导向所述第一晶体管，并且在第二布线层形成的第三条线。
9. 根据权利要求6所述的高频功率放大器，进一步包括：
连接在将高频信号导向所述第一晶体管的所述第三条线和所述第一晶体管之间、并且形成在所述第一布线层的输入匹配电路；以及
设置在所述第一布线层和所述第二布线层之间的第二接地层。
10. 根据权利要求6所述的高频功率放大器，进一步包括：
连接到所述第二晶体管的输出端，并且形成在所述第一布线层的输出匹配电路；以及
设置在所述第一布线层和所述第二布线层之间的所述第二接地层。
11. 一种高频功率放大器，包括：
包含第一和第二布线层以及设置在所述第一和第二布线层之间的第一接地层的基板；
设置在所述第一布线层，并且放大所提供的高频信号的第一晶体管；
设置在所述第一布线层，并且放大所述第一晶体管的输出信号的第二晶体管；
向所述第一晶体管提供电源，并且设置在所述第一布线层的第一电源线；以及
向所述第二晶体管提供电源，并且设置在所述第二布线层的第二电源线。
12. 根据权利要求11所述的高频功率放大器，其中用导电膜覆盖所述第一接地层的大部分表面。
13. 根据权利要求11所述的高频功率放大器，进一步包括将高频信号导向所述第一晶体管，并且形成在所述第二布线层的第三条线。
14. 根据权利要求13所述的高频功率放大器，进一步包括连接在所述第三条线和所述第一晶体管之间的输入匹配电路，该输入匹配电路形成在所述第一布线层，并且远离所述第一电源线。
15. 根据权利要求11所述的高频功率放大器，进一步包括连接到所述第二晶体管的输出端的输出匹配电路，该输出匹配电路形成在所述第一布线层，并且远离所述第一电源线。
16. 一种高频功率放大器，包括：
包含第一、第二和第三布线层以及第一和第二接地层的基板，该第一接地层设置在所述第一和第二布线层之间，并且该第二接地层设置在所述第二和第三布线层之间；
设置在所述第一布线层，并且放大所提供的高频信号的第一晶体管；
设置在所述第一布线层，并且放大所述第一晶体管的输出信号的第二晶体管；
向所述第一晶体管提供电源，并且设置在所述第三布线层的第一电源线；以及
向所述第二晶体管提供电源，并且设置在所述第二布线层的第二电源线。
17. 根据权利要求16所述的高频功率放大器，其中用导电膜覆盖所述第一和第二接地层的大部分表面。
18. 根据权利要求16所述的高频功率放大器，进一步包括将高频信号导向所述第一晶体管，并且形成在所述第二布线层的第三条线。
19. 根据权利要求16所述的高频功率放大器，进一步包括连接在将高频信号导向所述第一晶体管的所述第三条线和所述第一晶体管之间、并且形成在所述第一布线层的输入匹配电路。
20. 根据权利要求16所述的高频功率放大器，进一步包括连接到所述第二晶体管的输出端，并且形成在所述第一布线层的输出匹配电路。
CNB03823274XA 2003-06-10 2003-06-10 高频功率放大器模块 Expired - Fee Related CN100421352C (zh)

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US7769355B2 (en) * 2005-01-19 2010-08-03 Micro Mobio Corporation System-in-package wireless communication device comprising prepackaged power amplifier
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6172567B1 (en) * 1998-08-31 2001-01-09 Hitachi, Ltd. Radio communication apparatus and radio frequency power amplifier
US6249186B1 (en) * 1998-04-10 2001-06-19 Taiyo Yuden Co., Ltd. High-frequency power amplifier circuit and high-frequency power amplifier module

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278701A (ja) * 1990-03-28 1991-12-10 Tdk Corp 高周波増幅器
JPH10197662A (ja) 1996-12-28 1998-07-31 Casio Comput Co Ltd 受信装置
JP3407694B2 (ja) 1999-06-17 2003-05-19 株式会社村田製作所 高周波多層回路部品
JP2002141756A (ja) 2000-10-31 2002-05-17 Kyocera Corp 高周波部品

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249186B1 (en) * 1998-04-10 2001-06-19 Taiyo Yuden Co., Ltd. High-frequency power amplifier circuit and high-frequency power amplifier module
US6172567B1 (en) * 1998-08-31 2001-01-09 Hitachi, Ltd. Radio communication apparatus and radio frequency power amplifier

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