CN100420003C - 一种陶瓷基板及其分断方法 - Google Patents

一种陶瓷基板及其分断方法 Download PDF

Info

Publication number
CN100420003C
CN100420003C CNB2005100339115A CN200510033911A CN100420003C CN 100420003 C CN100420003 C CN 100420003C CN B2005100339115 A CNB2005100339115 A CN B2005100339115A CN 200510033911 A CN200510033911 A CN 200510033911A CN 100420003 C CN100420003 C CN 100420003C
Authority
CN
China
Prior art keywords
ceramic substrate
area
dividing
sealing
sliver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100339115A
Other languages
English (en)
Other versions
CN1841712A (zh
Inventor
孔小花
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
- Core Of Electronic Science And Technology (zhongshan) Co Ltd
Original Assignee
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongfujin Precision Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Hongfujin Precision Industry Shenzhen Co Ltd
Priority to CNB2005100339115A priority Critical patent/CN100420003C/zh
Priority to US11/323,269 priority patent/US7575954B2/en
Publication of CN1841712A publication Critical patent/CN1841712A/zh
Application granted granted Critical
Publication of CN100420003C publication Critical patent/CN100420003C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/0909—Preformed cutting or breaking line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/302—Bending a rigid substrate; Breaking rigid substrates by bending
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

一种陶瓷基板，其内嵌有多个电路单元，陶瓷基板上表面边缘分布有多个辨识点，其每相对的两个辨识点分别与电路单元之间隙处对应，下表面具有多个裂片线分布于多个电路单元之间的间隙位置，陶瓷基板上表面分布有多个辨识点的区域为第一区域，分布有多个电路单元的区域为第二区域。该陶瓷基板分断方法包括以下步骤：在陶瓷基板上表面第一区域贴胶带；在陶瓷基板上表面灌封胶；去除胶带；根据陶瓷基板上表面辨识点的位置切割封胶；沿陶瓷基板下表面的裂片线分断陶瓷基板。该分断方法可以提高切割速度，减少切割刀具的磨损，提升产品良率，降低成本。

Description

一种陶瓷基板及其分断方法
【技术领域】
本发明涉及一种半导体封装及制造工艺，尤其涉及一种封胶压模封装的陶瓷基板及其分断方法。
【背景技术】
众所周知，集成电路的应用日益广泛，举凡计算机网络、通讯设备、家用电气等均与集成电路息息相关。随着电子制造技术的不断发展演进，对集成电路的产品品质需求日益提升。在IC芯片轻、薄、短、小及多功能的要求下，使得电子产业之封装技术不断的推陈出新，为得到高良率和维持应有的生产效益，其中分断制造工艺的良率实为产品品质成功的关键因素之一。
传统的陶瓷基板，尤其是封胶压模制造工艺的陶瓷基板采用切割方法分离产品。参阅图12，为一普通陶瓷基板130的正面视图，在陶瓷基板130中内嵌有多个电路单元132，在其上下表面边缘部分对应于各个电路单元132的间隙位置分布有多个辨识点134。陶瓷基板130上表面与下表面的布局相同。图13为图12所示陶瓷基板130E-E向局部剖视图。参阅图14，对于封胶压模封装的陶瓷基板130，首先，在陶瓷基板130的上表面灌封胶136，用于包覆陶瓷基板130上多个电路单元132。由于陶瓷基板130上表面的辨识点134被封胶136覆盖，因此只能根据陶瓷基板下表面的辨识点134将陶瓷基板130上的电路单元132分断为独立的产品。参阅图15，为切割刀具138切割如图14所示的陶瓷基板130的剖视图。切割刀具138首先根据陶瓷基板130背面的辨识点134切割陶瓷基板130，然后切割封胶136。
又如，2002年7月16日公告的美国第6,420,244号专利揭示了一种制造晶圆级芯片尺寸封装(Wafer Lever of Chip Scale Package)的方法，其方法切割制造工艺中也是采用切割刀具将一具有多个芯片的基板切割成多个独立的芯片。
由于陶瓷基板具有硬而脆的特性，上述现有的陶瓷基板分断方法，均存在切割时容易引起陶瓷基板崩裂、切割速度慢、产能低、且切割刀具磨损快等缺陷，影响产品良率，增加生产成本。
针对上述不足，需要一种可减少切割刀具的磨损、提高切割速度、避免切割时引起陶瓷基板崩裂、降低成本的陶瓷基板分断方法。
【发明内容】
本发明所要解决的技术问题在于提供一种陶瓷基板，可便于切割刀具切割封胶，从而使陶瓷基板易于分断。
本发明所要解决的另一技术问题在于提供一种陶瓷基板分断方法，可实现在陶瓷基板分断的制造工艺中切割刀具不需直接切割陶瓷基板。
本发明提供的陶瓷基板具有上表面及下表面，上表面包括有靠近边缘部分的第一区域和中央部分的第二区域，其第一区域内分布有多个辨识点，下表面形成有多个裂片线，所述裂片线分别与第一区域内的两个相对辨识点的位置上下对应，封胶覆盖于陶瓷基板上表面的第二区域。
本发明提供的分断上述陶瓷基板的方法包括如下步骤：(a)在陶瓷基板上表面第二区域灌封胶；(b)根据陶瓷基板上表面辨识点的位置切割封胶；(c)沿陶瓷基板下表面上的裂片线分断陶瓷基板。
采用本发明所述的陶瓷基板，由于同时采用了辨识点和裂片线，一方面有利于切割刀具准确切割封胶。另一方面也使得在分断陶瓷基板时，切割刀具仅需切割封胶，大大提高了切割速度，减少切割刀具的磨损，防止了因切割陶瓷基板而引起的陶瓷基板崩裂，降低成本。
【附图说明】
图1表示本发明陶瓷基板正面视图。
图2表示图1的A-A向剖视图。
图3表示依本发明陶瓷基板分断方法，在陶瓷基板上表面四边贴胶带的正面视图。
图4表示图3的B-B向剖视图。
图5表示依本发明陶瓷基板分断方法，在陶瓷基板上表面四边胶带内部灌封胶后的正面视图。
图6表示图5的C-C向剖视图。
图7表示依本发明陶瓷基板分断方法，去除陶瓷基板上表面四边胶带后的正面视图。
图8表示图7的D-D向剖视图。
图9表示依本发明陶瓷基板分断方法，用切割刀具切割封胶后的剖视图。
图10表示依本发明陶瓷基板分断方法，在陶瓷基板上表面灌封胶的正面视图。
图11表示依本发明陶瓷基板分断方法，用切割刀具在陶瓷基板上表面灌封胶的四边切割封胶后的剖视图。
图12表示现有的陶瓷基板正面视图。
图13表示图12的E-E向剖视图。
图14表示依现有的陶瓷基板分断方法，在陶瓷基板上灌封胶后的剖视图。
图15表示依现有的陶瓷基板分断方法，用切割刀具切割陶瓷基板及封胶的剖视图。
【具体实施方式】
参阅图1，为本发明陶瓷基板100的正面视图。在陶瓷基板100中内嵌有多个电路单元102，所述电路单元102形成有多个间隙位置，在陶瓷基板100上表面的边缘部分分布有多个辨识点104，每相对的两个辨识点对应于其中一个间隙位置。在本实施方式中，定义陶瓷基板100上表面分布有多个辨识点104的区域为第一区域，定义分布有多个电路单元102的区域为第二区域。该多个辨识点104用于帮助辨识及确定多个电路单元102的准确位置。参阅图2，为本发明陶瓷基板100的A-A向的局部剖视图。该陶瓷基板100的下表面同样也包括有多个电路单元102。不同的是，在陶瓷基板100下表面各电路单元102的间隙处还分布有多条纵向和横向的裂片线106，并且所述裂片线106分别与每相对的两个辨识点104的位置上下对应。
参阅图3，在分断陶瓷基板100时，首先，在陶瓷基板100上表面第一区域上贴胶带108。胶带108以不覆盖任一电路单元102为宜。图4所示为图3的B-B向的局部剖视图。参阅图5，在陶瓷基板100上第二区域灌封胶110，其作用在于包覆多个电路单元102。在本发明的其他实施方式中，也可直接于陶瓷基板100上表面灌封胶，以提高工效。图6为图5的C-C向的局部剖视图。参阅图7，去除胶带108。图8为图7的D-D向的局部剖视图。参阅图9，根据陶瓷基板100上辨识点104的位置切割陶瓷基板100上的封胶110，形成切割道112，切割的深度可大于或等于封胶110的厚度。最后，沿陶瓷基板100下表面的裂片线106裂片，从而分断陶瓷基板100。对于裂片线106的深度，可根据陶瓷基板100的材料及厚度设计，一般为大于或等于1/5的陶瓷基板100厚度。
上述描述为本发明的第一较佳实施方式。图10及图11为本发明的第二较佳实施方式示意图。参阅图10，陶瓷基板120的与陶瓷基板100的布局相同，首先，在陶瓷基板120的上表面灌封胶124，封胶124覆盖整个陶瓷基板120的上表面。参阅图11，沿靠近陶瓷基板120上表面边缘的位置即上表面第一区域与第二区域的交界处切割封胶124，形成切割道126，切割的深度为大于或等于封胶124的厚度。然后，去除陶瓷基板120边缘的封胶124，露出陶瓷基板120上表面的辨识点，得到如图7所示相同的效果。其后的步骤与第一较佳实施方式相同，裂片线122深度也与第一较佳实施方式相同。

Claims (15)

1. 一种陶瓷基板，其具有上表面及下表面，上表面包括有靠近边缘部分的第一区域和中央部分的第二区域，其第一区域内分布有多个辨识点，下表面形成有多个裂片线，所述裂片线分别与第一区域内的两个相对辨识点的位置上下对应，其特征在于：陶瓷基板上表面的第二区域覆盖有封胶。
2. 如权利要求1所述的陶瓷基板，其特征在于所述第二区域内嵌有多个电路单元。
3. 如权利要求2所述的陶瓷基板，其特征在于所述每相对的两个辨识点分别与各电路单元的间隙对应。
4. 如权利要求2所述的陶瓷基板，其特征在于所述多个裂片线形成于陶瓷基板下表面多个电路单元的间隙处。
5. 如权利要求1所述的陶瓷基板，其特征在于所述多个裂片线的深度大于或等于1/5陶瓷基板的厚度。
6. 一种陶瓷基板分断方法，该陶瓷基板包括有上表面及下表面，上表面包括有靠近边缘部分的第一区域和中央部分的第二区域，其第一区域内分布有多个辨识点，下表面形成有多个裂片线，所述裂片线分别与第一区域内的两个相对辨识点的位置上下对应，其特征在于该分断方法包括以下步骤：
(a)在陶瓷基板上表面第二区域灌封胶；
(b)根据陶瓷基板上表面辨识点的位置切割封胶；
(c)沿陶瓷基板下表面上的裂片线分断陶瓷基板。
7. 如权利要求6所述的陶瓷基板分断方法，其特征在于所述第二区域内嵌有多个电路单元。
8. 如权利要求6所述的陶瓷基板分断方法，其特征在于所述步骤(a)包括：
(a1)在陶瓷基板上表面第一区域上贴胶带；
(a2)在陶瓷基板上表面灌封胶；
(a3)去除胶带。
9. 如权利要求6所述的陶瓷基板分断方法，其特征在于所述步骤(b)中切割封胶的深度大于或等于封胶的厚度。
10. 如权利要求6所述的陶瓷基板分断方法，其特征在于所述裂片线的深度为大于或等于1/5陶瓷基板厚度。
11. 如权利要求6所述的陶瓷基板分断方法，其特征在于所述步骤(a)包括：
(a11)在陶瓷基板上表面灌封胶；
(a22)沿陶瓷基板第一区域和第二区域交界处切割封胶；
(a33)去除陶瓷基板边缘的封胶，以露出辨识点。
12. 如权利要求11所述的陶瓷基板分断方法，其特征在于所述步骤(a22)中切割封胶的深度大于或等于封胶的厚度。
13. 一种陶瓷基板分断方法，该陶瓷基板包括有上表面及下表面，上表面包括有靠近边缘部分的第一区域和中央部分的第二区域，其第一区域内分布有多个辨识点，第二区域内分布有多个电路单元，每相对的两个辨识点分别与各电路单元的间隙位置对应，下表面形成有多个裂片线，所述裂片线分别与第一区域内的两个相对辨识点的位置上下对应，其特征在于该分断方法包括以下步骤：
(a)在陶瓷基板上表面第一区域上贴胶带；
(b)在陶瓷基板上表面灌封胶；
(c)去除胶带；
(d)根据陶瓷基板上表面上辨识点的位置切割封胶；
(e)沿陶瓷基板下表面上的裂片线分断陶瓷基板。
14. 如权利要求13所述的陶瓷基板分断方法，其特征在于所述步骤(d)中切割封胶的深度大于或等于封胶的厚度。
15. 如权利要求13所述的陶瓷基板分断方法，其特征在于所述裂片线的深度为大于或等于1/5陶瓷基板的厚度。
CNB2005100339115A 2005-03-29 2005-03-29 一种陶瓷基板及其分断方法 Expired - Fee Related CN100420003C (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CNB2005100339115A CN100420003C (zh) 2005-03-29 2005-03-29 一种陶瓷基板及其分断方法
US11/323,269 US7575954B2 (en) 2005-03-29 2005-12-30 Ceramic substrate and method of breaking same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100339115A CN100420003C (zh) 2005-03-29 2005-03-29 一种陶瓷基板及其分断方法

Publications (2)

Publication Number Publication Date
CN1841712A CN1841712A (zh) 2006-10-04
CN100420003C true CN100420003C (zh) 2008-09-17

Family

ID=37030645

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100339115A Expired - Fee Related CN100420003C (zh) 2005-03-29 2005-03-29 一种陶瓷基板及其分断方法

Country Status (2)

Country Link
US (1) US7575954B2 (zh)
CN (1) CN100420003C (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101530011A (zh) * 2006-11-30 2009-09-09 株式会社德山 金属化陶瓷基板芯片的制造方法
US8263876B2 (en) * 2009-12-30 2012-09-11 Harvatek Corporation Conductive substrate structure with conductive channels formed by using a two-sided cut approach and a method for manufacturing the same
KR102521372B1 (ko) * 2016-02-12 2023-04-14 삼성전자주식회사 마크 위치 예측 방법
BE1023850B1 (nl) * 2016-06-29 2017-08-14 C-Mac Electromag Bvba Verbeterde elektronische schakeling en substraat met identificatiepatroon voor afzonderlijke elektronische schakelingen en werkwijze voor het produceren daarvan
CN108430179A (zh) * 2018-02-11 2018-08-21 广东欧珀移动通信有限公司 制备移动终端壳体的方法、移动终端壳体和移动终端
JP6550516B1 (ja) * 2018-09-18 2019-07-24 レノボ・シンガポール・プライベート・リミテッド パネル、ｐｃｂおよびｐｃｂの製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110716A (ja) * 2000-09-29 2002-04-12 Kyocera Corp 半導体装置の製造方法
US20020056892A1 (en) * 1998-11-12 2002-05-16 Corisis David J. Semiconductor package
JP2003133347A (ja) * 2001-10-22 2003-05-09 Murata Mfg Co Ltd 電子部品の製造方法および電子部品

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW451436B (en) 2000-02-21 2001-08-21 Advanced Semiconductor Eng Manufacturing method for wafer-scale semiconductor packaging structure
JP2005026314A (ja) * 2003-06-30 2005-01-27 Sanyo Electric Co Ltd 固体撮像素子の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020056892A1 (en) * 1998-11-12 2002-05-16 Corisis David J. Semiconductor package
JP2002110716A (ja) * 2000-09-29 2002-04-12 Kyocera Corp 半導体装置の製造方法
JP2003133347A (ja) * 2001-10-22 2003-05-09 Murata Mfg Co Ltd 電子部品の製造方法および電子部品

Also Published As

Publication number Publication date
US20060223228A1 (en) 2006-10-05
US7575954B2 (en) 2009-08-18
CN1841712A (zh) 2006-10-04

Similar Documents

Publication Publication Date Title
CN100420003C (zh) 一种陶瓷基板及其分断方法
US7008825B1 (en) Leadframe strip having enhanced testability
JP3013347B2 (ja) 半導体パッケージを製作する方法
HK1035261A1 (en) Method for producing semiconductor device.
JP2002064114A (ja) 半導体装置及びその製造方法
CN101101880A (zh) 散热型封装结构及其制法
CN102104021B (zh) 晶片切割方法
US6286499B1 (en) Method of cutting and separating a bent board into individual small divisions
CN103855058B (zh) 电子元件制造装置及制造方法
CN101404270A (zh) 半导体器件及其制造方法和半导体基板
JP3896029B2 (ja) 混成集積回路装置の製造方法
JP2007048876A (ja) 半導体装置の製造方法
CN102842511A (zh) 芯片封装方法及使用该方法制造的晶圆
CN102782829A (zh) 具有非均匀真空分布的裸芯安装端部
JP4039881B2 (ja) 混成集積回路装置の製造方法
JP4606447B2 (ja) 中板の金属基板の製造方法。
JP2000091273A (ja) 半導体パッケージの製造方法およびその構造
JP2004006585A (ja) 混成集積回路装置の製造方法
JPS62112333A (ja) ミニモ−ルド型半導体素子の製造方法
CN204216033U (zh) 引线框架、半导体封装体
JP2000124163A (ja) 半導体装置及びその製造方法
CN106548950A (zh) 用于制作具有台阶式侧壁的ic的方法及相关ic器件
CN102903684A (zh) 半导体晶片、芯片、具有该芯片的半导体封装件及其制法
CN105633027A (zh) 扇出晶圆级芯片封装结构及其制造方法
CN1355553A (zh) 晶片切割研磨制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090123

Address after: No. two, 2 East Ring Road, tenth Pine Industrial Zone, Longhua Town, Guangdong City, Shenzhen Province, China: 518109

Co-patentee after: Hon Hai Precision Industry Co., Ltd.

Patentee after: Fujin Precision Industry (Shenzhen) Co., Ltd.

Co-patentee after: Ambit Electronics (Zhongshan) Co., Ltd.

Address before: No. two, 2 East Ring Road, tenth Pine Industrial Zone, Longhua Town, Guangdong City, Shenzhen Province, China: 518109

Co-patentee before: Hon Hai Precision Industry Co., Ltd.

Patentee before: Fujin Precision Industry (Shenzhen) Co., Ltd.

ASS Succession or assignment of patent right

Free format text: FORMER OWNER: HON HAI PRECISION INDUSTRY CO., LTD. AMBIT MICROSYSTEMS (ZHONGSHAN) CORPORATION

Effective date: 20121212

Owner name: AMBIT MICROSYSTEMS (ZHONGSHAN) CORPORATION

Free format text: FORMER OWNER: FOXCONN PRECISION INDUSTRY (SHENZHEN) CO., LTD.

Effective date: 20121212

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 518109 SHENZHEN, GUANGDONG PROVINCE TO: 528437 ZHONGSHAN, GUANGDONG PROVINCE

TR01 Transfer of patent right

Effective date of registration: 20121212

Address after: 528437 export processing zone of Torch Development Zone, Guangdong, Zhongshan

Patentee after: Ambit Electronics (Zhongshan) Co., Ltd.

Address before: 518109 Guangdong city of Shenzhen province Baoan District Longhua Town Industrial Zone tabulaeformis tenth East Ring Road No. 2 two

Patentee before: Hongfujin Precise Industry (Shenzhen) Co., Ltd.

Patentee before: Hon Hai Precision Industry Co., Ltd.

Patentee before: Ambit Electronics (Zhongshan) Co., Ltd.

C56 Change in the name or address of the patentee

Owner name: XUNXIN ELECTRONIC TECHNOLOGY (ZHONGSHAN) CO., LTD.

Free format text: FORMER NAME: AMBIT MICROSYSTEMS (ZHONGSHAN) CORPORATION

CP03 Change of name, title or address

Address after: 528437 No. 9 Jianye East Road, Torch Development Zone, Guangdong, Zhongshan

Patentee after: - the core of Electronic Science and Technology (Zhongshan) Co., Ltd.

Address before: 528437 export processing zone of Torch Development Zone, Guangdong, Zhongshan

Patentee before: Ambit Electronics (Zhongshan) Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080917

Termination date: 20210329

CF01 Termination of patent right due to non-payment of annual fee