CN100390989C - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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CN100390989C
CN100390989C CNB2006100585006A CN200610058500A CN100390989C CN 100390989 C CN100390989 C CN 100390989C CN B2006100585006 A CNB2006100585006 A CN B2006100585006A CN 200610058500 A CN200610058500 A CN 200610058500A CN 100390989 C CN100390989 C CN 100390989C
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wiring layer
circuit arrangement
metal level
arrangement according
substrate
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CN1841726A (zh
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水野崇人
山本炼
胁田茂
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Toyota Motor Corp
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Abstract

本发明涉及电路装置及其制造方法。该电路装置包括陶瓷基底，设置在陶瓷基底上的铝配线层以及电连接到配线层上的半导体装置和母线。配线层的一部分上镀有镍层。因而，提供了其中配线层覆盖有焊料润湿性优于铝的镍的被覆盖区域，以及其中从陶瓷基底上方看配线层被暴露的暴露区域。半导体装置通过焊料连接到被覆盖区域中的镍层。母线通过超声波接合到从陶瓷基底上方看被暴露的暴露区域内的配线层。因此，提供了包括以足够的接合强度接合到陶瓷基底上的半导体装置和母线的电路装置及其制造方法。

Description

电路装置及其制造方法
技术领域
本发明涉及一种其中半导体装置(器件)和母线接合到陶瓷基板上的电路装置及其制造方法，更具体地，本发明涉及一种包括在其表面上形成有作为主要部件的铝制配线层的陶瓷基底的电路装置及其制造方法。
背景技术
到目前为止，已知其中在基板上装有多个半导体装置和母线的电路装置。这种基板的示例可包括以陶瓷材料为基体的陶瓷基底。例如，在许多情况下使用一种被称为“DBA(直接接合铝)基板”的基板，其中在铝氮化物(AlN)基底的两面形成铝(Al)配线层。为了通过焊接将半导体装置等接合到基板上，例如铝层的表面通常都覆盖有镍镀层或其它材料镀层。
然而，在采用上述基板的动力模块中，在使用过程中由于半导体芯片发热所导致的热冲击可能会传递到焊料层。因此，焊料层可能会破裂，基板也很可能会因热膨胀系数不同而发生翘曲或断裂。另一方面，在日本待审专利申请公报No.11-346037(1999)中，已经提出了将陶瓷基板接合到母线部上的技术。该专利申请公报表明这种构造可减小因母线部与陶瓷基底之间热膨胀系数不同而导致的应力。
在日本待审专利申请公报No.2002-9190中，已经提出了一种利用超声波焊接技术将金属引线接合到形成于陶瓷基底上的金属电路层上的技术。这种技术能在不需加热的情况下进行接合。因此，可能减小对陶瓷与金属之间界面的影响，并增强接合可靠性。该待审专利申请公报还声明，金属电路层的材料和金属引线优选地包括相同的金属作为主要成分，同时还声明金属电路层的表面可以覆盖镍镀层。
然而，上述常规技术具有以下问题。’037号公报中的技术需要将陶瓷基板接合到母线上，从而导致部件数量增加并且制造工艺复杂。此外，母线与陶瓷基板间的接合部可能导致如上所述与热有关的问题。
与采用热接合技术的情况相比，’190号公报中的技术可充分避免诸如接合部因热而断裂的问题。因此，本发明的发明人已经尝试将铜母线利用超声波接合到典型的覆盖有镍镀层的DBA基板上。然而，该技术很难获得足够的接合性能。为了找出问题的原因，发明人将母线从基底上剥下来，进而检查接合部。通过检查发现，在接合部的中央部，母线和基底并没有适当地接合在一起。下面说明其原因。
如图6所示，进行上述检查的常规电路装置的基板100具有的结构为：在由铝氮化物等作为主要成分制成的陶瓷基底11的表面上形成有铝(Al)制配线层12，在配线层12上镀有镍层13。半导体装置20通过焊料21接合到基板100上。图6示出母线30接合到基板100前的状态。
然后，将超声波焊头(horn)40设置成与放置在基板100上的母线30相接触以进行超声波接合。在这个阶段，如图7所示，超声波焊头40使母线30振动。与Ni层13相比，形成基板100的配线层12的Al层很软。因此，可以发现，用于超声波接合的振动导致Al层发生很大的变形以至于Ni层13被吸入配线层12中。具体地，振动的能量不能被适当地传递到接触面，即Ni层13。
实际上，在图7中所示的接合区域的大多数部位，母线30和基板100都没有被适当地接合在一起。尤其是在接合区域的中央部位，母线30仅仅是与Ni层13搭接而没有接合在一起。另一方面，在接合区域的端部，镍层13断裂并且被推开，从而母线30接合到铝配线层12。因而，实际的接合区域小，不能提供足够的接合强度。
发明内容
本发明鉴于上述情况而提出，其目的是提供一种其中半导体装置和母线以足够的接合强度接合到陶瓷基板上的电路装置及其制造方法。本发明的其它目的和优点一部分在下面的说明中阐明，一部分可从说明书中明显看出，或者可通过本发明的实践得出。本发明的目的和优点可通过尤其是在所附权利要求中指出的装置以及组合实现和获得。
为了实现本发明的目的，提供了一种安装有功能装置和外部引出导体的电路装置，该电路装置包括：基底；设置在所述基底上并与所述功能装置和所述外部引出导体电连接的配线层；以及形成在所述配线层的一部分上的覆盖金属层，其将所述配线层分为被覆盖金属层覆盖的被覆盖区域，以及被暴露的暴露区域；其中，所述功能装置连接到位于所述被覆盖区域内的所述覆盖金属层；以及所述外部引出导体接合到所述配线层的位于所述暴露区域内的一部分。
根据本发明的另一方面，提供了一种安装有功能装置和外部引出导体的电路装置的制造方法，该方法包括以下步骤：在形成于基底上的配线层上部分地形成覆盖金属层，从而提供其中所述配线层被覆盖的被覆盖区域和其中所述配线层被暴露的暴露区域；将所述功能装置连接到位于所述被覆盖区域内的所述覆盖金属层；以及将所述外部引出导体接合到所述配线层的位于所述暴露区域内的一部分。
根据本发明，功能装置和外部引出导体电连接到包括由陶瓷等制成的其上形成有配线层的基底的基板上。功能装置被连接到其中配线层覆盖有覆盖金属层的被覆盖区域。另一方面，外部引出导体直接连接到其中配线层未覆盖覆盖金属层从而暴露的暴露区域内的配线层上。因此，可以为每个接合部选择适当的接合技术。例如，对于铝配线层，外部引出导体通过超声波接合被接合到配线层，从而能够以足够的接合强度被接合。此外，对于由镍(Ni)、铜(Cu)或其它焊料润湿性优于铝的材料制成的覆盖金属层，功能装置通过焊接被接合到覆盖金属层上，从而它们能够以足够的接合强度被接合。
根据本发明的电路装置及其制造方法，半导体装置和母线能够以足够的接合强度被接合到陶瓷基板上。
附图说明
结合入本说明书中并构成本说明书的一部分的附图示出本发明的一个实施例，并与说明书一起用于说明本发明的目的、优点和原理。
在附图中：
图1是本实施例中电路装置的一部分的截面图；
图2是电路装置的一部分的俯视图；
图3是电路装置的局部放大截面图；
图4是示出用于电路装置中的陶瓷基板的示意图；
图5是示出本实施例中的接合方法的示意图；
图6是示出常规接合方法的示意图；以及
图7是示出通过常规接合方法的接合状态的示意图。
具体实施方式
现在参照附图详细说明本发明的一个优选实施例。在本实施例中，本发明应用于一个其中半导体装置和母线接合到陶瓷基板上的电路装置。
如图1(截面图)和图2(俯视图)所示，本实施例中的电路装置1由接合到基板10上的半导体装置20(IGBT等)和母线30构成。基板10包括铝氮化物等作为主要成分制成的陶瓷基底11、形成于陶瓷基底11的两面的由铝制成的配线层12、以及相当于镀在配线层12的表面的覆盖金属层的镍层13。也可以采用镀铜层代替镍层13。半导体装置20通过焊料21接合到基板10的上表面(图中)。
母线30相当于形成为弯曲形的铜片的外部引出导体。仅其端部30a接合到基板10上。基部30b由壳体31支承，与基板10隔开。与常规布置相比，该布置使基板10在俯视图中的面积更小。壳体31固定在散热板23上以保持其整体强度和形状。此处，图1在其左右方向上示出整个电路装置1的大约一半。电路装置1实际上还包括另外的一半(位于所示一半的右侧)，其具有的部件与图1中所示的部分基本对称。图2仅以俯视图的形式示出电路装置1的很少一部分。实际上，在纵向和横向连续地布置有多个具有基本相同或对称的结构的基板10，这些基板10接合到一个散热板23上(图2中省略该散热板)。
图3是图1所示电路装置1的局部放大图。如图2和图3所示，在基板10的与母线30的端部30a接合的部位及其周围，未镀有镍层13。具体地，在端部30a的周围设置有其中铝配线层12被暴露的暴露区域32。端部30a直接接合到暴露区域32中的铝配线层12。暴露区域32之外的配线层12覆盖有镍层13。换句话说，本实施例中的基板10具有其中铝配线层12被暴露的暴露区域32，和其中铝配线层12覆盖有镍层13的被覆盖区域33。
铝在暴露的情况下容易被氧化，形成氧化物膜，因此通过焊料21接合相当困难。另一方面，利用超声波接合将母线30接合到具有镍层13的配线层12具有如上文提到的接合性能问题。为了避免这种问题，本实施例中的电路装置1设置成：配线层12中半导体装置20通过焊料21接合到其上的一部分覆盖有镍层13，而母线30通过超声波接合而接合到其上的其余部分未覆盖有镍层13。
图4示出用于本实施例中的基板10的一个示例。在陶瓷基底11的表面上形成铝配线层12，其形状根据与之接合的各个部件的构造决定。在配线层12除了对应于与母线30的端部30a相接合的位置的暴露区域32之外的部分上形成有镍层13。暴露区域32覆盖至少端部30a与铝配线层12相接触的范围和不干扰半导体装置20通过焊料21接合的位置的范围。考虑到端部30a的接触区域的变化和公差，暴露区域32优选被设计成具有适当的空白区域。在暴露区域32中，构成其底层的铝配线层12是可见的。
接下来，说明本实施例中的电路装置1的制造方法。该制造方法包括依次执行的配线层形成工艺、局部电镀工艺、装置接合工艺以及超声波接合工艺。首先，配线层形成工艺是在陶瓷基底11上形成铝配线层12的工艺。该工艺与常规工艺相同。
局部电镀工艺是在配线层12上局部覆盖镍镀层的工艺。在该局部电镀方法中，例如仅在相当于暴露区域32的区域，即与端部30a及其周围的环绕区域上设置掩模之后覆盖镍镀层。这样，暴露区域32将不会覆盖镍。或者，可采用另一种方法，其中，整个配线层12都覆盖有镍镀层，除暴露区域32之外的区域，即被覆盖区域33都加有掩模，然后，通过蚀刻等去除未加掩模区域上的镀层。这样，通过蚀刻技术去除镀在暴露区域32的镍层。在任一种情况下，都在所有工艺操作完成之后去除掩模。这样，最终形成图4所示的基板10。
随后的装置接合工艺是将各个半导体装置20焊接到基板10上每个预定位置的工艺。在各半导体装置20的焊接部位，已形成上述镍层13。由于镍是具有良好焊料润湿性的金属，可容易地以足够的接合强度将半导体装置20焊接到镍层13上。该工艺与常规工艺相同。
超声波接合工艺是利用超声波将母线30接合到配线层12的工艺。母线30的端部30a被放置在基底10上预定的位置，将超声波焊头40设置成从上方与端部30a相接触。此时，端部30a在图中的下表面保持与形成配线层12的铝层直接接触。当致动超声波焊头40使之振动时，其振动能量适当传递到端部30a，并通过端部30a传递到配线层12。如图5所示，端部30a能以强接合强度接合到配线层12，这是因为铝氧化所导致的氧化物膜不会在超声波接合方法中导致问题。
此外，由于超声波接合方法不需要热，因此不会影响焊料21、22以及配线层12。母线30的另一端，即，与配线层12接合的端部之外的一端，通常直接连接到容纳电路装置1的壳体上。从而，壳体上的振动或应力将传递到外部引出导体上。由于母线30的刚性通常高，这种振动或应力容易无衰减地直接传递到接合部位。一般而言，与焊料接合相比，超声波接合能提供更高的接合强度。因此，根据本实施例，母线30可牢靠地接合以能够承受传递到其上的振动或应力。
如上所述，根据本实施例的制造方法，可制造其中半导体装置20和母线30两者都适当接合的电路装置1。在本实施例的说明中，以先进行装置接合工艺然后进行超声波接合工艺的顺序接合半导体装置20和母线30。可选地，也可以按与上述顺序相反的顺序进行这些工艺。
下面说明本发明的发明者进行的评估测试的结果。此处，针对端部30a与铝层的接触面积约为11mm2的母线30的接合进行测试。超声波接合的接合条件为：频率为21kHz，振幅为44μm，压制力为160N，时间为1.2秒。将在该接合测试中接合的端部30a的接合部从铝层上剥下来，检查实际接合部的面积。检查发现，几乎端部30a的所有接触区域接合到铝层上，因此接合部的面积足以提供足够的接合强度。在多点测试中，即使是最差的结果也要优于利用常规技术进行测试所获得的最好结果。此外，完全能够达到所要求水平的接合质量。
根据本发明的电路装置1，如上述详细说明，镍层13镀在具有铝配线层12的基板10上除了母线要焊接的暴露区域32之外的表面上。因此，各个半导体装置20可容易地利用焊料21接合到形成有镍层13的被覆盖区域33上。另一方面，可容易地利用超声波将母线30接合到其中铝配线层12被暴露的暴露区域32。这还可以获得足够的接合面积和接合强度。因此，电路装置1可布置成使得半导体装置20和母线30各自都能以足够的接合强度接合到作为主要部件的由陶瓷制成的基板10上。
本发明可以在不背离其精神或实质特征的情况下体现为其它具体形式。例如，本实施例中示出的基板10、配线层12、母线30等部件的形状仅仅是作为示例而并不是对其进行限制。铝、镍和铜可以不是纯的。尽管已经示出和说明本发明的当前优选实施例，但是应当理解，本公开是以说明为目的，在不超出所附权利要求阐述的本发明的范围的情况下，可给出各种变化和变型。

Claims (12)

1.一种安装有功能装置和外部引出导体的电路装置，该电路装置包括：
基底；
设置在所述基底上并与所述功能装置和所述外部引出导体电连接的配线层；以及
形成在所述配线层的一部分上的覆盖金属层，其将所述配线层分为被覆盖金属层覆盖的被覆盖区域，以及被暴露的暴露区域；
其中，所述功能装置连接到位于所述被覆盖区域内的所述覆盖金属层；以及
所述外部引出导体接合到所述配线层的位于所述暴露区域内的一部分。
2.根据权利要求1所述的电路装置，其特征在于，所述配线层由铝制成。
3.根据权利要求2所述的电路装置，其特征在于，所述覆盖金属层由焊料润湿性优于铝的金属制成。
4.根据权利要求3所述的电路装置，其特征在于，所述功能装置经由焊料连接到位于所述被覆盖区域内的所述覆盖金属层。
5.根据权利要求3所述的电路装置，其特征在于，所述覆盖金属层由镍或铜制成。
6.根据权利要求1所述的电路装置，其特征在于，所述外部引出导体通过超声波接合被接合到位于所述暴露区域内的所述配线层上。
7.一种安装有功能装置和外部引出导体的电路装置的制造方法，该方法包括以下步骤：
在形成于基底上的配线层上部分地形成覆盖金属层，从而提供其中所述配线层被覆盖的被覆盖区域和其中所述配线层被暴露的暴露区域；
将所述功能装置连接到位于所述被覆盖区域内的所述覆盖金属层；以及
将所述外部引出导体接合到所述配线层的位于所述暴露区域内的一部分。
8.根据权利要求7所述的电路装置的制造方法，其特征在于，所述配线层由铝制成。
9.根据权利要求8所述的电路装置的制造方法，其特征在于，所述覆盖金属层由焊料润湿性优于铝的金属制成。
10.根据权利要求9所述的电路装置的制造方法，其特征在于，所述功能装置经由焊料连接到位于所述被覆盖区域内的所述覆盖金属层。
11.根据权利要求9所述的电路装置的制造方法，其特征在于，所述覆盖金属层由镍或铜制成。
12.根据权利要求7所述的电路装置的制造方法，其特征在于，所述外部引出导体通过超声波接合被接合到位于所述暴露区域内的所述配线层。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7444197B2 (en) * 2004-05-06 2008-10-28 Smp Logic Systems Llc Methods, systems, and software program for validation and monitoring of pharmaceutical manufacturing processes
US7799273B2 (en) 2004-05-06 2010-09-21 Smp Logic Systems Llc Manufacturing execution system for validation, quality and risk assessment and monitoring of pharmaceutical manufacturing processes
WO2006086274A2 (en) * 2005-02-08 2006-08-17 Dyno Nobel Inc. Delay units and methods of making the same
JP4965242B2 (ja) * 2006-12-27 2012-07-04 株式会社ティラド アルミニューム製ヒートシンクの製造方法
JP5102497B2 (ja) * 2007-01-19 2012-12-19 Ｄｏｗａメタルテック株式会社 金属セラミックス接合回路基板の製造方法
JP2008277438A (ja) * 2007-04-26 2008-11-13 Ricoh Microelectronics Co Ltd 電子部品、基板、並びに、電子部品及び基板の製造方法
JP4935735B2 (ja) * 2008-03-26 2012-05-23 トヨタ自動車株式会社 バスバー及びその製造方法
DE102008018841A1 (de) * 2008-04-15 2009-10-22 Conti Temic Microelectronic Gmbh Verfahren zur Herstellung und Aufbau eines Leistungsmoduls
JP2010239033A (ja) * 2009-03-31 2010-10-21 Honda Motor Co Ltd 半導体装置及びその製造方法
JP2013506310A (ja) * 2009-09-28 2013-02-21 アーベーベー・テヒノロギー・アーゲー 回路装置およびその製造方法
AU2011224469B2 (en) 2010-03-09 2014-08-07 Dyno Nobel Inc. Sealer elements, detonators containing the same, and methods of making
EP2628173A2 (en) 2010-10-13 2013-08-21 ABB Research Ltd. Semiconductor module and method of manufacturing a semiconductor module
US20130175704A1 (en) 2012-01-05 2013-07-11 Ixys Corporation Discrete power transistor package having solderless dbc to leadframe attach
JP2013235882A (ja) 2012-05-07 2013-11-21 Mitsubishi Electric Corp 半導体装置
US8716864B2 (en) * 2012-06-07 2014-05-06 Ixys Corporation Solderless die attach to a direct bonded aluminum substrate
SE537793C2 (sv) * 2012-08-29 2015-10-20 Jan Berglund Med Inco Innovation F Kraftledare monterad på ett mönsterkort
GB2509002B (en) * 2012-08-29 2014-09-10 Inco Innovation Power chain on a circuit board
WO2014049740A1 (ja) * 2012-09-26 2014-04-03 トヨタ自動車株式会社 電気部品
US8987911B2 (en) 2012-12-31 2015-03-24 Ixys Corporation Silver-to-silver bonded IC package having two ceramic substrates exposed on the outside of the package
DE102013221090A1 (de) * 2013-10-17 2015-04-23 Continental Teves Ag & Co. Ohg Elektronisches Steuergerät und Verfahren zur Anordnung und elektrischen Anbindung elektronischer Bauelemente auf einem Schaltungsträger
US9312231B2 (en) * 2013-10-31 2016-04-12 Freescale Semiconductor, Inc. Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process
JP2015201505A (ja) * 2014-04-07 2015-11-12 三菱電機株式会社 半導体装置
JP6468984B2 (ja) 2015-10-22 2019-02-13 三菱電機株式会社 半導体装置
JP6665664B2 (ja) * 2016-04-27 2020-03-13 富士電機株式会社 半導体装置及びその製造方法
KR102239209B1 (ko) * 2018-10-24 2021-04-12 대산전자(주) 도금방법 및 도금체
CN111751272B (zh) * 2020-07-03 2021-09-07 北京理工大学 一种粘接强度等级超声检测与拉伸标定试验方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11346037A (ja) * 1998-05-29 1999-12-14 Kyocera Corp 放熱用基板
US6166937A (en) * 1998-06-02 2000-12-26 Hitachi Ltd. Inverter device with cooling arrangement therefor
JP2002009190A (ja) * 2000-06-16 2002-01-11 Ngk Spark Plug Co Ltd セラミック基板及びその製造方法
EP1187198A2 (en) * 2000-09-04 2002-03-13 Dowa Mining Co., Ltd. Metal-ceramic circuit board and manufacturing method thereof
CN1368760A (zh) * 2001-02-06 2002-09-11 三菱电机株式会社 半导体设备
JP2003060129A (ja) * 2001-08-09 2003-02-28 Denki Kagaku Kogyo Kk 回路基板及び回路基板の部分メッキ方法
CN1430272A (zh) * 2001-12-26 2003-07-16 株式会社日立制作所 半导体装置及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386576A (en) * 1977-01-10 1978-07-31 Nec Corp Package for semiconductor element
JPH0620998B2 (ja) * 1988-01-20 1994-03-23 株式会社豊田自動織機製作所 スプレッダの位置合わせ装置
JP2963289B2 (ja) * 1992-11-30 1999-10-18 ユニ・チャーム株式会社 体液吸収性物品の表面シート
JP3524360B2 (ja) 1997-12-26 2004-05-10 株式会社東芝 半導体装置およびその製造方法
JP2000232189A (ja) 1999-02-10 2000-08-22 Toshiba Corp 半導体装置
JP2002164461A (ja) 2000-11-24 2002-06-07 Kyocera Corp セラミック回路基板
US6787706B2 (en) * 2001-02-21 2004-09-07 Kyocera Corporation Ceramic circuit board
US6670216B2 (en) * 2001-10-31 2003-12-30 Ixys Corporation Method for manufacturing a power semiconductor device and direct bonded substrate thereof
DE10157362B4 (de) * 2001-11-23 2006-11-16 Infineon Technologies Ag Leistungsmodul und Verfahren zu seiner Herstellung
JP2003188310A (ja) 2001-12-18 2003-07-04 Denki Kagaku Kogyo Kk 電極端子付き回路基板の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11346037A (ja) * 1998-05-29 1999-12-14 Kyocera Corp 放熱用基板
US6166937A (en) * 1998-06-02 2000-12-26 Hitachi Ltd. Inverter device with cooling arrangement therefor
JP2002009190A (ja) * 2000-06-16 2002-01-11 Ngk Spark Plug Co Ltd セラミック基板及びその製造方法
EP1187198A2 (en) * 2000-09-04 2002-03-13 Dowa Mining Co., Ltd. Metal-ceramic circuit board and manufacturing method thereof
CN1368760A (zh) * 2001-02-06 2002-09-11 三菱电机株式会社 半导体设备
JP2003060129A (ja) * 2001-08-09 2003-02-28 Denki Kagaku Kogyo Kk 回路基板及び回路基板の部分メッキ方法
CN1430272A (zh) * 2001-12-26 2003-07-16 株式会社日立制作所 半导体装置及其制造方法

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DE602006000104D1 (de) 2007-10-25
JP2006278913A (ja) 2006-10-12
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