CN100386852C - 形成半导体器件的钝化膜的方法 - Google Patents

形成半导体器件的钝化膜的方法 Download PDF

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CN100386852C
CN100386852C CNB200510005526XA CN200510005526A CN100386852C CN 100386852 C CN100386852 C CN 100386852C CN B200510005526X A CNB200510005526X A CN B200510005526XA CN 200510005526 A CN200510005526 A CN 200510005526A CN 100386852 C CN100386852 C CN 100386852C
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CN1722378A (zh
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金相德
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SK Hynix Inc
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Abstract

公开一种制造半导体器件的方法及一种半导体器件的结构。一种形成半导体器件的钝化膜的方法包括下列步骤：在一半导体衬底上形成多条金属线；在该金属线上形成一作为第一钝化膜的缓冲氧化膜，其中该缓冲氧化膜不通过施加偏置功率形成且可减轻等离子体所造成的损伤；在该缓冲氧化膜上形成一作为第二钝化膜的HDP膜，其中该HDP膜通过施加偏置功率形成，和该缓冲氧化膜和该HDP膜在同一反应室中在原处形成；以及在该第二钝化膜上形成第三钝化膜。依据本发明，有可能显著地减少在选择源极线与公共源极线间的漏电流。

Description

形成半导体器件的钝化膜的方法
技术领域
本发明涉及一种制造半导体器件的方法以及一种半导体器件的结构。更具体地，本发明涉及一种形成半导体器件的钝化膜的方法以及一种半导体器件的钝化膜的结构，其中可显著地减少选择源极线与公共源极线间的漏电流。
背景技术
通常，将半导体存储器件分类成：在停止供电时所储存的信息会丢失的易失性存储器件以及在停止供电时仍可保持所储存的信息的非易失性存储器件。该非易失性存储器件包括可擦除可编程只读存储器(ErasableProgrammable Read Only Memory，EPROM)、电可擦除可编程只读存储器(Electrically Erasable Programmable Read Only Memory，EEPROM)、闪存等。
闪存器件依据单元的结构可分类成NOR型及NAND型。NAND型闪存的单元阵列区域由许多单元组(strings)所构成。一单元组连接16或32个单元。每一单元组包括以串联方式连接的一单元组选择晶体管、多个单元晶体管及一接地选择晶体管。单元组选择晶体管的漏极区域连接至一位线，以及该接地选择晶体管的源极连接至一公共源极线。
在这种NAND型闪存器件中，使用一高密度等离子体(以下称为“HDP”)膜来作为钝化膜(passivation film)。该HDP膜通过化学气相淀积(CVD)方法形成，金属线之间相互绝缘。然而，当通过CVD方法形成该HDP膜时，等离子体电荷会通过该金属线渗透至该半导体器件中。这会导致在选择源极线与公共源极线间产生超过一参考值(例如：5×10-12A)的漏电流。当通过一绝缘膜作为该选择源极线与该公共源极线间的隔离时，要求不会产生超过一给定参考值的漏电流。实际上，在一直到实施过金属线工序的晶片中不会产生超过一给定参考值的漏电流。然而，在实施该HDP膜形成工序之后，会产生大量的漏电流。
发明内容
因此，有鉴于上述问题而提出本发明，而且本发明的一目的在于提供一种形成半导体器件的钝化膜的方法，其中可显著地减少选择源极线与公共源极线间的漏电流。
本发明的另一目的在于提供一种半导体器件的钝化膜的结构，其中可大大地减少选择源极线与公共源极线间的漏电流。
为了实现上述目的，依据本发明，提供一种形成半导体器件的钝化膜的方法，其包括下列步骤：在一半导体衬底上形成多条金属线；在该金属线上形成一作为第一钝化膜的缓冲氧化膜，其中该缓冲氧化膜不通过施加偏置功率形成且可减轻等离子体所造成的损伤；在该缓冲氧化膜上形成一作为第二钝化膜的HDP膜，其中该HDP膜通过施加偏置功率形成，和该缓冲氧化膜和该HDP膜在同一反应室中在原处形成；以及在该第二钝化膜上形成包括氮化硅膜的第三钝化膜。
该缓冲氧化膜可由使用硅烷(SiH4)气体作为硅源气体及氧气作为氧源气体所形成的氧化硅膜构成。
该缓冲氧化膜可在250到400℃温度及1到15mTorr压力下通过注入硅源气体及氧源气体形成。该硅源气体为硅烷气体且该氧源气体为氧气，并且该缓冲氧化膜可通过在10到100sccm的流速下注入该硅源气体及在15到200sccm的流速下注入该氧源气体来形成。
该缓冲氧化膜形成约50到
Figure C20051000552600041
的厚度，其中该厚度的程度可充分地防止在形成该HDP膜时等离子体电荷渗透至该金属线中。
该HDP膜可在250到400℃温度及1到15mTorr压力下通过注入硅烷气体及氧气及施加1000到5000W的源功率及1000到4000W的偏置功率来形成。该HDP膜可通过在30到150sccm的流速下注入硅烷气体及在40到300sccm的流速下注入氧气来形成。
该氮化硅膜可通过等离子体增强型化学气相淀积(PECVD)方法来形成，并且可在300到400℃温度及1到15mTorr压力下通过注入硅源气体及氮源气体及施加300到2000W的高频率功率来形成。
附图说明
图1为显示一NAND型闪存器件的一单元阵列区域的部分的等效电路图；
图2至5为用以说明依据本发明的一优选实施例来形成一半导体器件的钝化膜的方法的剖面图；以及
图6为显示一漏电流特性的图形，该漏电流特性依赖于是否在该NAND型闪存器件中形成一缓冲氧化膜。
主要组件符号说明
100 半导体衬底
110 金属线
120 第一钝化膜(缓冲氧化
    膜)
130 第二钝化膜(HDP膜)
140 第三钝化膜
B/L 位线
C1  单元晶体管
Cn  单元晶体管
CSL 公共源极线
DSL 单元组选择线
GST 接地选择晶体管
M/L 金属线
SSL 选择源极线
SST 单元组选择晶体管
WL1 字线
WLn 字线
具体实施方式
现在，将配合附图来描述依据本发明的优选实施例。因为要使熟习该项技术的一般人士能了解本发明而提供优选实施例，所以可以不同方式来修改这些优选实施例，并且本发明的范围并非局限于稍后所描述的优选实施例。同时，如果描述一膜位于另一膜或一半导体衬底″上″，该膜可直接接触该另一膜或该半导体衬底。或者，一第三膜可介于该膜与该另一膜或该半导体衬底之间。此外，在附图中，为了便于说明及明晰起见，放大了每一层的厚度及尺寸。相同组件符号用以标示相同或相似部分。
人们发现当形成这些金属线之后，测量漏电流时，漏电流特性是正常的，然而在形成一钝化膜之后，该漏电流会突然增加。这是因为淀积HDP膜时所产生的等离子体电荷对该漏电流特性具有坏的影响。作为第二钝化膜的该HDP膜是通过施加一高偏置功率来淀积的，以便掩埋该金属线。因此，实验结果表明漏电流特性劣化了。为了解决此问题，必须在淀积作为该第二钝化膜的HDP膜前使用一能防止等离子体所造成的损伤的缓冲氧化膜。
该缓冲氧化膜是在HDP膜淀积工序中在原处淀积的。亦即，在淀积该HDP膜的初始步骤中淀积该缓冲氧化膜之后，在一随后工序中实施用以掩埋金属线间的间隙的该HDP膜淀积工序。为此，在形成该缓冲氧化膜的步骤中，需要最小化要施加至该衬底的偏置功率。换句话说，必须通过最小化或不使用该偏置功率，在下列状态下通过化学反应形成一氧化膜：等离子体状态的离子不会对半导体衬底造成物理撞击。如果利用此原理，在淀积该缓冲氧化膜时就可最大限度地阻止对金属线造成物理损伤。同样，也可能防止选择源极线与公共源极线之间产生漏电流。
图1为显示一NAND型闪存器件的一单元阵列区域的部分的等效电路图。
参考图1，该NAND型闪存器件的单元阵列区域具有多个单元组，例如：第一至第四单元组S1、S2、S3及S4。一个单元组连接至16或32个单元。每一单元组包括一单元组选择晶体管SST、多个单元晶体管C1、...、Cn以及一接地选择晶体管GST。该单元组选择晶体管SST的栅极连接至一单元组选择线DSL。该接地选择晶体管GST的栅极连接至一选择源极线SSL。每一单元组的第一单元晶体管的控制栅极连接至第一字线WL1。每一单元组的第n单元晶体管Cn的控制栅极连接至一字线WLn。单元组选择晶体管SST漏极区域连接至一位线B/L。接地选择晶体管GST的源极区域连接至一公共源极线CSL。多条位线B/L朝横跨该多条字符WL1、...、WLn的方向来设置。公共源极线CSL朝平行于该选择源极线SSL的方向来设置。公共源极线CSL连接至一平行于该位线B/L的金属线M/L。该金属线M/L是一用以将该公共源极线CSL连接至周边区域(未示出)的金属线。
现将参考附图来描述依据本发明的一优选实施例的一形成半导体器件的钝化膜的方法。
图2至图5为用以说明依据本发明的一优选实施例来形成一半导体器件的一钝化膜的方法的剖面图。
参考图2，在一半导体衬底100上形成一金属线110。该金属线110可以是一单层金属线。虽然未示出于该半导体衬底100中，但是可将图1中所描述的一单元组选择晶体管、一单元晶体管、一接地选择晶体管、一选择源极线、一字线、一单元组选择线、一公共源极线、一位线等形成于该半导体衬底100中。多条金属线间的深度可以是例如5000到
Figure C20051000552600071
参考图3，在半导体衬底100上形成一作为第一钝化膜的缓冲氧化膜120，其中在该半导体衬底100上已形成有金属线110且该缓冲氧化膜120可减轻等离子体所造成的损伤。该缓冲氧化膜120可使用一具有低压应力或张应力的氧化膜来形成。当形成该缓冲氧化膜120时，优选使施加至该半导体衬底的偏置功率最小化。亦即，可通过最小化或不使用该偏置功率，在下列状态下通过化学反应形成该缓冲氧化膜120：等离子体状态的离子不会对半导体衬底(或金属线)造成物理撞击。当形成缓冲氧化膜120时，不施加偏置功率，或者施加只会使等离子体所造成的对该半导体衬底的物理撞击很少发生的程度的偏置功率(例如：低于1000W的偏置功率)。该缓冲氧化膜120可通过使用硅烷(SiH4)气体作为硅源气体及氧气(O2)作为氧源气体所形成的氧化硅膜(SiO2)构成。例如：该缓冲氧化膜120可在约250到400℃温度及约1到15mTorr压力下通过注入硅源气体及氧源气体及施加约1000到5000W的源功率及约0到1000W的偏置功率来形成。此时，将该硅源气体的流速设定成约10到100sccm，并将该氧源气体的流速设定成约15到200sccm。在形成该缓冲氧化膜120时，环境气体可以使用氩气(Ar)、氦气(He)、氮气(N2)等。该缓冲氧化膜120形成具有一可充分地防止在形成该HDP膜时等离子体电荷渗透至该金属线的厚度，例如：约50到
Figure C20051000552600081
参考图4，在该半导体衬底100上形成一作为第二钝化膜的HDP膜130，其具有一可至少完全地掩埋该金属线间的间隙的厚度，其中在该半导体衬底上已形成有该缓冲氧化膜。优选地，该HDP膜130在用以形成该缓冲氧化膜120的设备(反应室)中在原处连续地形成。该HDP膜130可通过化学气相淀积(CVD)方法来形成。该HDP膜130通过施加约1000到4000W的偏置功率形成。该HDP膜130可通过使用硅烷(SiH4)气体作为硅源气体及氧气(O2)作为氧源气体所形成的氧化硅膜(SiO2)构成。例如：该HDP膜130可在约250到400℃温度及约1到15mTorr压力下通过注入硅源气体及氧源气体及施加约1000到5000W的源功率及约1000到4000W的偏置功率来形成。此时，将该硅源气体的流速设定为约30到150sccm，并将该氧源气体的流速设定为约40到300sccm。在形成该HDP膜130时，环境气体可以使用氩气(Ar)、氦气(He)、氮气(N2)等。该HDP膜130形成具有至少可完全地掩埋该金属线间的间隙的厚度，例如：约3000到
Figure C20051000552600082
参考图5，在该半导体衬底100上形成一可防止水分等渗入的第三钝化膜140，其中在该半导体衬底100上已形成有该HDP膜130。该第三钝化膜140可使用氮化硅(Si3N4)膜或氮氧化硅(SiON)膜来形成。该第三钝化膜140可通过等离子体增强型化学气相淀积(PECVD)方法来形成。该第三钝化膜140可以通过使用硅烷(SiH4)或四乙基原硅酸盐(Tetra Ethyl Ortho Silicate，TEOS)气体作为硅源气体及一氧化二氮(N2O)、氨气(NH3)或其混合气体作为氮源气体所形成的氮化硅(Si3N4)形成。例如：该第三钝化膜140可在约300到400℃温度及约1到20mTorr压力下通过注入硅源气体及氮源气体及施加约300到2000W的源功率来形成。此时，将该硅源气体的流速设定为约5到30sccm，并将氮源气体的流速设定为10到100sccm。在形成该第三钝化膜140时，环境气体可以使用氩气(Ar)、氦气(He)、氮气(N2)等。该第三钝化膜140形成具有一可防止水分从外部渗入的厚度，例如：约2000到
Figure C20051000552600083
依据本发明的一实施例的半导体器件的钝化膜具有三层结构，其包括：在该半导体衬底100上所形成的缓冲氧化膜120，在该半导体衬底100上沿着该金属线110所要产生的台阶已形成有金属线110，其中该缓冲氧化膜120可减轻等离子体所造成的损伤；在该缓冲氧化膜120上所形成的HDP膜130，其具有一足以掩埋金属线间110的间隙的厚度；以及在该HDP膜130上所形成的氮化膜140，其用以防止水分从外部渗入。
当将5V的正电压施加至选择源极线SSL或公共源极线CSL时的漏电流量显示于表1及2中。表1及2表示根据一用以监控主单元的测试模式(testpattern)所测量到的漏电流。在这些表中，指定一晶片的相应点，在相应点上漏电流的测量值显示于表1及2中，以便使这些测量值对应于该晶片的相应点。
从表1可看出在一给定参考值(例如：5×10-12A)以上的漏电流不会产生于直到实施过金属线工序的晶片中(在未形成钝化膜情况下测量该漏电流)。
[表1]
  6.00E-14   6.00E-14   6.00E-14   8.00E-14
  1.00E-13   8.00E-14   1.00E-07   1.20E-13   1.00E-13   1.00E-13
  8.00E-14   1.40E-13   1.40E-13   1.20E-13   1.00E-13   1.40E-13   1.20E-13   1.20E-13
  1.40E-13   1.20E-13   1.00E-13   1.20E-13   6.00E-14   1.40E-13   1.20E-13   1.40E-13
  1.60E-13   1.80E-13   1.20E-13   1.20E-13   8.00E-14   1.00E-13   1.20E-13   1.00E-13
  4.00E-14   1.20E-13   1.00E-13   1.00E-13   1.20E-13   1.20E-13   1.40E-13   1.20E-13
  1.20E-13   1.40E-13   1.20E-13   1.00E-13   1.60E-13   1.40E-13   1.20E-13   1.40E-12
  1.40E-13   1.20E-13   1.40E-13   1.40E-13   1.40E-13   1.20E-13
  1.00E-13   1.20E-13   1.20E-13   8.00E-14
下面的表2显示在形成一HDP膜及一第三钝化膜之后而未形成一缓冲氧化膜的情况下的漏电流值。此时，该HDP膜在约350℃温度及约5mTorr压力下通过注入硅烷气体及氧气以及施加约4400W的源功率及约2750W的偏置功率形成。此时，将该硅烷气体的流速设定为约85sccm，并将该氧气的流速设定为约150sccm。当形成该HDP膜时，使用氩气作为环境气体。该HDP膜形成具有约
Figure C20051000552600091
的厚度。此外，该第三钝化膜在约400℃温度及约4Torr压力下通过注入硅烷气体及作为氮源气体的一氧化二氮(N2O)及氨气(NH3)以及施加约300W的高频率功率形成。此时，将该硅烷气体的流速设定为约250sccm，将该一氧化二氮气体(N2O)的流速设定为约3000sccm，并将该氨气(NH3)的流速设定为3500sccm。当形成该第三钝化膜时，使用氮气(N2)作为环境气体。该第三钝化膜形成具有约
Figure C20051000552600101
的厚度。
从表2可看出，在实施该钝化膜形成工序之后且未形成该缓冲氧化膜的情况下，会产生超过预定参考值(例如：5×10-12A)的大量的漏电流。
[表2]
  5.11E-09   1.59E-11   1.55E-10   2.44E-10
  1.80E-10   7.69E-10   2.68E-09   1.00E-07   3.37E-09   1.40E-13
  1.46E-11   8.46E-10   3.06E-09   1.00E-07   1.00E-07   4.42E-09   9.41E-10   8.00E-14
  4.46E-10   2.09E-09   1.65E-09   1.00E-07   1.00E-07   1.00E-07   4.57E-09   7.30E-12
  7.68E-10   1.00E-07   7.58E-09   3.00E-09   1.00E-07   1.00E-07   2.61E-09   1.00E-07
  1.56E-09   2.21E-07   3.12E-09   1.00E-07   1.00E-07   6.38E-09   8.73E-09   5.60E-13
  1.04E-09   1.00E-07   1.00E-07   3.19E-09   1.98E-09   1.75E-09   2.04E-10   9.80E-13
  1.84E-09   3.17E-09   4.98E-10   1.00E-07   1.54E-10   1.00E-13
  8.54E-11   9.76E-12   1.85E-09   1.00E-07
图6为显示一漏电流特性的图形，该漏电流特性依赖于是否在该NAND型闪存器件中形成一缓冲氧化膜。
在图6中，HDP膜及第三钝化膜的淀积条件与表2中的淀积条件相同。在图6中，该缓冲氧化膜在约350℃温度及约5mTorr压力下通过注入硅烷气体及氧气以及施加约4400W的源功率及约0W的偏置功率形成。此时，将该硅烷气体的流速设定为约53sccm，并将该氧气的流速设定为约105sccm。当形成该缓冲氧化膜时，使用氩气作环境气体，且该缓冲氧化膜形成具有约
Figure C20051000552600102
的厚度。
如果如现有技术那样没有形成该缓冲氧化膜，而只形成该HDP膜(图6中的(a))，则在选择源极线与公共源极线间会产生大量的漏电流。相反，如果先形成该缓冲氧化膜然后形成该HDP膜(图6中的(c))，则很少会产生漏电流。在图6中，(b)表示一直到进行完金属线工序的晶片的漏电流值(该漏电流是在没有形成该钝化膜情况下测量的)。从图6可看出该缓冲氧化膜足以起到一等离子体阻挡层的作用。
当然，纵然该缓冲氧化膜可在淀积该HDP膜之前在除该HDP膜淀积室以外的它处淀积室中形成，也可获得相同效果。然而，在此情况中，会有下列缺点：周转时间(turn around time，TAT)会变慢以及工序增加。
因此，优选地，该缓冲氧化膜及该HDP膜在相同淀积室中在原处形成。如果使用原处工序，相比于传统方法可在漏电流方面获得改善的结果，同时会有不需额外工序的优点，并且相比于在不同处形成该缓冲氧化膜及该HDP膜的情况，会有在周转时间方面上的优点。
如上所述，依据本发明，在形成HDP膜之前，形成一缓冲氧化膜。因此，有可能显著减少选择源极线与公共源极线间的漏电流。
虽然已参考优选实施例做出了上述说明，但是应当理解的是，本领域的一般技术人员在不脱离本发明的精神及范围及所附权利要求的前提下可以对本发明做出变更及修改。

Claims (8)

1.一种形成半导体器件的钝化膜的方法，其包括下列步骤：
在一半导体衬底上形成多条金属线；
在所述金属线上形成一作为第一钝化膜的缓冲氧化膜，其中该缓冲氧化膜不通过施加偏置功率形成且减轻等离子体所造成的损伤；
在所述缓冲氧化膜上形成一作为第二钝化膜的高密度等离子体膜，其中该高密度等离子体膜通过施加偏置功率形成，和该缓冲氧化膜和该高密度等离子体膜在同一反应室中在原处形成；以及
在所述第二钝化膜上形成包括氮化硅膜的第三钝化膜。
2.如权利要求1所述的方法，其中所述缓冲氧化膜由通过使用硅烷气体作为硅源气体及氧气作为氧源气体所形成的氧化硅膜构成。
3.如权利要求1所述的方法，其中该缓冲氧化膜在250到400℃温度及1到15mTorr压力下通过注入硅源气体及氧源气体形成。
4.如权利要求3所述的方法，其中所述硅源气体为硅烷气体且氧源气体为氧气，并且所述缓冲氧化膜通过在10到100sccm的流速下注入该硅源气体及在15到200sccm的流速下注入该氧源气体形成。
5.如权利要求1所述的方法，其中所述缓冲氧化膜形成50到
Figure C2005100055260002C1
的厚度，其中该厚度的程度可充分地防止在形成所述高密度等离子体膜时等离子体电荷渗透至所述金属线中。
6.如权利要求1所述的方法，其中所述高密度等离子体膜在250到400℃温度及1到15mTorr压力下通过注入硅烷气体及氧气及施加1000到5000W的源功率及1000到4000W的偏置功率形成。
7.如权利要求6所述的方法，其中所述高密度等离子体膜通过在30到150sccm的流速下注入硅烷气体及在40到300sccm的流速下注入氧气形成。
8.如权利要求1所述的方法，其中所述氮化硅膜通过等离子体增强型化学气相淀积方法形成，并且在300到400℃温度及1到15mTorr压力下通过注入硅源气体及氮源气体及施加300到2000W的高频率功率形成。
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US7411299B2 (en) 2008-08-12
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US20060014377A1 (en) 2006-01-19
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US20070132042A1 (en) 2007-06-14
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