CN100372231C - 双向双nmos开关 - Google Patents

双向双nmos开关 Download PDF

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CN100372231C
CN100372231C CNB038247623A CN03824762A CN100372231C CN 100372231 C CN100372231 C CN 100372231C CN B038247623 A CNB038247623 A CN B038247623A CN 03824762 A CN03824762 A CN 03824762A CN 100372231 C CN100372231 C CN 100372231C
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semiconductor switch
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CN1695300A (zh
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G·德克雷莫西
I·范鲁
J·迪肯
F·尼尤沃夫
Y·克里斯托福鲁
A·肯格
W·J·R·威廉森
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches

Abstract

一种半导体开关，包括两个以反串联设置耦合的NMOS晶体管、耦合到NMOS晶体管的栅极的栅极控制电路。NMOS晶体管的漏极是互连的，栅极控制电路耦合到漏极互连。所需的芯片面积是已有的开关的一半。将栅极泵送至更高的电压可以引起NMOS晶体管的尺寸的进一步减小。另外有利于在NMOS晶体管的源极之间允许大范围的输入和输出电压，源极分别充当开关的输入和输出，从而可以使开关应用于广泛的技术领域。

Description

双向双NMOS开关
技术领域
本发明涉及一种半导体开关，包括两个以反串联设置耦合的MOS晶体管、和耦合到MOS晶体管的栅极的栅极控制电路。
本发明还涉及一种系统，该系统包括两个通过半导体开关互连的电路。
背景技术
JP-11195972中公开了这种半导体开关。该已知的半导体开关包括两个实现为P沟道MOS场效应晶体管(FET)的金属氧化物半导体(MOS)晶体管，这两个晶体管以反串联设置耦合，由此将这两个简称为PMOS晶体管的源极互连。该半导体开关还包括耦合到PMOS晶体管的栅极的栅极控制电路，该栅极控制电路是还被耦合到源极的互连的栅-源控制电路。栅-源控制电路包括放电电路，用于通过使反转的控制信号控制其各自的阻抗，来释放PMOS晶体管的栅极和源极之间的电荷。这减小了用于半导体开关的漏极和源极之间的阻抗改变的时间。放电电路包括电阻器，当需要相对大的芯片面积时，该电阻器需要消耗相当数量的功耗。
该已知的半导体开关的缺点是其需要相对大的芯片和芯片管芯面积。
发明内容
本发明的目的是提供一种具有广泛的应用性、表现出提高的导电率，并需要减小的芯片和管芯面积的双向集成开关。
根据本发明的半导体开关的特征在于，MOS晶体管体现为N沟道MOS晶体管，其两个漏极互连，栅极控制电路耦合到漏极互连。
根据本发明的半导体开关的优点在于，发明人发现提出的半导体开关形态使芯片面积和芯片管芯尺寸减小了两倍。虽然减小了芯片面积，但是发现，由充当电荷泵的栅极控制电路来控制的开关的导电性能非常好。实际上，这种开关形态使得NMOS晶体管的各个栅极处的电荷泵输出电压越高，得到的开关整体上的导电性越好。因此，将这些栅极泵送至更高的电压引起NMOS晶体管的尺寸进一步减小，且不存在损坏的风险。另外，有利地是，可以允许NMOS晶体管的源极之间具有大范围的输入和输出电压，由此源极分别充当开关的输入和输出，因此允许开关被应用于广泛的技术领域。而且在根据本发明的开关中，不需要要求大芯片面积的大尺寸功耗的电阻器。
根据本发明的半导体开关的一个实施例，其特征在于半导体开关包括耦合于至少其中一个晶体管的栅极和源极之间的电压限制电路。
因为耦合于至少其中一个晶体管的栅极和源极之间的电压限制电路将各个栅极充电至与源极几乎相同的电压，因此在其中一个NMOS晶体管的源极上几十伏量级的非常高的电压，其对晶体管的完整性具有风险，则将不再构成威胁。
根据本发明的半导体开关的另一个实施例，其特征在于电压限制电路包括半导体装置，优选晶体管，例如NMOS晶体管或二极管。能够在有限的IC芯片面积上以非常有效的成本实现这些半导体装置。
根据本发明的半导体开关的另一个实施例，其特征在于NMOS晶体管是双扩散NMOS晶体管。
有利地是，这些所谓的DMOS晶体管能够耐受源极和栅极之间的中等电压，甚至是漏极和栅极之间的高电压也不被击穿。这省去了过电压保护措施的使用。
根据本发明的半导体开关的另一个实施例，其特征在于设置栅极控制电路用于执行两阶段的栅极泵送电压倍增操作。
在该两阶段的栅极泵送电压倍增操作的第一阶段期间，积累电荷，其后在第二阶段中，将该电荷加上另一电荷从而将增加的充电电压施加到NMOS晶体管的栅极。依次地，该增加的电压导致NMOS晶体管的期望的高导电性。
在根据本发明的半导体开关的另一个实施例中，栅极控制电路优选包括开关电容器装置。这些装置易于以有限的芯片面积实现，并能够控制其电荷传输以影响开关的启动时间。
根据本发明的半导体开关的另一个实施例，其特征在于该两阶段栅极泵送电压倍增操作具有大约为15-200KHz、优选大约为50KHz的可调电荷泵频率。
通过调节电荷泵频率，能够影响将栅极充电至工作电压的启动时间。
附图说明
现在将参照附图、结合其它优点进一步说明根据本发明的半导体开关和设置有该开关的系统，附图中相同的数字指的是相同的部件。在图中：
图1示出根据本发明的半导体开关的可能实施例的功能图；
图2示出图1的半导体开关的具体工作图；
图3示出具有根据本发明的半导体开关的系统略图。
具体实施方式
图1示出半导体开关1的功能图，半导体开关1包括以反串联设置耦合的两个N沟道MOS晶体管M1和M2。在这种反串联设置中，两个寄生本征体二极管D1和D2极性反转地串联连接。NMOS晶体管M1和M2中的每一个分别具有栅极G1、G2，源极S1、S2和漏极DR1、DR2。S1(PIN1)是开关1的输入，而S2(PIN2)是开关1的输出。漏极DR1和DR2互连。开关1还包括栅极控制电路2，其耦合到各个晶体管M1和M2的栅极G1和G2，还耦合到漏极互连，表示为MID。
充当源极S1和S2之间的双向开关的开关1的工作如下。栅极控制电路2(下文中也称为电荷泵2)感测MID电压，并例如通过电压倍增而导出栅极电压，其分别高于S1和S2上的输入电压和输出电压。这通过寄生二极管D1和D2的存在及其连接实现。这保证了晶体管M1和M2的开态。在关态时，通过电荷泵2向栅极G1、G2和/或漏极连接MID施加低电压，从而导致开关1的电流阻断。
体现为NMOS晶体管M1和M2的开关1需要的总面积是已有技术中需要的面积值的一半。需要不到其一半的面积用于包括电荷泵2的附加电路。NMOS晶体管可以是双扩散NMOS晶体管，也称为DMOS晶体管。这种DMOS晶体管能承受源极和栅极之间的中等电压，以及漏极和栅极之间的高电压，从而不需要对晶体管M1或M2应用保护电路。
在另一实施例中，半导体开关1包括图1中示为D3的电压限制电路，这里其耦合于晶体管M1的栅极G1和源极S1之间。因为G1上的电压一直为低于输入S1上的电压的受限电压值，这样特别在晶体管M1的关态时施加在S1上的高正电压不会破坏M1。实际上电压限制电路包括半导体装置，诸如晶体管，例如为NMOS晶体管或二极管。在后一种情况中，源极和栅极之间不同的电压将是一个二极管电压降，大约0.6-0.8伏的量级。
图2示出半导体开关1的具体工作图。电压限制电路由NMOS M3形成，其可以例如利用齐纳二极管(未示出)保护自身免受高电压影响。电荷泵是以虚线示出的部件2。它包括两个半导体转换(transition)DP1和DP2，其阳极互连，且其阴极分别连接到耦合至地GND的可控开关KS1和KS2。开关KS1和KS2还分别经电流限制器R1和R2耦合到M1和M2的各个栅极G1和G2。串联设置的可控开关K2和K1B连接于MID和GND之间，且它们的连接点耦合到电容装置C1的一侧，其标记为CPO的另一侧耦合到二极管DP1和DP2的公共阳极。在CPO和GND之间具有可控开关K1A和电压源V1的串联设置。
图2的半导体开关1的工作如下。关态时，KS1和KS2关闭，这意味着G1和G2经均可为电阻器的R1和R2被拉向地。如果一方面输入S1载有非常高的电压，那么M3中的寄生二极管将使M1的栅极G1保持在V源1-VM3，由此防止在G1和S1之间过高的电压，如上所述。在这种情况中，一些电流将流经M3的二极管和R1，但是将R1选择得足够高将能够控制这个低电流。因此将没有电流流经M1。如果另一方面输入S1载有负电压，由于栅源电压大于0伏，M3将导通。那么G1经M3连接到S1，M1的栅源电压为0伏，再次保证了没有电流流经M1。最后对于M2的源极S2上给定的电压，S1上任何正或负电压将导致缺少从S2到S1的电流汲取或来源。开关1关于栅极G1、G1和漏极DR1、DR2的形态提供了一种需要较少的ESD保护措施的更有效的静电放电(ESD)路径。
在开态时，KS1和KS2打开。现在M1和M2的栅极G1和G2在两个阶段被充电。当K1A和K1B关闭时，电容装置C1被充电至电压V1。V1可以是从例如S1或S2上的电压导出的内部电压。现在K1A和K1B打开，K2关闭。C1的电荷和极性维持不变，从而用MID取代GND使CPO电压上拉至VMID+V1。这形成过剩电压，其分别经二极管DP1和DP2将电荷注入到M1和M2的栅极G1和G2。重复几次该两阶段的电荷泵送操作，直至G1和G2实际被充电至最终电压VMID+V1-VDP1。因为VMID具有最高值减去半导体电压降，这确保了G1和G2被充电至高于S1或S2的电压。调整V1在G1和G2上获得最高电压，并获得最小尺寸的双向半导体开关1的最好导电性。实际上，非常有效的电荷泵电压倍增操作具有大约15至几百KHz的可调电荷泵频率。在一个实施例中，电荷泵频率大约为50KHz。在50KHz下，需要50个周期对G1和G2充电。然后在大约1msec内完全激活开关1。可以通过调节电荷泵频率或在每一时钟周期由C1传输的电荷，来调节启动时间。
图3示出设置有半导体开关的系统3的略图。系统3包括第一电路4，这里例如由电源如墙上插头式适配器形成，和使用该电源的第二电路5，例如其为诸如便携式电话的电话的电池。电路4和5均由半导体开关1隔离，且电流能够被阻塞或在一个或另一个方向上流经开关1。通过上述方式适当地控制开关1处于关态或开态。当然，其它的电路4、5可以用作这里的例子。通常一个电路提供电源，而另一电路使用该电源，或反之亦然。

Claims (6)

1.一种半导体开关，包括：
两个以反串联设置耦合的MOS晶体管，耦合到MOS晶体管的栅极的栅极控制电路，该MOS晶体管体现为N沟道MOS晶体管，MOS晶体管的漏极互连，该栅极控制电路耦合到该互连的漏极；
其中栅极控制电路包括开关电容装置，该开关电容装置的一端通过开关连接到互连的漏极，另一端通过至少一个二极管连接到两个MOS晶体管的栅极，以执行两阶段的栅极泵送电压倍增操作。
2.根据权利要求1的半导体开关，该半导体开关还包括耦合于至少其中一个MOS晶体管的栅极和源极之间的电压限制电路。
3.根据权利要求2的半导体开关，其中电压限制电路包括半导体装置。
4.根据权利要求3的半导体开关，其中半导体装置是NMOS晶体管。
5.根据权利要求1的半导体开关，其中两阶段的栅极泵送电压倍增操作具有15-200KHz的可调电荷泵频率。
6.一种包括两个电路的系统，该系统包括根据权利要求1或2的半导体开关，该半导体开关互连于两个电路之间。
CNB038247623A 2002-10-29 2003-09-22 双向双nmos开关 Expired - Fee Related CN100372231C (zh)

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US7199640B2 (en) 2007-04-03
KR20050061574A (ko) 2005-06-22
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