CN100370614C - 半导体集成电路装置及半导体集成电路装置的控制方法 - Google Patents
半导体集成电路装置及半导体集成电路装置的控制方法 Download PDFInfo
- Publication number
- CN100370614C CN100370614C CNB038243695A CN03824369A CN100370614C CN 100370614 C CN100370614 C CN 100370614C CN B038243695 A CNB038243695 A CN B038243695A CN 03824369 A CN03824369 A CN 03824369A CN 100370614 C CN100370614 C CN 100370614C
- Authority
- CN
- China
- Prior art keywords
- output
- signal
- input
- integrated circuit
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/73—Circuitry for compensating brightness variation in the scene by influencing the exposure time
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (21)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/004133 WO2004088749A1 (ja) | 2003-03-31 | 2003-03-31 | 半導体集積回路装置、および半導体集積回路装置の制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1689159A CN1689159A (zh) | 2005-10-26 |
CN100370614C true CN100370614C (zh) | 2008-02-20 |
Family
ID=33105363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038243695A Expired - Fee Related CN100370614C (zh) | 2003-03-31 | 2003-03-31 | 半导体集成电路装置及半导体集成电路装置的控制方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7135882B2 (zh) |
JP (1) | JP4021898B2 (zh) |
CN (1) | CN100370614C (zh) |
WO (1) | WO2004088749A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101124251B1 (ko) * | 2010-07-07 | 2012-03-27 | 주식회사 하이닉스반도체 | 적층된 칩들에 아이디를 부여하는 시스템, 반도체 장치 및 그 방법 |
KR20160034698A (ko) * | 2014-09-22 | 2016-03-30 | 에스케이하이닉스 주식회사 | 반도체장치 및 이를 포함하는 반도체시스템 |
CN104614662B (zh) * | 2015-01-21 | 2017-05-24 | 矽力杰半导体技术(杭州)有限公司 | 测试模式设定电路及设定方法 |
CN115588460B (zh) * | 2022-12-06 | 2023-03-14 | 仲联半导体(上海)有限公司 | 一种自动识别测试模式和产品模式的方法及芯片 |
CN117368701B (zh) * | 2023-12-07 | 2024-03-15 | 芯洲科技(北京)股份有限公司 | 焊盘检测电路 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0961496A (ja) * | 1995-08-29 | 1997-03-07 | Hitachi Ltd | 半導体集積回路装置および論理テスト方法 |
JPH10161898A (ja) * | 1996-11-29 | 1998-06-19 | Nec Eng Ltd | 半導体集積回路 |
JPH11101858A (ja) * | 1997-09-29 | 1999-04-13 | Toshiba Microelectronics Corp | 半導体集積回路 |
US5936423A (en) * | 1995-12-14 | 1999-08-10 | Kawasaki Steel Corporation | Semiconductor IC with an output circuit power supply used as a signal input/output terminal |
JP2000193724A (ja) * | 1998-12-24 | 2000-07-14 | Nec Corp | 入出力回路 |
US6330297B1 (en) * | 1999-04-30 | 2001-12-11 | Fujitsu Limited | Semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09318704A (ja) * | 1996-05-30 | 1997-12-12 | Ando Electric Co Ltd | Ic試験装置 |
EP1014547A3 (en) * | 1998-12-21 | 2000-11-15 | Fairchild Semiconductor Corporation | Low-current charge pump system |
JP4137474B2 (ja) * | 2002-03-18 | 2008-08-20 | 富士通株式会社 | 自己テスト回路及び半導体記憶装置 |
-
2003
- 2003-03-31 WO PCT/JP2003/004133 patent/WO2004088749A1/ja active Application Filing
- 2003-03-31 JP JP2004570177A patent/JP4021898B2/ja not_active Expired - Fee Related
- 2003-03-31 CN CNB038243695A patent/CN100370614C/zh not_active Expired - Fee Related
-
2005
- 2005-03-28 US US11/090,661 patent/US7135882B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0961496A (ja) * | 1995-08-29 | 1997-03-07 | Hitachi Ltd | 半導体集積回路装置および論理テスト方法 |
US5936423A (en) * | 1995-12-14 | 1999-08-10 | Kawasaki Steel Corporation | Semiconductor IC with an output circuit power supply used as a signal input/output terminal |
JPH10161898A (ja) * | 1996-11-29 | 1998-06-19 | Nec Eng Ltd | 半導体集積回路 |
JPH11101858A (ja) * | 1997-09-29 | 1999-04-13 | Toshiba Microelectronics Corp | 半導体集積回路 |
JP2000193724A (ja) * | 1998-12-24 | 2000-07-14 | Nec Corp | 入出力回路 |
US6330297B1 (en) * | 1999-04-30 | 2001-12-11 | Fujitsu Limited | Semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation |
Also Published As
Publication number | Publication date |
---|---|
WO2004088749A1 (ja) | 2004-10-14 |
US7135882B2 (en) | 2006-11-14 |
JPWO2004088749A1 (ja) | 2006-07-06 |
CN1689159A (zh) | 2005-10-26 |
JP4021898B2 (ja) | 2007-12-12 |
US20050169060A1 (en) | 2005-08-04 |
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Legal Events
Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Patentee after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Patentee before: Fujitsu Ltd. |
|
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTORS CO., LTD Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Fujitsu Microelectronics Ltd. |
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ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150526 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150526 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080220 Termination date: 20170331 |