CN100369530C - 元件装载用基板及其制造方法与半导体元件安装方法 - Google Patents
元件装载用基板及其制造方法与半导体元件安装方法 Download PDFInfo
- Publication number
- CN100369530C CN100369530C CNB200510006752XA CN200510006752A CN100369530C CN 100369530 C CN100369530 C CN 100369530C CN B200510006752X A CNB200510006752X A CN B200510006752XA CN 200510006752 A CN200510006752 A CN 200510006752A CN 100369530 C CN100369530 C CN 100369530C
- Authority
- CN
- China
- Prior art keywords
- layer
- solder layer
- mounting substrate
- element mounting
- circuit components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- Die Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
本发明的元件装载用基板,是具有用于与半导体电路元件相连接的焊料层的元件装载用基板,其特征为,在与所述半导体电路元件相连接一侧的该焊料层的表面,设有包含Au-Sn合金的δ相的结晶粒子层。另外,本发明的元件装载用基板的制造方法,是具有用于与半导体电路元件相连接的焊料层的元件装载用基板的制造方法,其特征为,在与所述半导体电路元件相连接一侧的该焊料层的表面,形成有包含Au-Sn合金的δ相的结晶粒子层。根据本发明的元件装载用基板及其制造方法与半导体元件安装方法,可在将半导体电路元件安装于基板上时,使用CCD相机等能够容易地根据焊料层的表面状态而对熔融行为进行图像识别,以减少安装时的连接不良。
Description
技术领域
本发明涉及一种元件装载用基板及其制造方法与半导体元件安装方法。
背景技术
首先对专利文献1中关于向基板上连接半导体电路元件的焊接技术加以介绍。在向表面上设有金属导电层的基板上连接半导体电路元件时,由CCD相机等对焊料层进行摄像,同时将基板加热到焊料的熔点温度以上,使焊料层熔化。用CCD相机等来摄像,根据读取表面状态伴随焊料层熔融时的变化而决定开始装载的时间。
[专利文献1]特开2001-57468号公报
然而,共晶点成分的Au-Sn焊料,在熔融前后其焊料层表面平滑,根据CCD相机等摄像所得到的图像数据而对表面状态的变化很难进行识别,存在误识别安装位置与时间的情况。从而引起接合精度不良与接合情况不佳等问题。
发明内容
本发明的目的在于提供一种在向基板上安装半导体电路元件时,由CCD相机等能够容易地根据焊料层的表面状态对熔融行为进行图像识别,能够减少安装时连接不良的元件装载用基板及其制造方法与半导体元件安装方法。
在装载前的基板与半导体电路元件相连接一侧的焊料层的基板表面,设有包含Au-Sn合金的δ相的结晶粒子层。
(发明效果)
根据本发明,在向基板上安装半导体电路元件时,由CCD相机等能够容易地根据焊料层的表面状态对熔融行为进行图像识别,是能够减少安装时连接不良的元件装载用基板及其制造方法与半导体元件安装方法。
附图说明
图1是表示本发明的实施例中半导体电路元件装载用基板的截面图。
图2是表示Au-Sn二元系的平衡状态图。
图3表示的是本发明的实施例中半导体电路元件装载用基板的制造工序。
图中:2-合层,3-金属层,4-Au层,5-Pt层,6、8-固相富有层,7-液相富有层,2-基板,21-金属导电层,31-焊料层。
具体实施方式
作为在表面上设置有金属导电层的基板上连接半导体电路元件的方法,有使用共晶点成分的Au-Sn合金(Au-Sn共晶焊料)的焊料焊接技术。下面,对该焊料焊接的顺序加以说明。
首先,用蒸镀及溅射等成膜方法,预先在基板的欲装载半导体电路元件的面上形成金属导电层。其后,在金属导电层上,由照相平版印刷技术形成图案制作的光致抗蚀剂层。在其上由蒸镀及溅射等成膜方法形成焊料层,经过剥离工序,进行焊料层的图案制作。最后使基板上的焊料层与半导体电路元件的安装面相连接。此时,一般是由机械自动地装载元件,但有在焊料加热及熔化前装载元件时和在焊料加热及熔化后装载元件的情况。在后者的情况下,必须确定由机械自身装载元件的位置和开始装载的时间。因此,由与安装用机械连动的CCD相机等对基板上的焊料层进行录像,同时,将基板加热到焊料熔点温度以上,使焊料层熔化。此时,由CCD相机等的录像,根据焊料层的位置读取装载位置,同时读取伴随焊料层熔融时表面状态的变化,由此来决定开始装载的时间。
但是,共晶点成分的Au-Sn焊料,在熔融前后,其焊料层表面平滑。即使是由CCD相机等的录像将该表面状态作成图像数据,但由于表面平滑,因此对表面状态的变化识别也变得困难。即,有对装载位置与时间产生误识别的情况。一旦发生了这样不希望的情况,机械会将半导体电路元件偏离焊料层而装载,尽管焊料层已熔化,但实际上尚未开始装载等发生安装时所不希望发生的情况。进而,还有在焊料层熔化一段时间后才开始安装元件的问题。另外,伴随着焊料熔化后时间的延长,焊料层中金属导电层的Au不断扩散,焊料的成分成为比共晶成分富有Au的成分。成为这样的富有Au成分时,由于进入了析出熔点高的ζ相Au-Sn合金的成分区域,所以液相线的温度会伴随着从共晶点的偏离而急剧上升。因此,在通常的连接温度(330~350℃)下,是ζ相(Au5Sn)与液相的共存区域,ζ相的析出会使焊料的一部分发生凝固现象。由此,在焊料层熔化后迟缓安装半导体电路元件时,由于部分焊料发生了凝固,所以元件表面的电极层与焊料层之间不能很好地润湿,存在有元件与基板之间不能牢固接合等问题。
在本发明的实施例中,是表面上设置了用于连接半导体电路元件的焊料层的基板,在向基板上安装半导体电路元件时,能够由CCD相机等从焊料层的表面状态容易地对熔融行为进行图像识别,为了减少安装时的连接不良问题,对元件装载用基板作了很大努力。
具体地说,在基板与半导体电路元件相连接的焊料层的最表层,形成包含Au-Sn合金的δ相的结晶粒子层。例如,在表面具有金属导电层的基板上形成焊料层。而且,该焊料层由包含Au-Sn合金的δ相的结晶粒子的固相富有层与Au-Sn合金的共晶点的作为共晶成分的液相富有层所构成。各个层都是由纵向的三层所构成,从接近基板的一侧依次是固相富有层、液相富有层、固相富有层。此时,在特定的温度范围内,将各层都设定为平衡状态。进而,在金属导电层与焊料层之间,设置有作为防止Au扩散的防护层的、Pt或Ni等金属层。
(实施例1)
对本发明的实施例,使用图1、图2、图3作以下的说明。图1是表示本发明的实施例中半导体电路元件装载用基板的截面图,图2是表示Au-Sn二元系的平衡状态图,图3是表示本发明的实施例中半导体电路元件装载用基板的制造工序。
如图1所示,元件装载用基板,在基板20上具有金属导电层21,在该金属导电层21上设置有焊料层31的基板。
金属导电层21,由在基板20的表面与基板的接合性高的金属材料Ti层或Cr层等的接合层2、在其上配置的Pt、Ni、Cu等金属层3、进而在其上为了防止氧化而配置的Au层4所构成。即,在基板20一侧,顺次形成接合层2,金属层3,以及作为防止氧化层的Au层4。
焊料层31,具有包含Au-Sn合金的δ相的结晶粒子的固相富有层6、固相富有层8以及Au-Sn合金的共晶点的共晶成分的液相富有层7。即,由纵向3层所构成,从接近金属导电层21的方向依次是固相富有层6、液相富有层7及固相富有层8。
如图2所示,在Au-Sn合金中,存在有δ相与液相的共存区域。由此可知,在278℃以上419.3℃以下的任意温度的δ相的Au-Sn合金(固相),与液相线上成分的Au-Sn合金(液相)相平衡。即,在278℃以上419.3℃以下范围内的任意温度,即使是液相线上成分的Au-Sn合金(液相)与δ相的Au-Sn合金(固相)相接触,固相不会溶解于液相,液相也不会凝固,固相与液相共存。由此,在将半导体电路元件向基板20上安装时,将其加热到278℃以上419.3℃以下的任意所希望的温度,固相富有层中的δ相结晶粒子不会溶解,且液相富有层中的液相部分也不会凝固,呈共存状态。
在本实施例中,固相富有层6、固相富有层8的具体组成为δ相的成分区域,是以Au50at.%-Sn50at.%为中心的宽度很窄的区域的成分范围(参照图2)。
这样,在与半导体元件相连接一侧的、作为焊料层的表面的固相富有层8中,通过设定包含Au-Sn合金的δ相结晶粒子,在安装时加热使焊料层熔化时,在最表面的固相富有层8中,析出δ相结晶粒子(固相),该δ相结晶粒子(固相)在表面上产生凹凸,使焊料层的表面发生变化。这样表面状态发生变化的固相富有层8,可以作为表示焊料开始熔化的标志,使得由CCD相机等的录像的图像识别变得更为容易。
而且,在下层的固相富有层6中,δ相结晶粒子(固相)会阻碍液相富有层7中的熔体到达金属导电层21,并且,还具有作为防止金属导电层21中的Au层4的扩散的防护层的功能。假定焊料层中Au发生了扩散,由于焊料成分富有Au,所以各焊料层之间不能保持平衡状态。
由于焊料层是由包含Au-Sn合金的δ相的结晶粒子层的固相富有层6与固相富有层8从上下夹持Au-Sn合金的共晶点的共晶成分的液相富有层7的结构,所以能够取得上述效果。
而且,固相富有层6与固相富有层8的成分,还可以是与上述所示δ相的成分区域有若干偏差的成分。具体地,可以是由Sn 45at.%以上、55at.%以下,其余为Au的Au-Sn合金、形成固相富有层6与固相富有层8。在这样的成分的情况下,若在安装时加热,例如则在固相富有层6与固相富有层8中,成为δ相(固相)结晶粒子与液相共存的状态。但是,如果是上述Sn 45at.%以上、55at.%以下的成分范围,则由于所生成的液相的量很少,所以δ相结晶粒子在最表面层能够作为表示熔融开始的标志,在下层具有作为防护层的功能。
另外,在本实施例中,液相焊料层的液相富有层7是由共晶点成分的Au-Sn合金所构成,具体的成分为Au71at.%-Sn29at.%(参照图2)。焊料层的最表面的固相富有层8以外的焊料层部分,设置有Au与Sn的成分不同的液相富有层7,上下两层重叠。该液相富有层7,不仅能够保持与固相富有层8的平衡状态,而且对半导体电路元件的电极层的润湿性好,还具有强化基板与元件之间接合的作用。
而且,液相富有层7并不限于该共晶成分,也可以是其它的组成。即,如图2所示,在278℃以上419.3℃以下的液相线上的成分及温度的Au-Sn合金与固相富有层的δ相相平衡,所以可以由Sn29at.%以上、低于50at.%的Au-Sn合金形成焊料层。在这种情况下,将连接时的连接温度设定为该焊料层成分的液相线温度。由此,在连接时能够得到上述平衡状态,在固相富有层的最表面,熔化时焊料的表面产生凹凸,可以作为熔融状态的标志,能够起到在下部层作为防止液相富有层中的熔体到达金属导电层以及金属导电层中Au的扩散的防护层的作用。
但是,即使是Sn29at.%以上、低于50at.%,由于随Sn的比例增大而液相线温度升高,随之要提高连接温度,所以为了降低连接温度,希望采用Sn45at.%以下。
在本实施例中,在焊料层31与金属导电层21之间设置有作为防护层的Pt层5。该Pt层5是为了防止Au层4中的Au向焊料层31中扩散而设置,具有稳定焊料层31中Au-Sn成分的功能。对于焊料层31保持如上所述的固相富有层6、固相富有层8、液相富有层7等三层,在各自的界面保持平衡状态,Pt层5是重要的防护层,起防止焊料层以外的Au层扩散的作用。
另外,如上所述,虽然焊料层下部的固相富有层6也同样起到防护层的作用,但设置Pt层则更为有效。作为上述防护层,还包含能够得到同样防止Au扩散效果的Ni等金属层。
另外,作为结构,虽然也包含金属层不是防护层本身的情况,但从保持焊料层31的成分、稳定保持焊料层中各层的平衡状态的观点出发,希望配置防护层。
接着,基于图3对上述图1的半导体元件装载用基板的制造方法与半导体电路元件安装方法加以说明。根据图3所示的制造及安装工序(a)~(d),制造半导体元件装载用基板。
在基板工序(a)中,首先准备基板20。
在金属化层工序(b)中,由蒸镀法,按照接合层2、金属层3、Au层4的顺序在基板20中与半导体电路元件相连接的面上形成金属导电层21。
在光致抗蚀剂层工序(c-1)中,在形成了金属导电层21的面上的整个面上涂敷光致抗蚀剂层9。
在照相平版印刷术工序(c-2)中,由照相平版印刷技术对涂敷的光致抗蚀剂层9形成图案。
在焊料层形成工序(c-3)中,在光致抗蚀剂层9的图案及金属导电层21上,由蒸镀法按照顺序整个面上形成Pt层5与焊料层31。此时,焊料层31是形成从金属导电层21一侧按照固相富有层6、液相富有层7、固相富有层8的顺序所构成的结构。此时,控制蒸镀时Au与Sn的来源量,使固相富有层6、固相富有层8成为如上所述的Au-Sn合金中δ相区域的成分(Au50at.%-Sn50at.%)。另外,对于液相富有层7,也控制来源量,将其成分控制为共晶成分(Au71at.%-Sn29at.%)。
在剥离工序(c-4)中,实施剥离,形成作为防护层的Pt层5、焊料层31的图案。
在连接工序(d)中,为了使半导体电路元件与基板相连接,预先将基板加热到连接温度。此时,为了对焊料层的熔化进行图像识别,由与安装用机械相连动的CCD相机等对焊料层进行录像。连接温度是使焊料层31能够熔化的温度。在本实施形式中,由于焊料层31的液相线温度是共晶点278℃,所以设置连接温度为278℃。此时液相富有层7熔化,但278℃时的δ相的Au-Sn合金的固相富有层6、固相富有层8仍为固相,二者平衡。而且,在最表层的固相富有层8中,δ相的结晶粒子(固相)在表面上形成凹凸,使焊料层的表面状态发生变化。此时的变化由CCD相机读取,安装机械开始将半导体电路元件40安装于基板上。即,加热包含Au-Sn合金的δ相结晶粒子的层,使其熔化,在由图像识别确认该熔融状态的同时进行焊接,由形成δ相的结晶粒子(固相)的表面的凹凸,能够容易地确认熔融状态,适宜地控制半导体元件安装时的位置与时间。所以,能够抑制连接不良等安装时所不希望发生的情况。
这里,在半导体电路元件40的连接面上,预先形成电极层41,该电极层41与金属导电层21相同,是由接合层2、金属层3、Au层4等三层所构成。在装载时,最表层的固相富有层8中的熔体部对金属导电层21有良好的浸润性。而且,下部层的固相富有层6中δ相的结晶粒子(固体)起到防护层的作用,能够保持固相富有层6、固相富有层8与液相富有层7的平衡状态,同时能够防止金属导电层中的Au向液相富有层7的扩散,由此抑制成分的Au富有化,防止引起连接不良的ζ相(Au5Sn)的析出。而且,液相富有层7的成分不发生变化,能够维持稳定的熔融状态。接着,冷却基板。由此,从液相富有层7中的熔体析出δ相与ζ相的共晶,液相富有层7成为共晶组织的固相,与上层与下层的固相富有层6、固相富有层8相接合。此时,虽然液相富有层7与固相富有层6、固相富有层8的成分不同,但由于都是Au-Sn合金,所以液相富有层7与固相富有层6、固相富有层8的接合性好,能够牢固接合。进而,对金属导电层21的Au层4润湿性好的最表面的固相富有层8中的熔体也同样析出δ相与ζ相的共晶,成为共晶组织的固相,与金属导电层21相接合。
在本实施例中,由以上的制造工序及安装工序,能够将半导体电路元件安装于基板。而且,在对表面上设置有焊料层的元件装载用基板上安装半导体电路元件时,能够根据焊料层的表面状态容易地对熔融行为进行图像识别,从而提供设置有可降低安装时连接不良的结构的基板。
(生产上的可利用性)
在将半导体电路元件安装于基板时,能够根据焊料层的表面状态容易地对熔融行为进行图像识别,从而提供设置有可降低安装时连接不良的结构的元件装载用基板及制造方法。
Claims (9)
1.一种元件装载用基板,是具有用于与半导体电路元件相连接的焊料层的装载前的元件装载用基板,其特征在于:
在装载前的与所述半导体电路元件相连接一侧的该焊料层的表面,设有包含Au-Sn合金的δ相的结晶粒子层。
2.根据权利要求1所述的元件装载用基板,其特征在于:该焊料层的最表面以外的焊料层部分,是将Au与Sn成分不同的层、上下两层重叠而成的结构。
3.根据权利要求1所述的元件装载用基板,其特征在于:该焊料层,是由上下两层包含Au-Sn合金的δ相的结晶粒子层隔着Au-Sn合金的共晶点的共晶成分的层而纵向重叠形成的3层结构。
4.根据权利要求1所述的元件装载用基板,其特征在于:最表层的焊料层的平均成分,是由大致为Sn 45at.%以上、Sn55at.%以下、其余为Au的Au-Sn合金所构成。
5.根据权利要求1所述的元件装载用基板,其特征在于:与基板表面上的金属导电层相接的下部层区域的焊料层的平均成分,大体由Sn45at.%以上、Sn55at.%以下、其余为Au的Au-Sn合金所构成。
6.根据权利要求1所述的元件装载用基板,其特征在于:存在于最表层与下部层区域之间的中间层的焊料层平均成分,是由Sn29at.%以上、Sn45at.%以下、其余为Au的Au-Sn合金所构成。
7.根据权利要求1所述的元件装载用基板,其特征在于:在金属导电层与焊料层之间,设置有作为防止Au扩散的防护层的金属层。
8.一种元件装载用基板的制造方法,是具有用于与半导体电路元件相连接的焊料层的装载前的元件装载用基板的制造方法,其特征在于:
在装载前的与所述半导体电路元件相连接一侧的该焊料层的表面,形成有包含Au-Sn合金的δ相的结晶粒子层。
9.一种半导体电路元件安装方法,是在具有焊料层的元件装载用基板上焊接半导体电路元件的半导体电路元件的安装方法,其特征在于:
在装载前的与所述半导体电路元件相连接一侧的该焊料层的表面,形成包含Au-Sn合金的δ相的结晶粒子层,对所述包含Au-Sn合金的δ相的结晶粒子层进行加热熔融,并由图像识别系统确认该熔融状态,同时进行焊接装载。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004093999 | 2004-03-29 | ||
JP2004093999A JP3994980B2 (ja) | 2004-03-29 | 2004-03-29 | 素子搭載用基板及びその製造方法並びに半導体素子実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1678165A CN1678165A (zh) | 2005-10-05 |
CN100369530C true CN100369530C (zh) | 2008-02-13 |
Family
ID=34988823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200510006752XA Expired - Fee Related CN100369530C (zh) | 2004-03-29 | 2005-02-04 | 元件装载用基板及其制造方法与半导体元件安装方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7476977B2 (zh) |
JP (1) | JP3994980B2 (zh) |
CN (1) | CN100369530C (zh) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005024430B4 (de) * | 2005-05-24 | 2009-08-06 | Infineon Technologies Ag | Verfahren zum Beschichten eines Siliziumwafers oder Siliziumchips |
DE102006053146A1 (de) * | 2006-04-13 | 2007-10-18 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Goldhaltiges Lotdepot, Verfahren zu dessen Herstellung, Lötverfahren und Verwendung |
CN101390210B (zh) * | 2005-12-28 | 2010-07-28 | 联合材料公司 | 半导体元件安装用基板及其制造方法以及半导体装置 |
EP2009971B1 (en) * | 2006-04-17 | 2015-01-07 | DOWA Electronics Materials Co., Ltd. | Solder layer, substrate for device junction utilizing the same, and process for manufacturing the substrate |
JP5526336B2 (ja) | 2007-02-27 | 2014-06-18 | Dowaエレクトロニクス株式会社 | 半田層及びそれを用いたデバイス接合用基板並びにその製造方法 |
JP4341693B2 (ja) * | 2007-05-16 | 2009-10-07 | ウシオ電機株式会社 | Led素子およびその製造方法 |
JP5131438B2 (ja) * | 2007-08-27 | 2013-01-30 | セイコーエプソン株式会社 | 圧電デバイスの製造方法 |
US8698925B2 (en) | 2010-04-21 | 2014-04-15 | Intevac, Inc. | Collimator bonding structure and method |
US9166364B2 (en) * | 2011-02-14 | 2015-10-20 | Spectrasensors, Inc. | Semiconductor laser mounting with intact diffusion barrier layer |
JP5716627B2 (ja) * | 2011-10-06 | 2015-05-13 | オムロン株式会社 | ウエハの接合方法及び接合部の構造 |
JP6100275B2 (ja) * | 2011-11-18 | 2017-03-22 | アップル インコーポレイテッド | 電気的絶縁層を持つマイクロled構造体及びマイクロled構造体のアレイの形成方法 |
US8349116B1 (en) | 2011-11-18 | 2013-01-08 | LuxVue Technology Corporation | Micro device transfer head heater assembly and method of transferring a micro device |
US8573469B2 (en) | 2011-11-18 | 2013-11-05 | LuxVue Technology Corporation | Method of forming a micro LED structure and array of micro LED structures with an electrically insulating layer |
US8333860B1 (en) | 2011-11-18 | 2012-12-18 | LuxVue Technology Corporation | Method of transferring a micro device |
US8426227B1 (en) | 2011-11-18 | 2013-04-23 | LuxVue Technology Corporation | Method of forming a micro light emitting diode array |
US8963305B2 (en) | 2012-09-21 | 2015-02-24 | Freescale Semiconductor, Inc. | Method and apparatus for multi-chip structure semiconductor package |
US9024205B2 (en) | 2012-12-03 | 2015-05-05 | Invensas Corporation | Advanced device assembly structures and methods |
US20160339538A1 (en) * | 2015-05-18 | 2016-11-24 | Toyota Motor Engineering & Manufacturing North America, Inc. | High temperature bonding processes incorporating traces |
EP3450945B1 (en) * | 2016-04-26 | 2022-10-12 | KYOCERA Corporation | Sensor substrate and sensor apparatus |
DE102017112866A1 (de) * | 2017-06-12 | 2018-12-13 | Osram Opto Semiconductors Gmbh | Verfahren zum Befestigen eines Halbleiterchips auf einem Substrat und elektronisches Bauelement |
JP7168280B2 (ja) * | 2018-06-26 | 2022-11-09 | 住友電工デバイス・イノベーション株式会社 | 半導体装置、および、半導体チップの搭載方法 |
EP3905343A4 (en) * | 2018-12-26 | 2022-09-28 | Kyocera Corporation | METHOD OF CONNECTING AN ELECTRONIC COMPONENT AND CONNECTED STRUCTURE |
DE102021131940A1 (de) * | 2021-12-03 | 2023-06-07 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | LÖTVERBINDUNG AUF AuSn-BASIS MIT NIEDRIGER VERBINDUNGSTEMPERATUR |
CN118099927B (zh) * | 2024-04-17 | 2024-07-30 | 化合积电(厦门)半导体科技有限公司 | 一种金刚石芯片及其制备方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4898791A (en) * | 1987-02-19 | 1990-02-06 | Vdo Adolf Schindling Ag | Solderable layer system |
US4929516A (en) * | 1985-03-14 | 1990-05-29 | Olin Corporation | Semiconductor die attach system |
JPH03185877A (ja) * | 1989-12-15 | 1991-08-13 | Sanyo Electric Co Ltd | 光起電力素子の製造方法 |
JPH07147292A (ja) * | 1993-11-25 | 1995-06-06 | Nec Corp | 半導体装置の製造方法 |
JP2001057468A (ja) * | 1999-08-18 | 2001-02-27 | Hitachi Ltd | はんだ接続構造を有する回路装置およびその製造方法 |
CN1350421A (zh) * | 2000-10-25 | 2002-05-22 | 松下电器产业株式会社 | 元件安装系统及安装方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6268114B1 (en) * | 1998-09-18 | 2001-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for forming fine-pitched solder bumps |
US6342442B1 (en) * | 1998-11-20 | 2002-01-29 | Agere Systems Guardian Corp. | Kinetically controlled solder bonding |
US6570251B1 (en) * | 1999-09-02 | 2003-05-27 | Micron Technology, Inc. | Under bump metalization pad and solder bump connections |
DE10308275A1 (de) * | 2003-02-26 | 2004-09-16 | Advanced Micro Devices, Inc., Sunnyvale | Strahlungsresistentes Halbleiterbauteil |
-
2004
- 2004-03-29 JP JP2004093999A patent/JP3994980B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-04 CN CNB200510006752XA patent/CN100369530C/zh not_active Expired - Fee Related
- 2005-02-14 US US11/056,169 patent/US7476977B2/en not_active Expired - Fee Related
-
2007
- 2007-05-11 US US11/747,344 patent/US7452798B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4929516A (en) * | 1985-03-14 | 1990-05-29 | Olin Corporation | Semiconductor die attach system |
US4898791A (en) * | 1987-02-19 | 1990-02-06 | Vdo Adolf Schindling Ag | Solderable layer system |
JPH03185877A (ja) * | 1989-12-15 | 1991-08-13 | Sanyo Electric Co Ltd | 光起電力素子の製造方法 |
JPH07147292A (ja) * | 1993-11-25 | 1995-06-06 | Nec Corp | 半導体装置の製造方法 |
JP2001057468A (ja) * | 1999-08-18 | 2001-02-27 | Hitachi Ltd | はんだ接続構造を有する回路装置およびその製造方法 |
CN1350421A (zh) * | 2000-10-25 | 2002-05-22 | 松下电器产业株式会社 | 元件安装系统及安装方法 |
Also Published As
Publication number | Publication date |
---|---|
JP3994980B2 (ja) | 2007-10-24 |
US20050212140A1 (en) | 2005-09-29 |
CN1678165A (zh) | 2005-10-05 |
US20070207557A1 (en) | 2007-09-06 |
US7452798B2 (en) | 2008-11-18 |
JP2005285882A (ja) | 2005-10-13 |
US7476977B2 (en) | 2009-01-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100369530C (zh) | 元件装载用基板及其制造方法与半导体元件安装方法 | |
KR100541377B1 (ko) | 반도체장치, 반도체장치의 제조방법 및 반도체장치의 제조장치 | |
JP4124740B2 (ja) | 無鉛すず−銀−銅合金はんだ組成物 | |
EP0629467B1 (en) | Lead free, tin-bismuth solder alloys | |
JP2758373B2 (ja) | 低温三元c4ボンディング法 | |
CN100501982C (zh) | 带半导体部件的布线基板 | |
JP2005517535A5 (zh) | ||
JPH04273453A (ja) | 直接チップ取り付け方法 | |
JP2011023721A (ja) | 銅の追加によるハンダ相互接続の改良 | |
US6902098B2 (en) | Solder pads and method of making a solder pad | |
US6258703B1 (en) | Reflow of low melt solder tip C4's | |
JP3718380B2 (ja) | はんだ接続構造を有する回路装置およびその製造方法 | |
US7413110B2 (en) | Method for reducing stress between substrates of differing materials | |
JP5576627B2 (ja) | 半導体装置の製造方法 | |
US8673761B2 (en) | Reflow method for lead-free solder | |
US6574861B1 (en) | System and method for solder ball rework | |
JPH0845940A (ja) | 半田ワイヤ及び半田バンプ電極 | |
US20210183800A1 (en) | Method for Temporarily Fastening a Semiconductor Chip to a Surface, Method for Producing a Semiconductor Component and Semiconductor Component | |
JPH0362926A (ja) | バンプの製造方法 | |
JPH1174448A (ja) | 素子搭載用基板、電子部品およびその製造方法 | |
JPH09153497A (ja) | 半田バンプの形成方法 | |
JPH08125322A (ja) | 高融点はんだバンプ形成方法及び半導体装置 | |
GB2403173A (en) | Soldering refractory metal surfaces | |
JPH06216514A (ja) | プリント回路基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080213 Termination date: 20190204 |
|
CF01 | Termination of patent right due to non-payment of annual fee |