JP5526336B2 - 半田層及びそれを用いたデバイス接合用基板並びにその製造方法 - Google Patents
半田層及びそれを用いたデバイス接合用基板並びにその製造方法 Download PDFInfo
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- JP5526336B2 JP5526336B2 JP2007048170A JP2007048170A JP5526336B2 JP 5526336 B2 JP5526336 B2 JP 5526336B2 JP 2007048170 A JP2007048170 A JP 2007048170A JP 2007048170 A JP2007048170 A JP 2007048170A JP 5526336 B2 JP5526336 B2 JP 5526336B2
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- solder layer
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- bonding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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Description
上記構成において、上層の表面における炭素濃度は、好ましくは、その上層を構成するSnの成分濃度の10原子%未満である。
上記構成によれば、半田層表面を均一に溶解することが可能となり、半田層が溶解凝固後にも平衡状態となるため、デバイスと半田層とで形成される半田接合の初期接合強度を安定させることができると共に、半田接合における不良率を低減できる。
上記構成において、好ましくは、上層の表面における炭素濃度はこの上層を構成するSnの成分濃度の10原子%未満である。
上記構成によれば、半田接合の初期接合強度が高く、半田接合における不良率を低減化できるデバイス接合用基板を提供することができる。
熱処理温度は、好ましくは、150℃より高く、かつ、共晶反応温度未満である。
上記構成によれば、半田層内にAu5Sn相と前記AuSn相とからなる層を分離させて形成することができ、半田層を平衡状態にすることが可能となり、デバイスと半田層との初期接合強度が高く、半田接合における不良率を低減化できる、デバイス接合用基板を製造することができる。
図1は、本発明によるデバイス接合用基板の構造を模式的に示す断面図である。図1に示すように、デバイス接合用基板1は、基板2の片面及び/又は両面に形成される電極層4、図示例では基板2の両面に形成した電極層4と、この電極層4表面の所定箇所に形成される半田層5と、から構成されている。この半田層5は、密着層3を介して電極層4上に形成されてもよい。図示の場合、密着層3の表面側及び裏面側には、それぞれ符号3a、3bを付している。同様に、電極層4は表面側電極層4aと裏面側電極層4bとからなり、半田層5は表面側半田層5aと裏面側半田層5bとから形成されている。ここで、電極層4は、上記基板2の全面に形成してもよいし、電極パターンとして形成してもよい。また、電極層4の一部には、金線を接続して電気回路を形成してもよい。
図5は、図1に示したデバイス接合用基板1に半導体装置7を実装した構造を模式的に示す断面図である。図5に示すように、デバイス接合用基板1において、半導体装置7は表面側の半田層5aにより半田接合をすることができる。
なお、図5及び図6では実装するデバイスとして半導体装置7,15を示しているが、受動素子、スイッチ等や各種能動素子を含む、所謂電子デバイスであれば何でもよく、複数のデバイスが基板上の半田層5,14に半田接合されてもよい。
図7(A)に示すように、本発明の半田層5aは、その溶解前には、溶解開始温度の異なる相が2層5c,5dに分離されて平衡状態になっている。図7(B)は図7(A)の半田層5aを加熱して半田接合温度とした状態、すなわち半田層5aが溶解した状態を、液相5eとして示している。このとき、デバイス7の接合面側である半田層の上層5cは相対的に低い溶解開始温度のAu5 Sn相であり、半田層の下層5dは相対的に高い溶解開始温度のAuSn相であるので、デバイス7の接合面側のAu5 Sn相5cが先に溶解状態となる。すなわち、本発明の半田層5aは上層5cに相対的に低融点のAu5 Snが分離されているため、デバイス接合面側を均一に溶解させることができる。従って、半田層5aの均一な濡れ性を確保することができるため、デバイス7の接合部全体を、半田層5aを介して基板2と接合することができる。さらに、半田層5aのAu5 Sn上層5cのみを溶解させて接合するため、図7(C)に示すように、半田層5aを冷却してデバイス接合した後も、半田層を2層5c,5dに分離した平衡状態に維持することができ、初期接合強度を向上させることができる。
なお、本発明における半田層5の初期接合強度とは、半田層5にデバイス7を半田接合した後、25±10℃の室温雰囲気で放置された状態で、接合後1日以内に測定した接合強度である。
ここで、原子%とは、本発明においてはX線光電子分光分析装置で半田層5の表面を測定した値から算出される値である。データの解析は、最初にバックグラウンド除去を行い、スムージング後、相対感度補正を行ってピーク面積を算出し、錫のピーク面積で規格化した酸素及び炭素の原子濃度である。
ここで、Rは気体定数、PO2は酸素分圧、ΔH゜は標準エンタルピー変化、ΔS゜は標準エントロピー変化であり、ΔH゜およびΔS゜は、下記(2)式で求められる。
・ 式中の熱力学データ(比熱Cp,融点Tm,潜熱ΔHm、標準エンタルピー変化ΔH°(298K)、標準エントロピーS°(298K))としては、非特許文献5及び6に記載のデータを用い、標準生成自由エネルギーを計算した。
図8は、Au,Ag,Cu,Sn及びPの標準生成自由エネルギーと温度との関係を示す図である。この図は所謂エリンガム図である。図8において、横軸は絶対温度(K)であり、縦軸は標準生成自由エネルギー(kJ/mol)である。図8から明らかなように、Au−Sn系合金又はAg−Sn系合金等から成る半田を用いる場合には、最も酸化し易い金属成分はSnとなる。
これにより、半田層5を相の異なる複数層とし、さらにその半田層5のデバイス接合面の炭素濃度や酸素濃度を低減することで、電子デバイス接合用基板1の製造における生産性の向上が可能となる。さらに、デバイス接合後の熱サイクル試験におけるデバイス7の生存率も向上、つまりデバイス接合における信頼性も向上させることができる。
図9(A)に示す状態から、図9(B)に示す半田層5aの接合温度に上昇させて、半田層5aを溶解すると、AuとSnとの溶解開始温度が高い相5f(図の粒状物)がデバイス接合面付近にも存在するため、一部が半田層5aの表面にまで飛び出ている状態となり、デバイス接合面側の半田層5aを均一に溶解することができない。そのため、半田層5aの溶解している箇所とデバイス7との接触面積を小さくし、デバイス7と半田層5aとの接合が局所的に阻害されるため、良好な半田接合強度が得られなくなる。
図10は図1のデバイス接合用基板の製造工程を順次に示すフローチャートである。
ステップST1にて、AlNから成る基板2を用意する。ステップST2にて、上記基板2の表面をラップ,ポリッシュ等の工程により研削及び研磨した後、ステップST3にて、フォトリソグラフィ法等によりパターニングを行い、電極層4が形成される領域のみを露出させる。
次にステップST6にて、上記基板上に半田層5を各種の蒸着法を用いて形成し、さらにリフトオフ工程により、上記半田層5の所定のパターンのみを残して、他の部分を除去する。
図11に示すように、半田層5とデバイス7は別々に加熱し、半田層5が半田接合温度T2に到達したときにデバイス7を半田層5上に載置した後、半田層5の温度を下げ始めるまで押圧治具22により押圧する方法である。この場合には、デバイス7を押圧している時間を短くしても、デバイス7と半田層5の接合不良を低減化できるため、簡単な装置で半田接合を行うことができ、さらにデバイス接合用基板の生産性を向上させることが可能になる。
最初に、デバイス接合用基板1の製造方法について、サブマウント1に適用した実施例について説明する。
AlNからなる基板2の両面を洗浄して表面清浄化を行い、この基板2の表面上に厚さ0.05μmのTi密着層3、密着層3上に厚さが0.2μmのPtと厚さが0.5μmのAuから成る電極層4、電極層4上の一部に、厚さ3μmで組成比としてAu:Sn=70:30(重量比)の半田層5を真空蒸着法により形成した。成膜条件は真空度を1×10-4Pa、基板温度を80℃とした。
上記の加工を施した基板2を、水素濃度が95%の還元性ガス雰囲気中において、共晶反応温度の278℃未満である220℃で10時間、半田層5の熱処理を施し、実施例1のサブマウント1を製造した。次に、サブマウント1の半田層5の密着強度を調べるためにテープ剥離テストを行った。
(比較例1)
半田層5の熱処理温度を120℃とした以外は、実施例1と同様にして、比較例1のサブマウントを製造した。テープ剥離テストを行った後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。発光ダイオード7の接合方法は実施例1と同様の方法で行った。
半田層5の熱処理温度を150℃とした以外は、実施例1と同様にして、比較例2のサブマウントを製造した。テープ剥離テストを行った後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。発光ダイオード7の接合方法は実施例1と同様の方法で行った。
半田層5の熱処理温度を280℃、すなわち半田層を溶解させた以外は、実施例1と同様にして、比較例3のサブマウントを製造した。テープ剥離テストを行った後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。発光ダイオード7の接合方法は実施例1と同様の方法で行った。
接合強度τ=荷重(kg)×重力加速度(m/s2 )/せん断面の面積(m2)(3)
ここで、せん断面の面積は、半田接合される面、すなわち、発光ダイオード7底面の面積(300μm×300μm)である。せん断方向のせん断面の長さは、発光ダイオード7のチップ側面に垂直な方向の長さであり、300μmである。
半田層5の熱処理を大気中で行った以外は、実施例5と同様にして比較例4のサブマウントを製造した。テープ剥離テストを行った後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。発光ダイオード7の接合は、実施例1と同様に行った。
半田層5の熱処理を行わない以外は、実施例5と同様にして比較例5のサブマウントを製造した。テープ剥離テストを行った後、剥離不良の無かったサブマウントの半田層に300℃で発光ダイオード7を接合した。発光ダイオード7の接合は、実施例1と同様に行った。
図13から明らかなように、半田層5の蒸着直後において、半田層5内には粒状に偏析した箇所が観察され、各相が、ナノオーダーの寸法で局在化していると推定される。図13からも明らかなように、蒸着直後は、AuSn相及びAu5Sn相の各相が粒子状に分布していることを確認した。半田層に熱処理を施さない比較例4における半田層の断面も、上記実施例5のサブマウントにおける熱処理前の半田層5の断面と同様であった。
一方、図14から明らかなように、基板上に作製した半田層5に熱処理を行った半田層5は、相状態が異なる2層に分離されて、さらに半田層5の溶解凝固後においても層状に分離されている。このように、熱処理により半田層5中が相の異なる層に分離され、それぞれの相が平衡状態となっていることが分かる。さらに、溶解凝固後にも同様の相状態、層構造を維持していることから、半田層5のデバイス接合面である上層5cが溶解していることが判明した。
表2に示す半田層5の表面酸素濃度及び炭素濃度は、実施例5、6及び比較例4のサブマウント1において、半田層5の熱処理後の発光ダイオード7を接合する前に、半田層5の最外層表面における酸素及び炭素濃度をX線光電子分光分析装置(ESCA、日本電子製、JPS−9000MC)で測定した値である。X線源としてはMgのKα線を用い、X線源における電子の加速条件は、電圧が10kVで、電流が20mAである。データは5回のスキャンの積算値を取得した。データの解析は、最初にバックグラウンド除去を行い、スムージング後、相対感度補正を行い、ピーク面積を算出し、錫のピーク面積で規格化した酸素及び炭素の原子濃度を得た。
以上のことから、半田接合前に半田層5を還元性ガス雰囲気中で熱処理を行うことで、短時間の半田接合においても、発光ダイオード7を半田層5に高い初期接合強度で接合することが可能となり、歩留まりも向上できることが分かる。
これにより、発光ダイオード7を接合前に、半田層5を還元性ガス雰囲気中での熱処理を行うことで、半田層5を相が異なる2層に分離し、かつ半田層5c表面の酸素濃度や炭素濃度を減少させることができる。このような半田層5を用いた半田接合において、半田層5を溶解させた後に発光ダイオード7を接触させて半田層5を凝固する半田接合方法においても、発光ダイオード7と半田層5を高い初期接合強度で接合することが可能となり、歩留まりも向上できることが判明した。
2:基板
3:密着層
4,13:電極層
5,5a,5b,14:半田層
5c:半田層のデバイス接合面側の半田層(Au5 Sn)
5d:半田層の基板接合面側の半田層(AuSn)
5e:液相
5f:溶解開始温度が高い相
7,15:半導体装置(デバイス)
11:金属基板
12:セラミック層(セラミック薄膜)
15a:半導体装置の下部電極
15b:半導体装置の上部電極
16:Au線
22:押圧治具
Claims (6)
- 基板上に形成された鉛を含まない半田層であって、
上記半田層が、共晶組成以外の組成としたAu−Sn系合金で構成され、上記基板側のAuSn相のみからなる下層と該下層上に形成され下層よりも融点の低いAu5Sn相のみからなる上層の二層で成り、
該上層の表面における酸素濃度が、その上層を構成する金属成分の内で最も酸化し易いSnの成分濃度の30原子%未満であることを特徴とする、半田層。 - 前記上層の表面における炭素濃度は、該上層を構成する前記Snの成分濃度の10原子%未満であることを特徴とする、請求項1に記載の半田層。
- 基板と該基板上に形成される鉛を含まない半田層とを含むデバイス接合用基板であって、
上記半田層が、共晶組成以外の組成としたAu−Sn系合金で構成され、上記基板側のAuSn相のみからなる下層と該下層上に形成され下層よりも融点の低いAu5Sn相のみからなる上層の二層で成り、
該上層の表面における酸素濃度が、その上層を構成する金属成分の内で最も酸化し易いSnの成分濃度の30原子%未満であることを特徴とする、デバイス接合用基板。 - 前記上層の表面における炭素濃度は、該上層を構成する前記Snの成分濃度の10原子%未満であることを特徴とする、請求項3に記載のデバイス接合用基板。
- 基板と該基板上に形成される鉛を含まない半田層とを含むデバイス接合用基板の製造方法であって、
金と錫とを主成分とする共晶組成以外の組成のAu−Sn系合金からなる半田層を、上記基板上に形成し、
上記半田層を、還元雰囲気中で熱処理を行って、上記半田層の基板側のAuSn相のみからなる下層と、該下層上のAu5Sn相のみからなる上層とに分離することを特徴とする、デバイス接合用基板の製造方法。 - 前記熱処理温度が、150℃より高く、かつ、共晶反応温度未満であることを特徴とする、請求項5に記載のデバイス接合用基板の製造方法。
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DE102008011265.8A DE102008011265B4 (de) | 2007-02-27 | 2008-02-27 | Verfahren zum Herstellen eines Substrats zum Bonden von Vorrichtungen mit einer Lötschicht |
US12/037,958 US8747579B2 (en) | 2007-02-27 | 2008-02-27 | Solder layer and device bonding substrate using the same and method for manufacturing such a substrate |
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WO2018139770A1 (ko) * | 2017-01-26 | 2018-08-02 | 엘지이노텍 주식회사 | 반도체 소자 및 반도체 소자 패키지 |
DE102017104276B4 (de) * | 2017-03-01 | 2020-01-16 | Osram Opto Semiconductors Gmbh | Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement |
DE102017108422A1 (de) | 2017-04-20 | 2018-10-25 | Osram Opto Semiconductors Gmbh | Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement |
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