CN100358114C - 形成穿透电极的方法以及具有穿透电极的基片 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000000149 penetrating effect Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000004020 conductor Substances 0.000 claims description 41
- 230000004888 barrier function Effects 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 4
- 230000001681 protective effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000002002 slurry Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000001680 brushing effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 239000011135 tin Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000013532 laser treatment Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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Abstract
一种形成穿透电极的方法,其中导电物质被置入一微孔中,该微孔只有一端被由导电物质形成的布线和垫片封住,而布线和垫片没有破损。在形成穿透电极的方法中,导电物质被置入微孔中,所述微孔穿透基片且一个开口被导电薄膜封住。在支撑导电薄膜的保护元件在基片的导电薄膜侧的表面上配置之后,导电物质从微孔的另一开口置入。
Description
技术领域
本发明涉及一种形成穿透电极(penetration electrode)的方法以及其上粘附有穿透电极的基片。尤其涉及一种适合于当制造用于在电子装置以及光学装置等装置中布线使用的穿透电极,或者是当装置堆叠连接时用于布线层的穿透电极时的一种形成穿透电极的方法。本发明也涉及其上粘附有穿透电极的基片。
背景技术
为了缩小电子装置和光学装置的尺寸,提高其性能,或为了将这些装置堆叠,有时用穿透电极将基片的正面和背面电连接。现有技术中,穿透电极的制造采用如图1A至图1C所示的方法。
如图1A所示,由导电薄膜2形成的布线(wiring)和垫片(pad)配置在基片1的一个主表面A。该布线和垫片用于实现与其它基片或装置电连接。
首先如图1B所示,微孔从基片1的另一主表面B径直延伸至导电薄膜2的下面。用于形成微孔3的方法的实施例包括以感应耦合等离子体反应离子蚀刻(ICP-RIE)为代表的深度反应离子蚀刻(DRIE)、采用氢氧化钾溶液或类似溶液的各向异性蚀刻以及激光处理。必要时,可以在主表面B和微孔3的孔壁表层涂一层绝缘层。
之后如图1C所示,导电物质4从主表面B置入微孔3中,以便能够完全充满微孔3的内部。置入导电物质4的方法可以是熔融金属置入法或刷涂法。此时,为使导电薄膜2形成的布线和垫片与导电物质4实现电连接,穿透基片1前后的穿透电极形成在微孔3的后端(参见已公开的日本专利申请(JP-A)2002-158191号)。
如上所述,在现有的形成穿透电极的方法中,由于微孔的一端被导电薄膜形成的布线和垫片封住,而且导电薄膜的厚度经常小于几μm或更小,因此这部分的机械强度很小,而且在有些情况下,制造过程中会发生传送时薄膜破损的情况。
而且,采用刷涂法将导电浆置入微孔中时,为了在微孔的后端实现可靠性高的电连接,我们希望将刷涂压力增大一些,然而,当刷涂压力增大的时候,会发生置入的导电浆通过导电薄膜溢出的现象。
考虑到上述情况,本发明的目的是提供一种形成穿透电极的方法,其中导电物质被置入微孔中,在导电物质形成的布线和垫片不破损的情况下,其一端仅仅被布线和垫片封住,本发明还提供一种其上粘附有穿透电极的基片。
发明内容
为实现上述目的,本发明提供了一种形成穿透电极的方法,其中导电物质被置入穿透基片且其中一个开口被导电薄膜封住的微孔中。在微孔形成的位置上设置有包覆导电薄膜的保护元件。
保护元件20通过使用例如热熔胶而粘附到基片10,以便简单地通过加热基片10而被去除。保护元件可在置入导电物质之后被去除。
导电物质从与被导电薄膜封住的口径相对的微孔的口径置入。
本发明的方法中,优选的是,导电物质由金属制成,且从被导电薄膜封住的第一开口相对的微孔的口径置入。
将所述导电物质置入微孔中的步骤包括:对所述导电薄膜朝向保护元件的一侧施加第一压力以及对所述导电物质朝向第一开口的一侧施加第二压力,且在所述导电薄膜朝向保护元件的一侧的压力可大于在所述第一开口一侧的压力。
可选的是,导电物质由导电浆制成,且采用刷涂法置入微孔中。
除此之外,本发明还提供一种其上粘附有穿透电极的基片,该穿透电极采用本发明的形成穿透电极的方法形成。
附图说明
图1A、1B、1C所示为现有形成穿透电极的方法中制造过程的主体部分的截面视图。
图2A、2B、2C和2D所示为本发明所述方法的一个实施例中制造过程的主体部分的截面视图。
图3A和3B所示为本发明所述方法的另一实施例中主体部分的截面视图。
具体实施方式
上面描述并示意了本发明的具体实施方式,上述内容应该理解为是本发明的例证,不应该理解为对本发明的限制。在不脱离本发明的实质和范围的情况下,可以做出对本发明的增加、删除、替换和其它修改。此外,本发明不应被理解为仅限于上述内容,而应理解为后附权利要求书所述的范围。
下面结合附图对本发明的各具体实施例进行描述。
图2A至2D所示为本发明形成穿透电极的方法的一个实施例的制造过程。
图2A所示为一个其上将形成有穿透电极的基片10。本发明中使用了各种基片,如半导体基片、陶瓷基片和玻璃基片。基片的厚度可根据基片的计划用途来选择,大约在50μm至1mm之间。
该实施例中,采用硅基片作为基片10。如图2A所示,由二氧化硅膜形成的绝缘层11形成于基片10的两个主表面A和B,二氧化硅膜的厚度为几μm或更小,优选的是大约1μm。
导电薄膜12形成于基片10的一个主表面A上。必要时,导电薄膜12可以形成图案和用于与其它基片和装置电连接时使用的垫片和布线。
如铝、金、铂、钛、银、铜、铋、锡、镍、铬、锌等金属或这些金属的合金可以选作导电薄膜12。导电薄膜12可以采用各种现有的公知方法形成,例如溅射法、真空沉积法、电镀法等。导电薄膜12的厚度正常情况下为几μm或更小。
接着如图2B所示,微孔13沿着基片10的主表面B侧延伸至导电薄膜12而形成。首先,微孔13所形成处的主表面B的绝缘层11被去除。之后,主表面A侧上的基片10和绝缘层11采用DRIE方法蚀刻,直到接触到导电薄膜12。用于形成微孔13的方法可以采用氢氧化钾等溶液或激光处理等各向异性蚀刻,还可以是以感应耦合等离子体反应离子蚀刻(ICP-RIE)为代表的深度反应离子蚀刻(DRIE)。同时,当该微孔形成时或形成之后,在微孔13的孔壁上形成一层新的绝缘层11,结果,如图2B所示,在微孔13的结构中,其一端被导电薄膜12封住。
根据所制造的穿透电极15的配置,所形成的微孔13的直径可以在大约5至200μm的范围内。
之后如图2C所示,保护元件20与基片10的主表面A相联结,由此导电薄膜12可以由保护元件20支撑。任何具有平面部分且能够通过平面部分支撑导电薄膜12的元件都可以用作保护元件20。这类元件包括玻璃基片、半导体基片,如硅、陶瓷基片和塑料基片。优选的是,保护元件20采用热熔胶、紫外强力胶等与基片10的主表面A相联结。采用热熔胶是最好的,这是因为采用热熔胶可以使粘附到基片10的保护元件20仅仅通过加热基片10就能够去除。如以下所述,保护元件20可以在置入导电物质之后被去除。需要注意的是,保护元件20仅仅支撑导电薄膜12的微孔结构部分就可以了。然而,如图2C所示,优选的是保护元件20支撑整个导电薄膜12。
之后如图2D所示,采用刷涂法或熔融金属置入法,从主表面B向微孔13中置入导电物质14。
如果采用刷涂法,那么如铜浆、银浆、碳浆、金-锡浆等导电浆可以用作导电物质置入微孔13中。
如果采用熔融金属置入法,那么如锡和铟等低熔点金属或焊料,如金-锡焊料、锡-铅焊料、锡焊料、铅焊料、金焊料、铟焊料、铝焊料等,可以用作导电物质置入微孔13中。
如果导电物质14如铜浆采用刷涂法置入,那么刷涂压力设置在一个足够大的水平,以保证导电薄膜12和导电物质14之间的电连接。该实施例中,由于导电薄膜12的一个表面被保护元件20支撑,即使导电物质14以较高的压力置入微孔13中,也不会出现导电薄膜12破损的现象。导电薄膜朝向保护元件的一侧的第二压力可大于导电薄膜朝向第一开口的一侧的第一压力。
通过这种方法,导电物质14被置入微孔13中,形成了将基片10的前后端电连接的穿透电极15。
该实施例中,由于导电物质14被置入微孔13中,在导电薄膜12由布线和垫片等封住微孔13一端的物质形成之后,由于导电薄膜12被保护元件20支撑,因此脆弱的导电薄膜12形成的布线和垫片也就受到保护元件20的保护。由此,能防止现有技术中存在的传送过程中布线和垫片的破损现象的发生。
此外,和现有技术相比,由于在较高的压力下将导电物质14置入微孔13而不破坏导电薄膜12的布线和垫片等成为可能,因此能够形成具有高可靠性的电连接的穿透电极15。
此外,由于采用该方法制得的其上粘附有穿透电极的基片提供了在导电薄膜12不发生破损的情况下导电物质14与导电薄膜12之间高度可靠的电连接,因此可靠性得到提高。
图3A至3B所示为本发明所述形成穿透电极的方法的另一实施例。在前述实施例中,微孔13在基片10中形成后,保护元件20与基片10相联结,而该实施例中,如图3A所示,通过将保护元件20联结在基片10的主表面A上,导电薄膜12受到保护,之后微孔13才在基片10中形成,如图3B所示。然后,采用刷涂法或熔融金属置入法将导电物质14置入微孔13中,以形成穿透电极15。
该实施例中,除可以实现和前述实施例相同的效果,还可以实现另外的效果。在微孔13形成之前采用保护元件支撑导电薄膜12,可以防止微孔13的形成过程中或向后续程序传送的过程中导电薄膜12的破损。
例证:
图2A至2D所示为根据该方法制造其上粘附有穿透电极的基片的示意图。
采用厚度为100μm的硅基片作为基片10。如图2A所示,由二氧化硅膜形成的厚度大约为1μm的绝缘层11形成于基片11的两个主表面A和B上,然后将铝制的导电薄膜12形成于主表面A上。
之后,如图2B所示,微孔13从主表面B延伸至导电薄膜12。首先,主表面B上的绝缘层11在微孔13形成的位置被去除。之后,主表面A上的基片10和绝缘层11采用DRIE法蚀刻,直至接触到导电薄膜12。在微孔13的孔壁上形成一层新的绝缘层11,以便形成由导电薄膜12封住其一端的微孔13。微孔13的直径为100μm。
之后,如图2C所示,厚度为300μm由玻璃基片形成的保护元件20采用粘合剂联结在基片10的主表面A,以便保护元件20支撑该导电薄膜12。
之后,如图2D所示,采用刷涂法从主表面B将由铜浆形成的导电物质14置入微孔13中。此时,设置刷涂压力,以实现导电薄膜与铜浆之间的电连接。因此,制成了与基片10的前后端电连接的穿透电极15。制得的穿透电极没有诸如导电薄膜12撕破或破损的缺陷,而且导电薄膜12和置入微孔13之间的导电基片14之间能实现很好的电连接。
如上所述,根据本发明的方法,由于导电物质在布线和垫片等封住微孔一端的物质的导电薄膜受保护元件的保护之后被置入微孔中,因此,脆弱的导电薄膜形成的布线和垫片受保护元件的保护,而且防止现有技术中的传送过程中布线和垫片的破损。
而且,和现有技术相比,由于在较高的压力下将导电物质置入微孔而不破坏导电薄膜12的布线和垫片等成为可能,因此能够形成具有高可靠性的电连接的穿透电极。
此外,由于本发明的其上粘附有穿透电极的基片具有采用本发明的方法制作的穿透电极,因此使得在无需破损导电薄膜的情况下,实现导电物质和导电薄膜之间的可靠的电连接并提高可靠性成为可能。
Claims (12)
1、一种形成穿透电极的方法,包括:
在基片上至少穿透电极形成位置的部分所对应的基片的第一表面上配置一层导电薄膜,所述基片包括设置在基片的第一表面上的第一绝缘层和设置在与所述第一表面相对的第二表面上的第二绝缘层;
形成一微孔,所述微孔从所述基片的第二表面到所述基片的第一表面上的所述导电薄膜穿透所述基片;
在所述微孔的侧壁上形成绝缘层;
通过将一保护元件联结到所述基片的第一表面而将所述保护元件提供在所述导电薄膜上;以及
将导电物质置入所述微孔中,所述导电物质和导电薄膜形成一个穿过所述基片的导电通道;
其中所述导电薄膜封住基片第一表面上的微孔的第一开口,且
其中所述导电物质通过在所述基片的第二表面的所述微孔的开口置入所述微孔。
2、如权利要求1所述的形成穿透电极的方法,其特征在于,所述导电物质由金属制成,且采用熔融金属置入法置入微孔中。
3、如权利要求1所述的形成穿透电极的方法,其特征在于,所述导电物质由导电浆制成,且采用刷涂法置入微孔中。
4、如权利要求1所述的形成穿透电极的方法,还包括:
在所述导电物质置入所述微孔中之后,从所述基片上去除保护元件。
5、如权利要求4所述的形成穿透电极的方法,其特征在于,所述保护元件通过加热所述基片从导电薄膜和基片上去除。
6、如权利要求1所述的形成穿透电极的方法,其特征在于,将所述导电物质置入所述微孔中的步骤包括:对所述导电薄膜朝向所述微孔的第一开口的一侧施加第一压力,
当对所述导电薄膜朝向所述微孔的第一开口的一侧施加第一压力时,所述保护元件在适当的位置支撑所述导电薄膜。
7、如权利要求6所述的形成穿透电极的方法,其特征在于,施加于所述导电薄膜朝向所述保护元件的一侧的第二压力大于所述第一压力。
8、如权利要求1所述的形成穿透电极的方法,其特征在于,所述导电物质充满所述微孔。
9、如权利要求1所述的形成穿透电极的方法,其特征在于,所述导电薄膜与所述导电物质为不同的材料。
10、一种具有穿透电极的基片,包括:
一个基片;
位于具有穿透电极的基片的至少一部分中的基片第一表面上的导电薄膜;
穿透基片且由导电物质充满的微孔,所述微孔的一端由导电薄膜封住,所述导电物质与所述导电薄膜相接触;以及
保护元件,位于所述导电薄膜的至少一部分上,所述导电薄膜的所述部分封住所述微孔的一端,在所述导电薄膜与所述微孔相对的一侧,所述保护元件与所述基片相联结并防止所述导电薄膜破损。
11、如权利要求10所述的具有穿透电极的基片,还包括:
顺着所述微孔的侧壁排列的第一绝缘层;以及
基片第一表面上的第二绝缘层,位于所述导电薄膜与所述基片之间,所述微孔穿透由导电薄膜封住的所述微孔一端的第二绝缘层,所述导电物质与所述导电薄膜之间的连通不被所述第二绝缘层隔断,
所述第一绝缘层与所述第二绝缘层相连。
12、如权利要求11所述的具有穿透电极的基片,还包括:
第三绝缘层,位于所述基片的与所述第一表面相对的第二表面上;
其中,在填充所述导电物质的微孔处有一个穿过所述第三绝缘层的开口,以及
其中,所述第三绝缘层与所述第一绝缘层相连。
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