CN100352047C - 用于半导体器件的非铸模封装 - Google Patents

用于半导体器件的非铸模封装 Download PDF

Info

Publication number
CN100352047C
CN100352047C CNB028044363A CN02804436A CN100352047C CN 100352047 C CN100352047 C CN 100352047C CN B028044363 A CNB028044363 A CN B028044363A CN 02804436 A CN02804436 A CN 02804436A CN 100352047 C CN100352047 C CN 100352047C
Authority
CN
China
Prior art keywords
semiconductor device
chip
substrate
pcb
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028044363A
Other languages
English (en)
Other versions
CN1489788A (zh
Inventor
R·乔希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of CN1489788A publication Critical patent/CN1489788A/zh
Application granted granted Critical
Publication of CN100352047C publication Critical patent/CN100352047C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种不包括铸模体即封装的半导体器件。该半导体器件包括基片(12)和连接到基片的芯片(11)。在设想为MOS场效应晶体管类型时，该芯片是这样连接到基片的，使得芯片的源如栅极区被连接到基中。焊球(13)是这样被连接到与芯片相邻的，使得当半导体器件被连接到印刷电路板时，芯片的曝露表面用作漏的连接，而焊球则用作源和栅的连接。

Description

用于半导体器件的非铸模封装
技术领域
本发明涉及一种用于半导体器件的封装，具体地说，涉及一种用于不需要铸模体的半导体器件的封装。
背景技术
通常，半导体器件，特别是MOS场效应晶体管，需要有具有良好热性能的非常低的封装电阻(RDSon)。通常，它还需要有简单、快速而又有效的方法来封装半导体器件。因此，在现有的技术中，已经发展了许多封装想法和方法。
一种这样的封装相法的一个例子包含有球栅阵列(ball grid array BGA)。这样一种想法包含源栅极阵列和直接连接到印刷电路板(PCB)上的栅漏焊球。这就需要一个凸出芯片和用来便于漏接触的引线框，另一封装想法是一般被称之为导入铸模封装中的反装晶片(Flip chip in beaded Molded Package，FLMP)，它包括铸模的导入表面安装封装，在这封装上把凸出的芯片连接到框架的栅和源的漏点。在芯片背侧的漏从铸模综合体即本体上曝露出来，并通过标准线路板安装工艺过程中的焊料回流被连接到PCB。另外的封装想法使用铜带和/或金属线焊接技术。
这些现有技术的想法牵涉到各种组成部分，并可能导致复杂的制作(封装)工艺。
发明内容
本发明提供一种半导体器件，它包括基片和连接到基片的芯片，又把多个焊球连接到与芯片相邻的基片。当半导体器件连接到印刷电路板时，焊球与芯片的表面基本上是共面的。因此，在半导体器件是MOS场效应晶体管的情况下，当半导体器件被连接到PCB时，不与基片连接的芯片表面用作直接的漏连接，而基片和焊球用作源和栅的连接。
按照本发明的一个方面，基片包括基本层金属层和在基本层和金属之间的绝缘层。
按照本发明的另一个方面，该基本层包括金属化的图形，而该金属层包括另一金属化的图形用作热播散器。
按照本发明的还有一个方面，基本是金属化的陶瓷片。
按照本发明仍然还有另一个方面，该基片包括两层金属化的陶瓷片，这两层可便于把两个芯片(硅)附着在相对的面上。
本发明也提供一种包括提供基片和芯片的封装半导体器件的方法，在MOS场效应晶体管中的焊料，或任何适合的导电性内连，至少被放在基片和芯片中的一个上，而该芯片是被反装到基片上的。然后把该焊球放在与芯片相邻的基片上。
本发明的特点和优点将在阅读并理解列于下文的较佳示范性实施例的详细描述，连同参考附图，后理解，在附图中的相同数字代表相同的元件。
附图说明
图1是根据本发明半导体器件的平面图，
图2是示于图1半导体器件的沿直线A-A所见到的侧截面图；
图3是根据本发明另一半导体器件的平面图；
图4是示于图3半导体器件的沿直线B-B所见到的侧截面图；
图5是根据本发明替换实施例的侧截面图。
具体实施方式
图1示出半导体器件的一个MOS场效应晶体管10，它包括芯片11，基片12和焊球13。该基片包括栅极区14。
正如在图2中见到的，该基中较佳地包括基本层20，和顶部金属层21。基本层和顶部金属层由绝缘层22所分开，较佳的是把这两层连接起来的绝缘外延层。基本材料较佳的是包括金属化图形，而顶部金属层较佳的是包括另一金属化图形，金属层也可用作热播散器。
芯片较佳的是用高温焊浆连接到基片，但是也可用在本技术领域中知道的任何合适的导电性内连来连接。把焊球放在芯片对面的侧面上与芯片邻近，其中至少把一个焊球放在基片的栅极区上。
因此，在使用时，把半导体器件放在印刷电路板上并用焊浆或合适的导电性内连把芯片的表面直接连接到PCB，从而用作漏连接。连接到基片的芯片表面包括芯片的栅极区和源区。因此，在基片栅极区中的焊球用来把芯片的栅极区连接到PCB而余下的焊球通过基片把芯片的源区连接到PCB。从而，基片的栅极区与基片的其余部分是电绝缘的。
制作即封装这样一种半导体器件的方法包括把焊浆放在基片和芯片中的一个并把芯片附着于基片的反装晶片上。然后，较佳的是要测试这种组合。于是平整该半导体器件并对该半导体器件再测试。
要把焊球放到这样的高度，使得当把半导体器件连接到PCB时，该焊球基本上与芯片漏表面是共面的，从而，使半导体器件能嵌平在PCB上。
在一替换的实施例上，不把焊球放在半导体器件上，而宁可是在PCB上，于是半导体器件就向该向被连接。
参考图3，示出了根据本发明半导体器件的一替换实施例。在这实施例中，基片包括金属化的陶瓷片。用于该基片的材料例子包括被绝缘的金属基片。
在这样的实施例中，芯片的曝露表面用作到PCB的漏连接，而焊球则用作到PCB的栅极和源的连接。
示于图3和图4的器件是用参考示于图1和2的半导体器件在上面描述的类似方式制作的。
因此，本发明提供一种半导体器件，这种器件提供改良的器件散热，由于芯片的背面直接焊接到PCB，而MOS场效应晶体管的源和栅极较佳的是通过高温焊浆焊到基片上。因此，芯片不需要凸出的芯片，而宁可说是需要象，例如具有金属外层的化学镀镍(或电解镍)的可焊的顶部金属层表面。而且，由于它不涉及象金属丝焊接，铸模，去除模锻毛边，整平和形成以及电镀的专用操作的形成因素，所以组装工艺被显著地简化。此外，由于焊球在设计过程中是可移动的，所以对于半导体布置的迹印现在是可变换。
正如在图5中所见到的，本发明也可在高密度封装方案中(在基片12的每个侧面上有多于一个芯片能容易地组合多于两个芯片11a，b。在这样做的时候，可以在不用表面安装封装制造的常规方法下获得一个高密度集成的简易方法，而它是与诸如铸模，去除模锻毛边，整平和形成加工无关的形成因素。基片包括两层金属化的陶瓷片，用绝缘层把它们分开或相反用电的方法来隔离。因此，焊球的位置决定于每个芯片的源和栅极的连接。如果要想把芯片11b的漏连接到PCB，则可采用诸如金属焊接的已知技术。
虽然本发明已经参考了专门的实施例作了描述，但要体会到，它的本意是在所附权利要求书的范围内覆盖所有的修改和等价技术方案。

Claims (4)

1.一种连接于印刷电路板(PCB)的半导体器件，包括：
基片，包括第一侧和第二侧；
包含边缘的半导体芯片，其耦合至所述基片的第一侧，所述半导体芯片包括第一表面和耦合到所述基片的第二表面，当将所述半导体器件安装到所述印刷电路板上时，该第一表面作为连接到所述印刷电路板的漏极连接，其中所述第二表面包括源极区和栅极区；以及
焊球，耦合至所述半导体芯片边缘的基片外侧，其中，当所述半导体芯片安装于所述印刷电路板之上时所述焊球与所述半导体芯片基本共面，且其中所述焊球用作到所述源极区和栅极区的源极连接和栅极连接。
2.如权利要求1所述的半导体器件，其特征在于，所述基片包括基极层、金属层和在该基极层和金属层之间的绝缘层。
3.如权利要求1所述的半导体器件，其特征在于，所述半导体芯片是第一芯片，且其中，所述半导体器件包括在所述基片第二侧上的第二芯片。
4.如权利要求1所述的半导体器件，其特征在于，所述芯片具有一个MOSFET。
CNB028044363A 2001-02-01 2002-01-17 用于半导体器件的非铸模封装 Expired - Fee Related CN100352047C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/776,341 US6469384B2 (en) 2001-02-01 2001-02-01 Unmolded package for a semiconductor device
US09/776,341 2001-02-01

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN200710162352A Division CN100576483C (zh) 2001-02-01 2002-01-17 用于半导体器件的非铸模封装

Publications (2)

Publication Number Publication Date
CN1489788A CN1489788A (zh) 2004-04-14
CN100352047C true CN100352047C (zh) 2007-11-28

Family

ID=25107113

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB028044363A Expired - Fee Related CN100352047C (zh) 2001-02-01 2002-01-17 用于半导体器件的非铸模封装
CN200710162352A Expired - Fee Related CN100576483C (zh) 2001-02-01 2002-01-17 用于半导体器件的非铸模封装

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN200710162352A Expired - Fee Related CN100576483C (zh) 2001-02-01 2002-01-17 用于半导体器件的非铸模封装

Country Status (6)

Country Link
US (4) US6469384B2 (zh)
JP (2) JP4729244B2 (zh)
CN (2) CN100352047C (zh)
DE (1) DE10295972B4 (zh)
TW (1) TW535243B (zh)
WO (1) WO2002061832A1 (zh)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6870254B1 (en) * 2000-04-13 2005-03-22 Fairchild Semiconductor Corporation Flip clip attach and copper clip attach on MOSFET device
US6989588B2 (en) * 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
US6753605B2 (en) * 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6798044B2 (en) * 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6891256B2 (en) 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
DE10392377T5 (de) 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
TWI287282B (en) * 2002-03-14 2007-09-21 Fairchild Kr Semiconductor Ltd Semiconductor package having oxidation-free copper wire
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
TW560023B (en) * 2002-06-20 2003-11-01 Advanced Semiconductor Eng Semiconductor device and method for manufacturing a semiconductor package
US7061077B2 (en) * 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6777800B2 (en) 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US6806580B2 (en) * 2002-12-26 2004-10-19 Fairchild Semiconductor Corporation Multichip module including substrate with an array of interconnect structures
US7217594B2 (en) * 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6873043B2 (en) * 2003-03-10 2005-03-29 Delphi Technologies, Inc. Electronic assembly having electrically-isolated heat-conductive structure
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
US7154186B2 (en) * 2004-03-18 2006-12-26 Fairchild Semiconductor Corporation Multi-flip chip on lead frame on over molded IC package and method of assembly
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
US7501702B2 (en) * 2004-06-24 2009-03-10 Fairchild Semiconductor Corporation Integrated transistor module and method of fabricating same
US7256479B2 (en) * 2005-01-13 2007-08-14 Fairchild Semiconductor Corporation Method to manufacture a universal footprint for a package with exposed chip
CN101807533B (zh) * 2005-06-30 2016-03-09 费查尔德半导体有限公司 半导体管芯封装及其制作方法
US7504733B2 (en) 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
US20090057852A1 (en) * 2007-08-27 2009-03-05 Madrid Ruben P Thermally enhanced thin semiconductor package
US7371616B2 (en) * 2006-01-05 2008-05-13 Fairchild Semiconductor Corporation Clipless and wireless semiconductor die package and method for making the same
US7345499B2 (en) * 2006-01-13 2008-03-18 Dell Products L.P. Method of Kelvin current sense in a semiconductor package
US20070164428A1 (en) * 2006-01-18 2007-07-19 Alan Elbanhawy High power module with open frame package
US7868432B2 (en) * 2006-02-13 2011-01-11 Fairchild Semiconductor Corporation Multi-chip module for battery power control
US7446375B2 (en) * 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7618896B2 (en) * 2006-04-24 2009-11-17 Fairchild Semiconductor Corporation Semiconductor die package including multiple dies and a common node structure
US7656024B2 (en) * 2006-06-30 2010-02-02 Fairchild Semiconductor Corporation Chip module for complete power train
US20080036078A1 (en) * 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
US7564124B2 (en) * 2006-08-29 2009-07-21 Fairchild Semiconductor Corporation Semiconductor die package including stacked dice and heat sink structures
US8106501B2 (en) * 2008-12-12 2012-01-31 Fairchild Semiconductor Corporation Semiconductor die package including low stress configuration
US7768105B2 (en) 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US7821116B2 (en) * 2007-02-05 2010-10-26 Fairchild Semiconductor Corporation Semiconductor die package including leadframe with die attach pad with folded edge
KR101391925B1 (ko) * 2007-02-28 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형
KR101489325B1 (ko) * 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
US7659531B2 (en) * 2007-04-13 2010-02-09 Fairchild Semiconductor Corporation Optical coupler package
US7683463B2 (en) * 2007-04-19 2010-03-23 Fairchild Semiconductor Corporation Etched leadframe structure including recesses
US7902657B2 (en) * 2007-08-28 2011-03-08 Fairchild Semiconductor Corporation Self locking and aligning clip structure for semiconductor die package
US7737548B2 (en) 2007-08-29 2010-06-15 Fairchild Semiconductor Corporation Semiconductor die package including heat sinks
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US20090140266A1 (en) * 2007-11-30 2009-06-04 Yong Liu Package including oriented devices
US7589338B2 (en) * 2007-11-30 2009-09-15 Fairchild Semiconductor Corporation Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice
KR20090062612A (ko) * 2007-12-13 2009-06-17 페어차일드코리아반도체 주식회사 멀티 칩 패키지
US7781872B2 (en) * 2007-12-19 2010-08-24 Fairchild Semiconductor Corporation Package with multiple dies
US8426960B2 (en) * 2007-12-21 2013-04-23 Alpha & Omega Semiconductor, Inc. Wafer level chip scale packaging
US7791084B2 (en) 2008-01-09 2010-09-07 Fairchild Semiconductor Corporation Package with overlapping devices
US8106406B2 (en) 2008-01-09 2012-01-31 Fairchild Semiconductor Corporation Die package including substrate with molded device
US7626249B2 (en) * 2008-01-10 2009-12-01 Fairchild Semiconductor Corporation Flex clip connector for semiconductor device
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US20090194857A1 (en) * 2008-02-01 2009-08-06 Yong Liu Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
KR101524545B1 (ko) * 2008-02-28 2015-06-01 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
US7768108B2 (en) 2008-03-12 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die package including embedded flip chip
US8018054B2 (en) * 2008-03-12 2011-09-13 Fairchild Semiconductor Corporation Semiconductor die package including multiple semiconductor dice
KR101519062B1 (ko) * 2008-03-31 2015-05-11 페어차일드코리아반도체 주식회사 반도체 소자 패키지
US20090256245A1 (en) * 2008-04-14 2009-10-15 Yong Liu Stacked Micro-Module Packages, Systems Using the Same, and Methods of Making the Same
US20090278241A1 (en) * 2008-05-08 2009-11-12 Yong Liu Semiconductor die package including die stacked on premolded substrate including die
US20090315163A1 (en) * 2008-06-20 2009-12-24 Terry Johnson Semiconductor Die Packages with Stacked Flexible Modules Having Passive Components, Systems Using the Same, and Methods of Making the Same
US7745244B2 (en) 2008-06-23 2010-06-29 Fairchild Semiconductor Corporation Pin substrate and package
US8373257B2 (en) * 2008-09-25 2013-02-12 Alpha & Omega Semiconductor Incorporated Top exposed clip with window array
US8193618B2 (en) 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US7851856B2 (en) * 2008-12-29 2010-12-14 Alpha & Omega Semiconductor, Ltd True CSP power MOSFET based on bottom-source LDMOS
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
US7973393B2 (en) 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
US8222718B2 (en) * 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same
US20100289129A1 (en) * 2009-05-14 2010-11-18 Satya Chinnusamy Copper plate bonding for high performance semiconductor packaging
US8222078B2 (en) 2009-07-22 2012-07-17 Alpha And Omega Semiconductor Incorporated Chip scale surface mounted semiconductor device package and process of manufacture
US8362606B2 (en) 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
US8421204B2 (en) 2011-05-18 2013-04-16 Fairchild Semiconductor Corporation Embedded semiconductor power modules and packages
US8803297B2 (en) * 2012-08-10 2014-08-12 Infineon Technologies Ag Semiconductor device including a stress relief layer and method of manufacturing
DE102014204722A1 (de) * 2014-03-14 2015-09-17 Robert Bosch Gmbh Elektronisches Modul sowie Verfahren und Vorrichtung zum Herstellen eines elektronischen Moduls
CN105118817B (zh) * 2015-09-10 2017-09-19 江阴长电先进封装有限公司 一种低成本的硅基模块的封装结构及其封装方法
US11862983B1 (en) 2019-03-28 2024-01-02 Roger W. Graham Earth energy systems and devices
US11393743B2 (en) 2019-12-18 2022-07-19 Infineon Technologies Ag Semiconductor assembly with conductive frame for I/O standoff and thermal dissipation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517051A (en) * 1982-12-27 1985-05-14 Ibm Corporation Multi-layer flexible film module
US5159535A (en) * 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5777386A (en) * 1995-08-23 1998-07-07 Shinko Electric Industries Co., Ltd. Semiconductor device and mount structure thereof

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5974653A (ja) * 1982-10-22 1984-04-27 Hitachi Ltd 半導体装置
JPS63104435A (ja) 1986-10-22 1988-05-09 Hitachi Ltd 半導体装置
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package
JP3348562B2 (ja) 1995-04-05 2002-11-20 ソニー株式会社 半導体パッケージの実装構造
US5789809A (en) 1995-08-22 1998-08-04 National Semiconductor Corporation Thermally enhanced micro-ball grid array package
US5637916A (en) 1996-02-02 1997-06-10 National Semiconductor Corporation Carrier based IC packaging arrangement
JPH10284544A (ja) * 1997-04-10 1998-10-23 Hitachi Ltd 半導体装置およびその製造方法
US6023094A (en) 1998-01-14 2000-02-08 National Semiconductor Corporation Semiconductor wafer having a bottom surface protective coating
JPH11238828A (ja) 1998-02-20 1999-08-31 Toshiba Corp Ｂｇａ型パッケージの半導体装置およびその製造方法、実装装置
US6049624A (en) * 1998-02-20 2000-04-11 Micron Technology, Inc. Non-lot based method for assembling integrated circuit devices
US6137164A (en) * 1998-03-16 2000-10-24 Texas Instruments Incorporated Thin stacked integrated circuit device
EP0966038A3 (en) * 1998-06-15 2001-02-28 Ford Motor Company Bonding of semiconductor power devices
US6226699B1 (en) * 1998-06-25 2001-05-01 Compaq Computer Corporation Method and apparatus for clock selection and switching
US6225699B1 (en) * 1998-06-26 2001-05-01 International Business Machines Corporation Chip-on-chip interconnections of varied characteristics
US6084308A (en) 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6051887A (en) * 1998-08-28 2000-04-18 Medtronic, Inc. Semiconductor stacked device for implantable medical apparatus
JP2000077563A (ja) 1998-08-31 2000-03-14 Sharp Corp 半導体装置およびその製造方法
JP2000077591A (ja) * 1998-09-02 2000-03-14 Sanken Electric Co Ltd 半導体装置及びその組立方法
JP2000114413A (ja) * 1998-09-29 2000-04-21 Sony Corp 半導体装置、その製造方法および部品の実装方法
CA2366318A1 (en) * 1999-03-03 2000-09-08 Ida Royalty Aps Novel pharmaceutical, dietary and cosmetic compositions comprising zinger officinale roscoe, eicosapentaenoic acid and/or docosahexaenoic acid
US6255143B1 (en) * 1999-08-04 2001-07-03 St. Assembly Test Services Pte Ltd. Flip chip thermally enhanced ball grid array
US6720642B1 (en) 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6462421B1 (en) * 2000-04-10 2002-10-08 Advanced Semicondcutor Engineering, Inc. Multichip module
US6661082B1 (en) 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
US6798044B2 (en) 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6753605B2 (en) 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6469384B2 (en) 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6683375B2 (en) 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6724083B2 (en) * 2001-07-16 2004-04-20 Ars Electronics Co., Ltd. Method of producing semiconductor packages by cutting via holes into half when separating substrate
US6633030B2 (en) 2001-08-31 2003-10-14 Fiarchild Semiconductor Surface mountable optocoupler package
US6458695B1 (en) * 2001-10-18 2002-10-01 Chartered Semiconductor Manufacturing Ltd. Methods to form dual metal gates by incorporating metals and their conductive oxides
US6891256B2 (en) 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6566749B1 (en) 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
US6620635B2 (en) * 2002-02-20 2003-09-16 International Business Machines Corporation Damascene resistor and method for measuring the width of same
DE10392377T5 (de) 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
US6836023B2 (en) 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4517051A (en) * 1982-12-27 1985-05-14 Ibm Corporation Multi-layer flexible film module
US5159535A (en) * 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5777386A (en) * 1995-08-23 1998-07-07 Shinko Electric Industries Co., Ltd. Semiconductor device and mount structure thereof

Also Published As

Publication number Publication date
CN1489788A (zh) 2004-04-14
JP4729244B2 (ja) 2011-07-20
DE10295972T5 (de) 2004-04-15
WO2002061832A1 (en) 2002-08-08
CN101154607A (zh) 2008-04-02
US6469384B2 (en) 2002-10-22
US6740541B2 (en) 2004-05-25
US20040164386A1 (en) 2004-08-26
DE10295972B4 (de) 2013-05-16
US20050280161A1 (en) 2005-12-22
TW535243B (en) 2003-06-01
JP2009124176A (ja) 2009-06-04
JP2004521493A (ja) 2004-07-15
CN100576483C (zh) 2009-12-30
US20020100962A1 (en) 2002-08-01
US20030011005A1 (en) 2003-01-16
US6953998B2 (en) 2005-10-11
US7393718B2 (en) 2008-07-01

Similar Documents

Publication Publication Date Title
CN100352047C (zh) 用于半导体器件的非铸模封装
CN100466235C (zh) 包括两个设置在公用夹具中的半导体管芯的半导体封装
US6956741B2 (en) Semiconductor package with heat sink
US7595551B2 (en) Semiconductor package for a large die
US9006870B2 (en) Stacked multi-chip packaging structure and manufacturing method thereof
CN1065662C (zh) 半导体芯片封装及其制造方法
KR101167742B1 (ko) 집적화된 트랜지스터모듈 및 그 제조방법
CN100378972C (zh) 散热器及使用该散热器的封装体
JP4195380B2 (ja) 冷却を改善した半導体デバイスのパッケージ
US7701054B2 (en) Power semiconductor module and method for its manufacture
CN102576702B (zh) 具有嵌入式衬底及引线框的模块封装
CN101258609B (zh) 使用配置于层积板上导线的垂直电子组件封装结构
CN1711639B (zh) 折叠的柔性无接合引线的多芯片功率封装
EP3310140A1 (en) Mounting assembly with a heatsink
JPH07335783A (ja) 半導体装置及び半導体装置ユニット
CN103946976A (zh) 具有翻转式球接合表面的双层级引线框架及装置封装
CN1458691A (zh) 形成多引线框半导体器件的结构和方法
EP1137066A3 (en) Semiconductor device and process of production of same
JP2005506691A5 (zh)
US20080136015A1 (en) High power semiconductor device
JP2010141295A (ja) 基板上シュリンクパッケージ
CN101091247B (zh) 双扁平无引脚半导体封装
CN100463152C (zh) 制造一种直接芯片连接装置及结构的方法
CN207966971U (zh) 用于半导体封装结构的万用转接电路层
RU82379U1 (ru) Устройство семейства корпусов по размерам кристалла интегральных микросхем

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20071128

Termination date: 20150117

EXPY Termination of patent right or utility model