CN100351863C - 用于制造微电路板的方法 - Google Patents

用于制造微电路板的方法 Download PDF

Info

Publication number
CN100351863C
CN100351863C CNB028254457A CN02825445A CN100351863C CN 100351863 C CN100351863 C CN 100351863C CN B028254457 A CNB028254457 A CN B028254457A CN 02825445 A CN02825445 A CN 02825445A CN 100351863 C CN100351863 C CN 100351863C
Authority
CN
China
Prior art keywords
cavity
plate body
module
resin
microcircuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB028254457A
Other languages
English (en)
Other versions
CN1606805A (zh
Inventor
弗朗索瓦·洛奈
热罗姆·布瓦尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idemia France SAS
Original Assignee
Oberthur Card Systems SA France
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oberthur Card Systems SA France filed Critical Oberthur Card Systems SA France
Publication of CN1606805A publication Critical patent/CN1606805A/zh
Application granted granted Critical
Publication of CN100351863C publication Critical patent/CN100351863C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • G06K19/07747Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073Special arrangements for circuits, e.g. for protecting identification code in memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及一种用于在板体内安装微电路模块以使板子在不受破坏下不可拆卸的方法。该方法在于在调整了树脂(30)对空腔(12)的腔壁的附着力,使得该附着力显著大于树脂(30)对模块(22)的附着力之后,用树脂将模块(22)固定在板体(11)的空腔(12)内。

Description

用于制造微电路板的方法
技术领域
本发明涉及一种用于制造微电路板的方法,微电路板包括支持板和携带该微电路的模块,该模块被安装于所述支持板内的开放式空腔中。本发明一个更特别的目的是防止一种欺诈行为,包括不影响功能地拆卸此类模块,以便将其移植到另一个支持板内。
背景技术
所有技术领域内微电路板的研制经常遇到安全标准问题。这些标准之一是任何试图把模块从支持板拔出必须导致失败,即破坏该微电路和/或其连接的事实。需要在此领域内取得进展的认识很强烈,尤其是自生产微电路身份证得到正视以后。
安装于支持板内空腔中的模块包括形成印刷电路并在一面携带该微电路的支持薄膜。在当前使用的大部分技术中拆卸该模块而不破坏它是可能的。这是因为该模块通常附着在开放一侧和空腔底部之间确定的外围平面上,该微电路,通常有涂层,被装入空腔本身。在空腔的边缘和模块的边缘之间插入一个工具以卸下该模块相对比较容易。如果小心操作,分离不会导致破坏微电路和/或其连接。已有建议加入一滴粘合剂以接合空腔底部与微电路的涂层。然而,如果能够在涂层的树脂和粘合剂之间插入一个工具则仍然可能拆卸。由本申请人提出的另一项技术在于将保护微电路的树脂淀积到空腔自身并在树脂聚合之前将微电路涂以该树脂。这项技术使该模块更加难以拆卸但结果难以控制,因为它们在很大程度上依赖于树脂与空腔壁,特别是与其底部的附着力。本发明的目的是改进这项技术。
发明内容
本发明更特别地涉及一种用于制造微电路板的方法,微电路板包括板体和模块,该模块包括形成一个在其一个表面上携带所述微电路的印刷电路的支持薄膜,其中所述模块通过树脂至少部分填充所述空腔并环绕所述微电路被固定到所述板体内的空腔中,其特征在于使树脂与空腔壁的附着力增大,使得该附着力显著大于树脂与所述模块的支持薄膜的附着力。
树脂的附着力可通过对空腔壁,更特别地通过对其底部作适当表面处理而改变。这种表面处理反映在粗糙度的增加和/或处理后表面的化学改变,非常显著地增强了树脂与处理后表面的附着力,特别是使之比同样的树脂与该模块的支持薄膜的附着力强很多。这样的结果是,如果欺诈人企图通过插入一个工具到空腔边缘和模块边缘之间来卸下模块,所施加的力最多导致从树脂上扯开支持薄膜,而微电路及其连接线仍然嵌入在附着于空腔的树脂中。因此,以这种方式拆卸的模块变得不能使用。
这种类型的表面处理的成功特别依赖于控制表面处理装置的设置。
然而矛盾的是,在研制本发明的环境中,已经显示最好由具有较低表面能(典型地低于45mN/m)的塑料制造板体,即与树脂,甚至与用于固定模块到空腔外围的粘合剂具有固有的较弱附着力的材料,通常被用于组成空腔底部内的涂层。这是因为,从这种具有固有低表面能的材料开始,在表面处理装置的设置参数和表面处理后获得的附着力之间获得一个更好的相互关联。此外,如后面的解释,已知具有低表面能的材料,以及出于这种原因在微电路板领域直到现在还使用相对较少的材料,也具有最好的机械强度和热特性,这能提供微电路板预期的更长使用期限。
作为非受限的例子,可制造板体使得至少空腔的底部由聚对苯二甲酸乙二醇酯(PET),聚碳酸酯或聚对苯二甲酸丁烯酯(PBT)组成。没有必要整个板体由这种材料制造。例如,如果是通过层压多层塑料或可能的不同材料制造板体,则应满足空腔底部深度的涂层为低表面能的塑料,例如上面提及的材料中的一种。如果是PET的情形,则尤其可使用聚对苯二甲酸乙二醇酯薄膜(PETF)。
如果是以这种方式,即通过层压多层薄膜制造板体,则可在层压后通过加工到所述板体的厚度制造空腔,注意这个操作要达到正确的深度以暴露出低表面能的塑料,以便塑料形成空腔的底部。当然,机械加工可在一个整块板体,即一个由低表面能塑料的固体块制造的板体上完成。另一种可能是模压板体,在此情况下空腔可在模压期间形成。由于表面能低,选择塑料用于模压过程,而且塑料是例如上面指出的材料中的一种。
表面处理可包括产生处理表面的机械和/或化学改变的激光束处理。使用YAG激光束发生器或CO2激光束发生器可获得较好结果。
处理可以是通过暴露于紫外线使底面发生化学改变,例如借助于一盏灯,它可能与使用紫外频带内发射的受激准分子激光束发生器的激光处理有关。受激准分子激光器,特别是氩-氟和氙-氯激光器,可用于此目的。
空腔的表面状态也可通过利用特殊气体的等离子体处理或在露天(电晕处理)改变。这种类型的处理反映在表面的化学改变。
激光处理具有结合化学改变与生成促进树脂附着力增强的微小空腔的优点。
上面指出的处理装置的操作参数可精确调整以控制塑料,更特别地是控制较低表面能的塑料的表面状态的改变。
在上面提到的调整表面状态的操作之后,通过淀积所需数量的树脂到以这种方式处理的空腔底部上,以及在空腔内放置该模块以便其微电路被液体树脂环绕的现有技术已知方式结束本方法。树脂接着被聚合。根据所使用树脂的类型,聚合可在安装了模块之后通过热处理或通过紫外线照射继之以热处理获得。用于固定模块到空腔外围平面的粘合剂可以是冷粘合剂或热激活粘合剂。在聚合之后,树脂粘附到模块内表面以及粘附到处理后的空腔内表面。然而,树脂与模块的附着力比同样的树脂与空腔底部的附着力要小得多。这导致在试图拔出模块时破坏模块。
在本发明的一个方面,提供了一种用于制造包括板体和模块的微电路板的方法,所述模块包括支持薄膜,其形成在其一个表面上携带所述微电路的印刷电路,其中所述模块借助于树脂至少部分填充所述板体内的空腔以及环绕所述微电路而被固定到所述空腔中,其特征在于,所述空腔的至少一部分的表面状态被改变以增大所述树脂与处理后的表面的附着力,使得该附着力显著大于所述树脂与所述模块的支持薄膜的附着力。
附图说明
根据下面对通过举例给出的符合本发明的方法的一个实施例的描述以及参照附图将更好地理解本发明,而且其其他的优点将更为明显,其中:
-图1是示意板体和空腔的制造框图;
-图1a示意了图1步骤的一种变型;
-图2示意了空腔底部的表面处理;
-图3示意了插入微电路模块到空腔中;
-图4示意了加工完毕的板;以及
-图5示意了在欺诈人试图拔出模块时模块被破坏。
具体实施方式
本发明的方法包括图1至5显示的连续操作。在图1中,板体11由具有低表面能的塑料形成。在这个例子中,板体被模压而且在模压操作期间根据铸模14的其中一个部件的特殊外形形成空腔12。如图1a中所示,如果从塑料薄板切掉板体11a,则空腔12可通过机械加工形成。如前面指出,如果板体是通过层压多层不同塑料的薄膜制造,则位于最大加工深度的薄膜为低表面能塑料,原因是构成空腔底部的这种薄膜必须经历所设想的处理。
图2图解描述了这些表面处理中的一种,也就是至少暴露空腔12的底部16到由发生器19,例如YAG发生器,产生的激光束18中。在所示出的该例子中,空腔包括在其上支撑有该模块边缘的外围平面20。该外围平面可能经受同样的处理。
图3示意了由形成确定金属连接盘24、25的印刷电路的支持薄膜23组成的标准模块22。微电路26被粘附到印刷电路的另一面上。其输入-输出由导线28连接到印刷电路的各个连接盘。热激活粘合剂29被淀积在携带了微电路26的支持薄膜23的表面外围。预定数量的树脂也淀积在空腔内而且模块22被安置在空腔内以便微电路被静止液体树脂环绕。粘合剂29保持在空腔的外围平面20上。当以该方式安装模块时,静止液体树脂基本上填充所有的空腔或至少是空腔的大部分。树脂特别地接触微电路周围的支持薄膜23的内表面。树脂环绕着微电路。这种情形在图4中描述。当树脂被聚合时,模块完全附着到板体11上。在进行欺诈的尝试时,覆盖微电路26的树脂30及其连接线28保持粘附在空腔底部,而一方面从树脂另一方面从电连接盘25分离模块的支持薄膜23,都会导致连接线28和微电路26的分离。模块因此变得不可用并不能被安装于另一个板体内。

Claims (19)

1.一种用于制造包括板体(11)和模块(22)的微电路板的方法,所述模块包括支持薄膜(23),其形成在其一个表面上携带所述微电路(26)的印刷电路,其中所述模块借助于树脂至少部分填充所述板体内的空腔(12)以及环绕所述微电路而被固定到所述空腔(12)中,其特征在于,所述空腔的至少一部分的表面状态被改变以增大所述树脂(30)与处理后的表面的附着力,使得该附着力显著大于所述树脂(30)与所述模块的支持薄膜(23)的附着力。
2.根据权利要求1的方法,其特征在于,所述板体(11)由低表面能的塑料制成,以及所述空腔(12)的至少一部分的表面状态被改变以增大所述树脂与处理后的表面的附着力。
3.根据权利要求2的方法,其特征在于,制造所述板体(11)使得至少所述空腔(12)的底部由聚对苯二甲酸乙二醇酯组成。
4.根据权利要求2的方法,其特征在于,制造所述板体(11)使得至少所述空腔(12)的底部由聚碳酸酯组成。
5.根据权利要求2的方法,其特征在于,制造所述板体(11)使得至少所述空腔(12)的底部由聚对苯二甲酸丁烯酯组成。
6.根据权利要求2-5任一项的方法,其特征在于,通过层压多层塑料制造所述板体(11),而且形成空腔底部的层由低表面能的塑料组成。
7.根据权利要求1的方法,其特征在于,以一种本身已知的方式,通过加工至所述板体的厚度来形成所述空腔(12)。
8.根据权利要求1的方法,其特征在于,通过模压制造所述板体(11),所述空腔(12)在所述模压期间形成。
9.根据权利要求2的方法,其特征在于,通过产生处理后表面的机械和/或化学改变的激光处理(18)来改变空腔的表面状态。
10.根据权利要求9的方法,其特征在于,所述激光处理通过YAG激光束发生器(19)实现。
11.根据权利要求9的方法,其特征在于,所述激光处理通过受激准分子激光束发生器实现。
12.根据权利要求2的方法,其特征在于,通过气体等离子体处理来改变表面状态。
13.根据权利要求2的方法,其特征在于,通过电晕处理来改变表面状态。
14.根据权利要求2的方法,其特征在于,通过紫外线处理来改变表面状态。
15.根据权利要求2的方法,其特征在于,在表面状态改变操作之后,所需数量的树脂(30)被淀积到所述空腔底部,所述模块(22)被放置在所述空腔内使得其微电路(26)被液体树脂环绕,以及聚合所述树脂。
16.根据权利要求1的方法,其特征在于,所述空腔(12)是开放的。
17.根据权利要求16的方法,其特征在于,所述模块(22)被粘到在所述空腔(12)的底部和开放侧之间所确定的外围平面上。
18.根据权利要求1的方法,其特征在于,所述微电路(26)被电连接或连接到印刷电路的连接盘(24,25)。
19.根据权利要求18的方法,其特征在于,所述微电路(26)被粘附到所述印刷电路的与所述连接盘(24,25)相对的一面上。
CNB028254457A 2001-12-19 2002-12-18 用于制造微电路板的方法 Expired - Lifetime CN100351863C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR01/16483 2001-12-19
FR0116483A FR2833801B1 (fr) 2001-12-19 2001-12-19 Procede de realisation d'une carte a microcircuit

Publications (2)

Publication Number Publication Date
CN1606805A CN1606805A (zh) 2005-04-13
CN100351863C true CN100351863C (zh) 2007-11-28

Family

ID=8870702

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028254457A Expired - Lifetime CN100351863C (zh) 2001-12-19 2002-12-18 用于制造微电路板的方法

Country Status (9)

Country Link
US (1) US7584537B2 (zh)
EP (1) EP1464083A2 (zh)
JP (1) JP4327600B2 (zh)
CN (1) CN100351863C (zh)
AU (1) AU2002365005A1 (zh)
CA (1) CA2470229C (zh)
FR (1) FR2833801B1 (zh)
MX (1) MXPA04006036A (zh)
WO (1) WO2003052822A2 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100566507C (zh) * 2003-10-15 2009-12-02 皇家飞利浦电子股份有限公司 电子设备及其制造方法
FR2861201B1 (fr) 2003-10-17 2006-01-27 Oberthur Card Syst Sa Procede de fabrication d'une carte a double interface, et carte a microcircuit ainsi obtenue.
FR2862410B1 (fr) * 2003-11-18 2006-03-10 Oberthur Card Syst Sa Carte a microcircuit a fond marque d'un motif et procede pour sa realisation
JP4867150B2 (ja) * 2004-09-30 2012-02-01 凸版印刷株式会社 クリーニング用icタグの製造方法
JP2007079632A (ja) * 2005-09-09 2007-03-29 Lintec Corp 非接触icカード及びその非接触icカード用の平板状カード基板
US20080179404A1 (en) * 2006-09-26 2008-07-31 Advanced Microelectronic And Automation Technology Ltd. Methods and apparatuses to produce inlays with transponders
JP2008084040A (ja) * 2006-09-28 2008-04-10 Dainippon Printing Co Ltd Icカードのicモジュール装着方法
US8987632B2 (en) * 2009-10-09 2015-03-24 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Modification of surface energy via direct laser ablative surface patterning
DE102010011517A1 (de) * 2010-03-15 2011-09-15 Smartrac Ip B.V. Laminataufbau für eine Chipkarte und Verfahren zu dessen Herstellung
KR101427283B1 (ko) 2013-06-10 2014-08-07 옴니시스템 주식회사 플라스틱 카드의 제조방법 및 그 방법에 의해 제조된 금속 메탈층을 포함한 플라스틱 카드
DE102017213080A1 (de) 2017-07-28 2019-01-31 Robert Bosch Gmbh Verfahren zum Integrieren einer elektrischen Schaltung in eine Vorrichtung und Vorrichtung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5026452A (en) * 1986-12-11 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Method of producing IC cards
EP1050844A1 (fr) * 1999-05-06 2000-11-08 Oberthur Card Systems Sa Procédé de fabrication d'une carte à microcircuit
JP2001014442A (ja) * 1999-06-29 2001-01-19 Miyota Kk Icタグ構造
US6241153B1 (en) * 1998-03-17 2001-06-05 Cardxx, Inc. Method for making tamper-preventing, contact-type, smart cards

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68923686T2 (de) * 1988-04-20 1996-01-25 Matsushita Electric Ind Co Ltd Halbleiterkarte und verfahren zur herstellung.
DE4122049A1 (de) * 1991-07-03 1993-01-07 Gao Ges Automation Org Verfahren zum einbau eines traegerelements
DE69512137T2 (de) * 1994-06-15 2000-05-25 De La Rue Cartes Et Systemes, Paris Herstellungsverfahren und Montage für IC-Karte.
CN1054573C (zh) * 1994-09-22 2000-07-19 罗姆股份有限公司 非接触型ic卡及其制造方法
FR2736740A1 (fr) * 1995-07-11 1997-01-17 Trt Telecom Radio Electr Procede de production et d'assemblage de carte a circuit integre et carte ainsi obtenue
JPH0948190A (ja) 1995-08-04 1997-02-18 Dainippon Printing Co Ltd Icモジュールのカードに対する接着方法及びicカード
US5817207A (en) * 1995-10-17 1998-10-06 Leighton; Keith R. Radio frequency identification card and hot lamination process for the manufacture of radio frequency identification cards
JP2000090226A (ja) 1998-09-08 2000-03-31 Dainippon Printing Co Ltd Icモジュールの製造方法およびicカードの製造方法
FR2793330B1 (fr) * 1999-05-06 2001-08-10 Oberthur Card Systems Sas Procede de montage d'un microcircuit dans une cavite d'une carte formant support et carte ainsi obtenue

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5026452A (en) * 1986-12-11 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Method of producing IC cards
US6241153B1 (en) * 1998-03-17 2001-06-05 Cardxx, Inc. Method for making tamper-preventing, contact-type, smart cards
EP1050844A1 (fr) * 1999-05-06 2000-11-08 Oberthur Card Systems Sa Procédé de fabrication d'une carte à microcircuit
JP2001014442A (ja) * 1999-06-29 2001-01-19 Miyota Kk Icタグ構造

Also Published As

Publication number Publication date
EP1464083A2 (fr) 2004-10-06
AU2002365005A8 (en) 2003-06-30
JP4327600B2 (ja) 2009-09-09
CA2470229A1 (fr) 2003-06-26
MXPA04006036A (es) 2005-03-31
WO2003052822A3 (fr) 2004-01-22
FR2833801B1 (fr) 2005-07-01
AU2002365005A1 (en) 2003-06-30
US7584537B2 (en) 2009-09-08
FR2833801A1 (fr) 2003-06-20
WO2003052822A2 (fr) 2003-06-26
CN1606805A (zh) 2005-04-13
US20050223550A1 (en) 2005-10-13
JP2005513637A (ja) 2005-05-12
CA2470229C (fr) 2012-02-14

Similar Documents

Publication Publication Date Title
CN100351863C (zh) 用于制造微电路板的方法
TWI463930B (zh) 電路基板及在電路基板安裝有元件之半導體裝置
EP0790123A3 (en) Patterned metal foil laminate and method for making same
FR2788455B1 (fr) Procede de traitement d'une bande mince metallique fragile et pieces magnetiques realisees a partir d'une bande en alliage nanocristallin
US5318855A (en) Electronic assembly with flexible film cover for providing electrical and environmental protection
CZ300550B6 (cs) Zpusob výroby vícevrstvé desky s tištenými spoji a kompozitní fólie pro použití pri tomto zpusobu
TWI451820B (zh) 電路基板及其製造方法
CN102307437B (zh) 提高半加成工艺中积层基材与积层导体层的结合力的方法
KR20060041609A (ko) 금속화 폴리이미드필름 및 그 제조방법
EP0672334B1 (en) Process for production of printed circuit boards and use thereby
JP2000332387A (ja) プリント配線基板の製造方法
EP2367405A1 (en) Method for manufacturing circuit board, and circuit board obtained using the manufacturing method
EP0687405A1 (en) Drum-side treated metal foil and laminate for use in printed circuit boards and methods of manufacture
EP0949855A2 (en) Multilayer circuit board
CN112873355B (zh) 一种触控屏oca贴合对位靶标设计方法
KR20000057738A (ko) 비접촉 데이터 캐리어의 제조방법
CN108668464B (zh) 一种超薄软板与金属端子超声波焊接的方法及制品结构
US6652697B2 (en) Method for manufacturing a copper-clad laminate
US20240273328A1 (en) Method for producing a chip card body
CN1193650C (zh) 一种电路板封胶的制作方法
JPH0499088A (ja) 多層プリント配線板の製造方法
JPH09153682A (ja) 多層プリント基板の製造方法
JPH03262195A (ja) 複合多層プリント配線板の製造方法
KR101513292B1 (ko) 도체 패턴 형성방법
JPH04125115A (ja) 電磁シールド性樹脂外板の成形方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20071128