CH623685A5 - - Google Patents

Download PDF

Info

Publication number
CH623685A5
CH623685A5 CH1382977A CH1382977A CH623685A5 CH 623685 A5 CH623685 A5 CH 623685A5 CH 1382977 A CH1382977 A CH 1382977A CH 1382977 A CH1382977 A CH 1382977A CH 623685 A5 CH623685 A5 CH 623685A5
Authority
CH
Switzerland
Prior art keywords
silicon
arsenic
germanium
doped
substrate
Prior art date
Application number
CH1382977A
Other languages
German (de)
English (en)
Inventor
Siegfried Reinhard Mader
Burton Joseph Masters
Hans Bernhard Pogge
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH623685A5 publication Critical patent/CH623685A5/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/024Defect control-gettering and annealing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/061Gettering-armorphous layers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/938Lattice strain control or utilization

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
CH1382977A 1976-12-06 1977-11-14 CH623685A5 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/748,035 US4111719A (en) 1976-12-06 1976-12-06 Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium

Publications (1)

Publication Number Publication Date
CH623685A5 true CH623685A5 (fr) 1981-06-15

Family

ID=25007704

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1382977A CH623685A5 (fr) 1976-12-06 1977-11-14

Country Status (14)

Country Link
US (2) US4111719A (fr)
JP (1) JPS5370668A (fr)
AU (1) AU507591B2 (fr)
BE (1) BE860359A (fr)
BR (1) BR7707919A (fr)
CA (1) CA1075831A (fr)
CH (1) CH623685A5 (fr)
DE (1) DE2752439C3 (fr)
ES (1) ES464680A1 (fr)
FR (1) FR2379162A1 (fr)
GB (1) GB1536618A (fr)
IT (1) IT1113672B (fr)
NL (1) NL7713449A (fr)
SE (1) SE425529B (fr)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369072A (en) * 1981-01-22 1983-01-18 International Business Machines Corp. Method for forming IGFET devices having improved drain voltage characteristics
JPS5935425A (ja) * 1982-08-23 1984-02-27 Toshiba Corp 半導体装置の製造方法
GB2133618B (en) * 1983-01-05 1986-09-10 Gen Electric Co Plc Fabricating semiconductor circuits
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
US4928156A (en) * 1987-07-13 1990-05-22 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
US4837173A (en) * 1987-07-13 1989-06-06 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
JPH01220822A (ja) * 1988-02-29 1989-09-04 Mitsubishi Electric Corp 化合物半導体装置の製造方法
US4835112A (en) * 1988-03-08 1989-05-30 Motorola, Inc. CMOS salicide process using germanium implantation
US5097308A (en) * 1990-03-13 1992-03-17 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
US5298435A (en) * 1990-04-18 1994-03-29 National Semiconductor Corporation Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
US5095358A (en) * 1990-04-18 1992-03-10 National Semiconductor Corporation Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
US5316958A (en) * 1990-05-31 1994-05-31 International Business Machines Corporation Method of dopant enhancement in an epitaxial silicon layer by using germanium
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities
US5108954A (en) * 1991-09-23 1992-04-28 Micron Technology, Inc. Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method
US5420055A (en) * 1992-01-22 1995-05-30 Kopin Corporation Reduction of parasitic effects in floating body MOSFETs
US5426069A (en) * 1992-04-09 1995-06-20 Dalsa Inc. Method for making silicon-germanium devices using germanium implantation
KR0123434B1 (ko) * 1994-02-07 1997-11-26 천성순 실리콘 웨이퍼에서의 부정합전위의 발생을 억제화하기 위한 링패턴 형성방법 및 그 구조
JP3243146B2 (ja) * 1994-12-08 2002-01-07 株式会社東芝 半導体装置
JP2002504270A (ja) * 1998-04-09 2002-02-05 コーニンクレッカ、フィリップス、エレクトロニクス、エヌ、ヴィ 整流接合を有する半導体デバイスおよび該半導体デバイスの製造方法
US6030863A (en) * 1998-09-11 2000-02-29 Taiwan Semiconductor Manufacturing Company Germanium and arsenic double implanted pre-amorphization process for salicide technology
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US6114206A (en) * 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
GB9826519D0 (en) * 1998-12-02 1999-01-27 Arima Optoelectronics Corp Semiconductor devices
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US7253071B2 (en) * 2004-06-02 2007-08-07 Taiwan Semiconductor Manufacturing Company Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
WO2021163175A1 (fr) * 2020-02-11 2021-08-19 QROMIS, Inc. Procédé et système destinés à diffuser du magnésium dans des matériaux de nitrure de gallium au moyen de sources de magnésium pulvérisées

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL204025A (fr) * 1955-03-23
US3485684A (en) * 1967-03-30 1969-12-23 Trw Semiconductors Inc Dislocation enhancement control of silicon by introduction of large diameter atomic metals
US3836999A (en) * 1970-09-21 1974-09-17 Semiconductor Res Found Semiconductor with grown layer relieved in lattice strain
US3943016A (en) * 1970-12-07 1976-03-09 General Electric Company Gallium-phosphorus simultaneous diffusion process
NL161920C (nl) * 1971-03-12 1980-03-17 Hitachi Ltd Werkwijze voor het vervaardigen van een half- geleiderinrichting, waarbij de roostervervorming t.g.v. doteerstoffen wordt gecompenseerd.
JPS50116274A (fr) * 1974-02-27 1975-09-11

Also Published As

Publication number Publication date
US4111719A (en) 1978-09-05
CA1075831A (fr) 1980-04-15
AU3034977A (en) 1979-05-10
ES464680A1 (es) 1979-01-01
NL7713449A (nl) 1978-06-08
IT1113672B (it) 1986-01-20
SE7713736L (sv) 1978-06-07
GB1536618A (en) 1978-12-20
DE2752439C3 (de) 1981-01-29
BE860359A (fr) 1978-02-15
AU507591B2 (en) 1980-02-21
DE2752439A1 (de) 1978-06-08
DE2752439B2 (de) 1980-05-22
BR7707919A (pt) 1978-09-05
US4137103A (en) 1979-01-30
FR2379162B1 (fr) 1980-12-19
FR2379162A1 (fr) 1978-08-25
JPS5370668A (en) 1978-06-23
SE425529B (sv) 1982-10-04

Similar Documents

Publication Publication Date Title
CH623685A5 (fr)
EP0813753B1 (fr) Cellule solaire avec champ electrique arriere et procede de fabrication de ladite cellule
DE102006003283A1 (de) Verfahren zur Herstellung eines Halbleiterbauelements mit unterschiedlich stark dotierten Bereichen
DE2449688A1 (de) Verfahren zur herstellung einer dotierten zone eines leitfaehigkeitstyps in einem halbleiterkoerper sowie nach diesem verfahren hergestellter transistor
DE2845460A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE2650511A1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE1614540B2 (de) Halbleiteranordnung sowie verfahren zu seiner herstellung
EP0018520A1 (fr) Procédé d'élimination des défauts de réseau causés par l'implantation d'ions de phosphore dans des couches de type N de dispositifs semiconducteurs au silicium et dispositif obtenu
DE2615754C2 (fr)
DE2449012C2 (de) Verfahren zur Herstellung von dielektrisch isolierten Halbleiterbereichen
DE2655341A1 (de) Halbleiteranordnung mit passivierter oberflaeche und verfahren zur herstellung dieser anordnung
DE1444496A1 (de) Epitaxialer Wachstumsprozess
DE2718449A1 (de) Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte anordnung
DE2239686A1 (de) Verfahren zur herstellung von dielektrisch isolierten schichtbereichen aus einem siliciumhalbleitermaterial auf einer traegerschicht
DE1950069B2 (de) Verfahren zum Herstellung einer Halbleiteranordnung
DE2103468A1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE1259469B (de) Verfahren zur Herstellung von inversionsschichtfreien Halbleiteruebergaengen
DE2211709B2 (de) Verfahren zum Dotieren von Halbleitermaterial
DE2558925C2 (de) Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung
DE1964837B2 (de) Verfahren zur Herstellung einer lichtemittierenden Halbleiterdiode
DE2439535A1 (de) Verfahren zum eindiffundieren aktiver stoerelemente in halbleitermaterialien
DE1789204C2 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE2219696A1 (de) Verfahren zur Isolationsbereichsbildung
DE2506436B2 (de) Isolationsdiffusionsverfahren zum Herstellen aluminiumdotierter Isolationszonen für Halbleiterbauelemente
DE2048201A1 (de) Halbleitervorrichtung

Legal Events

Date Code Title Description
PL Patent ceased