ES464680A1 - Un metodo para formar regiones de tipo de conductividad n enun sustrato de silicio - Google Patents

Un metodo para formar regiones de tipo de conductividad n enun sustrato de silicio

Info

Publication number
ES464680A1
ES464680A1 ES464680A ES464680A ES464680A1 ES 464680 A1 ES464680 A1 ES 464680A1 ES 464680 A ES464680 A ES 464680A ES 464680 A ES464680 A ES 464680A ES 464680 A1 ES464680 A1 ES 464680A1
Authority
ES
Spain
Prior art keywords
arsenic
substrate
silicon
atoms
germanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES464680A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES464680A1 publication Critical patent/ES464680A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/061—Gettering-armorphous layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
  • Physical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)

Abstract

Un método para formar regiones de tipo de conductividad N en un sustrato de silicio, que comprende implantar iónicamente arsénico para formar en dicho sustrato una región que tiene una concentración de átomos de arsénico de al menos 1 x 10-2 átomos de As/átomos totales en el sustrato, e implantar iónicamente germanio en dicha región de sustrato.
ES464680A 1976-12-06 1977-12-02 Un metodo para formar regiones de tipo de conductividad n enun sustrato de silicio Expired ES464680A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/748,035 US4111719A (en) 1976-12-06 1976-12-06 Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium

Publications (1)

Publication Number Publication Date
ES464680A1 true ES464680A1 (es) 1979-01-01

Family

ID=25007704

Family Applications (1)

Application Number Title Priority Date Filing Date
ES464680A Expired ES464680A1 (es) 1976-12-06 1977-12-02 Un metodo para formar regiones de tipo de conductividad n enun sustrato de silicio

Country Status (14)

Country Link
US (2) US4111719A (es)
JP (1) JPS5370668A (es)
AU (1) AU507591B2 (es)
BE (1) BE860359A (es)
BR (1) BR7707919A (es)
CA (1) CA1075831A (es)
CH (1) CH623685A5 (es)
DE (1) DE2752439C3 (es)
ES (1) ES464680A1 (es)
FR (1) FR2379162A1 (es)
GB (1) GB1536618A (es)
IT (1) IT1113672B (es)
NL (1) NL7713449A (es)
SE (1) SE425529B (es)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369072A (en) * 1981-01-22 1983-01-18 International Business Machines Corp. Method for forming IGFET devices having improved drain voltage characteristics
JPS5935425A (ja) * 1982-08-23 1984-02-27 Toshiba Corp 半導体装置の製造方法
GB2133618B (en) * 1983-01-05 1986-09-10 Gen Electric Co Plc Fabricating semiconductor circuits
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4928156A (en) * 1987-07-13 1990-05-22 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
US4837173A (en) * 1987-07-13 1989-06-06 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
JPH01220822A (ja) * 1988-02-29 1989-09-04 Mitsubishi Electric Corp 化合物半導体装置の製造方法
US4835112A (en) * 1988-03-08 1989-05-30 Motorola, Inc. CMOS salicide process using germanium implantation
US5097308A (en) * 1990-03-13 1992-03-17 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
US5298435A (en) * 1990-04-18 1994-03-29 National Semiconductor Corporation Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
US5095358A (en) * 1990-04-18 1992-03-10 National Semiconductor Corporation Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
US5316958A (en) * 1990-05-31 1994-05-31 International Business Machines Corporation Method of dopant enhancement in an epitaxial silicon layer by using germanium
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5108935A (en) * 1990-11-16 1992-04-28 Texas Instruments Incorporated Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities
US5108954A (en) * 1991-09-23 1992-04-28 Micron Technology, Inc. Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method
US5420055A (en) * 1992-01-22 1995-05-30 Kopin Corporation Reduction of parasitic effects in floating body MOSFETs
US5426069A (en) * 1992-04-09 1995-06-20 Dalsa Inc. Method for making silicon-germanium devices using germanium implantation
KR0123434B1 (ko) * 1994-02-07 1997-11-26 천성순 실리콘 웨이퍼에서의 부정합전위의 발생을 억제화하기 위한 링패턴 형성방법 및 그 구조
JP3243146B2 (ja) * 1994-12-08 2002-01-07 株式会社東芝 半導体装置
EP1008187B1 (en) * 1998-04-09 2009-09-23 Nxp B.V. Semiconductor device having a rectifying junction and method of manufacturing same
US6030863A (en) * 1998-09-11 2000-02-29 Taiwan Semiconductor Manufacturing Company Germanium and arsenic double implanted pre-amorphization process for salicide technology
US6114206A (en) * 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
GB9826519D0 (en) * 1998-12-02 1999-01-27 Arima Optoelectronics Corp Semiconductor devices
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US7253071B2 (en) * 2004-06-02 2007-08-07 Taiwan Semiconductor Manufacturing Company Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
CN115088079A (zh) * 2020-02-11 2022-09-20 克罗米斯有限公司 使用溅射的镁源来扩散氮化镓材料中镁的方法和系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL204025A (es) * 1955-03-23
US3485684A (en) * 1967-03-30 1969-12-23 Trw Semiconductors Inc Dislocation enhancement control of silicon by introduction of large diameter atomic metals
US3836999A (en) * 1970-09-21 1974-09-17 Semiconductor Res Found Semiconductor with grown layer relieved in lattice strain
US3943016A (en) * 1970-12-07 1976-03-09 General Electric Company Gallium-phosphorus simultaneous diffusion process
DE2211709C3 (de) * 1971-03-12 1979-07-05 Hitachi, Ltd., Tokio Verfahren zum Dotieren von Halbleitermaterial
JPS50116274A (es) * 1974-02-27 1975-09-11

Also Published As

Publication number Publication date
CA1075831A (en) 1980-04-15
DE2752439A1 (de) 1978-06-08
JPS5370668A (en) 1978-06-23
AU507591B2 (en) 1980-02-21
SE425529B (sv) 1982-10-04
SE7713736L (sv) 1978-06-07
DE2752439B2 (de) 1980-05-22
FR2379162B1 (es) 1980-12-19
NL7713449A (nl) 1978-06-08
BE860359A (fr) 1978-02-15
BR7707919A (pt) 1978-09-05
CH623685A5 (es) 1981-06-15
DE2752439C3 (de) 1981-01-29
IT1113672B (it) 1986-01-20
GB1536618A (en) 1978-12-20
AU3034977A (en) 1979-05-10
US4111719A (en) 1978-09-05
FR2379162A1 (fr) 1978-08-25
US4137103A (en) 1979-01-30

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