JPS5688322A - Processing method for semiconductor substrate - Google Patents

Processing method for semiconductor substrate

Info

Publication number
JPS5688322A
JPS5688322A JP16592879A JP16592879A JPS5688322A JP S5688322 A JPS5688322 A JP S5688322A JP 16592879 A JP16592879 A JP 16592879A JP 16592879 A JP16592879 A JP 16592879A JP S5688322 A JPS5688322 A JP S5688322A
Authority
JP
Japan
Prior art keywords
gettering effect
ions
gettering
kinds
amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16592879A
Other languages
Japanese (ja)
Inventor
Hiroyuki Matsumoto
Junichi Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16592879A priority Critical patent/JPS5688322A/en
Publication of JPS5688322A publication Critical patent/JPS5688322A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Physical Vapour Deposition (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To enhance the gettering effect by implanting ions of at least two kinds of elements from the side opposite to the element forming surface of a substrate, thereafter performing gettering. CONSTITUTION:In the case B and P ions are implanted, the gettering effect does not increase by only increasing the amount of dose. The peak value of the gettering effect (life time) exists only in a specific range of dosing amount (i.e. specific mixing ratio of B and P). If the dosing amounts of B and P are set at 10<14>-10<15>cm<-3>, respectively, the peak is formed in the life time even though the individual dosing amount is relatively small, and the gettering effect is improved than in the case of single implantation of P. The lattice defects increase by the implantation of two kinds of the element ions, and the difference in the radii of the atoms of the implanted ions effectively acts. Therefore, the gettering effect is remarkably enhanced.
JP16592879A 1979-12-20 1979-12-20 Processing method for semiconductor substrate Pending JPS5688322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16592879A JPS5688322A (en) 1979-12-20 1979-12-20 Processing method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16592879A JPS5688322A (en) 1979-12-20 1979-12-20 Processing method for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS5688322A true JPS5688322A (en) 1981-07-17

Family

ID=15821667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16592879A Pending JPS5688322A (en) 1979-12-20 1979-12-20 Processing method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5688322A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111373A (en) * 1982-12-16 1984-06-27 Matsushita Electric Ind Co Ltd Compound semiconductor substrate and manufacture thereof
US5296385A (en) * 1991-12-31 1994-03-22 Texas Instruments Incorporated Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing
US6465873B1 (en) * 1997-08-21 2002-10-15 Micron Technology, Inc. Semiconductor gettering structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111373A (en) * 1982-12-16 1984-06-27 Matsushita Electric Ind Co Ltd Compound semiconductor substrate and manufacture thereof
US5296385A (en) * 1991-12-31 1994-03-22 Texas Instruments Incorporated Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing
US6465873B1 (en) * 1997-08-21 2002-10-15 Micron Technology, Inc. Semiconductor gettering structures

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