JPS6467911A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6467911A
JPS6467911A JP22462687A JP22462687A JPS6467911A JP S6467911 A JPS6467911 A JP S6467911A JP 22462687 A JP22462687 A JP 22462687A JP 22462687 A JP22462687 A JP 22462687A JP S6467911 A JPS6467911 A JP S6467911A
Authority
JP
Japan
Prior art keywords
oxide film
ion implantation
impurities
silicon substrate
thick oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22462687A
Other languages
Japanese (ja)
Other versions
JPH0760809B2 (en
Inventor
Shinken Okawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62224626A priority Critical patent/JPH0760809B2/en
Publication of JPS6467911A publication Critical patent/JPS6467911A/en
Publication of JPH0760809B2 publication Critical patent/JPH0760809B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To control thresholds of a MIS transistor and decrease the number of ion implantation as well, by introducing impurities not only into a part of a thin oxide film but also into a thick oxide film collectively after forming a thick oxide film at a semiconductor device having regions of element isolation and element formation. CONSTITUTION:A thin oxide film 2 is formed on the principal surface of a P-type silicon substrate 1 and a blocking material 8 is formed at a part where an element formation region is formed. Then, a thick oxide film 3 is formed at a part where the blocking material 8 is not formed. After that, the blocking material 8 is removed. And then, a layer having highly concentrated impurities is formed in the silicon substrate 1 by performing ion implantation 6. If ion implantation is carried out on condition that nearly 50% or more impurities which are implanted on the thick oxide film 3 reach into the silicon substrate 1, peak positions of impurity concentration are exhibited by an ion implantation locus 4. When the impurities are introduced by ion implantation 7 at shallow positions below thin oxide film 2, the peak positions of impurity concentration are exhibited by the ion implantation locus 5. In such a case, the impurities do not reach the silicon substrate 1 at the thick oxide film 3 and they are introduced only into the region of thin oxide film 2 selectively.
JP62224626A 1987-09-08 1987-09-08 Method for manufacturing semiconductor device Expired - Lifetime JPH0760809B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62224626A JPH0760809B2 (en) 1987-09-08 1987-09-08 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62224626A JPH0760809B2 (en) 1987-09-08 1987-09-08 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6467911A true JPS6467911A (en) 1989-03-14
JPH0760809B2 JPH0760809B2 (en) 1995-06-28

Family

ID=16816654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62224626A Expired - Lifetime JPH0760809B2 (en) 1987-09-08 1987-09-08 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0760809B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091324A (en) * 1990-08-10 1992-02-25 Advanced Micro Devices, Inc. Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures
US6451645B1 (en) 2000-07-12 2002-09-17 Denso Corp Method for manufacturing semiconductor device with power semiconductor element and diode

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
JPS5687340A (en) * 1979-12-19 1981-07-15 Fujitsu Ltd Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
JPS5687340A (en) * 1979-12-19 1981-07-15 Fujitsu Ltd Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091324A (en) * 1990-08-10 1992-02-25 Advanced Micro Devices, Inc. Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures
US6451645B1 (en) 2000-07-12 2002-09-17 Denso Corp Method for manufacturing semiconductor device with power semiconductor element and diode

Also Published As

Publication number Publication date
JPH0760809B2 (en) 1995-06-28

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