JPS6449268A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6449268A
JPS6449268A JP20673987A JP20673987A JPS6449268A JP S6449268 A JPS6449268 A JP S6449268A JP 20673987 A JP20673987 A JP 20673987A JP 20673987 A JP20673987 A JP 20673987A JP S6449268 A JPS6449268 A JP S6449268A
Authority
JP
Japan
Prior art keywords
ions
phosphorus
implanted
transistor
characteristic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20673987A
Other languages
Japanese (ja)
Inventor
Katsuya Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20673987A priority Critical patent/JPS6449268A/en
Publication of JPS6449268A publication Critical patent/JPS6449268A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve a characteristic of a transistor by a method wherein ions of silicon are implanted before an n<-> impurity region is formed and the upper part of a phosphorus-doped polysilicon gate electrode is made to be amorphous in order to prevent the channeling phenomenon of the ions of phosphorus. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed on a p<->-type silicon substrate 1; phosphorus-doped polysilicon is grown thereon. A gate electrode 4 is formed by a dry-etching operation. Ions of silicon are implanted at 100KeV; an amorphous layer 5 is formed on the electrode 4. Ions of phosphorus as n<-> impurities are implanted; n<-> impurity regions 6 are formed. By this setup, it is made possible to prevent a channeling phenomenon of the ions of phosphorus further; it is made possible to improve a characteristic of a transistor.
JP20673987A 1987-08-20 1987-08-20 Manufacture of semiconductor device Pending JPS6449268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20673987A JPS6449268A (en) 1987-08-20 1987-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20673987A JPS6449268A (en) 1987-08-20 1987-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6449268A true JPS6449268A (en) 1989-02-23

Family

ID=16528300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20673987A Pending JPS6449268A (en) 1987-08-20 1987-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6449268A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method

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