JPS6449269A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6449269A
JPS6449269A JP20674187A JP20674187A JPS6449269A JP S6449269 A JPS6449269 A JP S6449269A JP 20674187 A JP20674187 A JP 20674187A JP 20674187 A JP20674187 A JP 20674187A JP S6449269 A JPS6449269 A JP S6449269A
Authority
JP
Japan
Prior art keywords
ions
phosphorus
implanted
phosphorous
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20674187A
Other languages
Japanese (ja)
Inventor
Katsuya Ishikawa
Morio Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20674187A priority Critical patent/JPS6449269A/en
Publication of JPS6449269A publication Critical patent/JPS6449269A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the characteristic of a transistor by a method wherein ions of tin which are electrically neutral are implanted before an n<-> impurity is formed and an upper part of a phosphorus-doped polysilicon gate electrode is made to be amorphous in order to prevent a channeling phenomenon of ions of phosphorus. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed on a p-type silicon substrate 1; phosphorus-doped polysilicon is grown thereon. A gate electrode 4 is formed by a dry-etching operation. Ions of tin which are electrically neutral are implanted at 200KeV; an amorphous layer 5 is formed on the electrode 4. Ions of phosphorous as n<-> impurities are implanted; n<-> impurity regions 6 are formed. By this setup, it is made possible to prevent a channeling phenomenon of the ions of phosphorous; whereby the characteristic of a transistor can be improved.
JP20674187A 1987-08-20 1987-08-20 Manufacture of semiconductor device Pending JPS6449269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20674187A JPS6449269A (en) 1987-08-20 1987-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20674187A JPS6449269A (en) 1987-08-20 1987-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6449269A true JPS6449269A (en) 1989-02-23

Family

ID=16528333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20674187A Pending JPS6449269A (en) 1987-08-20 1987-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6449269A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method
JP2002217123A (en) * 2001-01-18 2002-08-02 Sony Corp Ion implantation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method
JP2002217123A (en) * 2001-01-18 2002-08-02 Sony Corp Ion implantation method

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