JPS59111373A - Compound semiconductor substrate and manufacture thereof - Google Patents
Compound semiconductor substrate and manufacture thereofInfo
- Publication number
- JPS59111373A JPS59111373A JP22145182A JP22145182A JPS59111373A JP S59111373 A JPS59111373 A JP S59111373A JP 22145182 A JP22145182 A JP 22145182A JP 22145182 A JP22145182 A JP 22145182A JP S59111373 A JPS59111373 A JP S59111373A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- semiconductor substrate
- layer
- fet
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 title claims abstract description 22
- 150000001875 compounds Chemical class 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 6
- 229910052796 boron Inorganic materials 0.000 claims abstract 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 150000002500 ions Chemical class 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 230000005669 field effect Effects 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract description 2
- -1 boron ions Chemical class 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 102200056507 rs104894175 Human genes 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は化合物半導体、例えばガリウム砒素（Ｇａ Ａ
ｓ ） を用いたショットキー障壁グート形電界効果
トランジヌタの製造等に用いられる化合物半導体基板に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to compound semiconductors, such as gallium arsenide (GaA
The present invention relates to a compound semiconductor substrate used for manufacturing a Schottky barrier-Goutt type field effect transistor, etc.
従来例の構成とその問題点
Ｇａ Ａｓショットキー障壁ゲート型電界効果トランジ
スタ（以下ＦＩＴと略称する）を構成素子とするＧａ
Ａｓ集積回路の製造を例にとって説明すると、半絶縁性
Ｇａ Ａｓ基板の所望の領域にイオン注入法を用いて選
択的にｎ型半導体層を形成し、素子の能動部としてｎ型
半導体層にソース、ドレインと称するオーミック電極と
ゲートと称するショットキ設けてＦＲＴが構成される。Conventional configuration and its problems Ga As Schottky barrier gate field effect transistor (hereinafter abbreviated as FIT) as a constituent element
Taking the manufacturing of an As integrated circuit as an example, an n-type semiconductor layer is selectively formed in a desired region of a semi-insulating GaAs substrate using ion implantation, and a source is added to the n-type semiconductor layer as the active part of the device. An FRT is constructed by providing an ohmic electrode called a drain and a Schottky called a gate.
Ｇａ Ａｓ集積回路に於ては構成素子であるＦＥＴの閾
値電圧（以下ＶＴと略称する）の均一化が最も重要で、
７丁の不均一のため、Ｇａ Ａｓ集積回路が動作しない
、動作してもＧａ Ａｓ集積回路の特徴である高速、低
消費電力化が達成できない等の不都合が生じる。ＶＴの
不均一化は半絶縁性Ｇａ Ａｓ基板にほとんど起用して
いる。即ち半絶縁性職人Ｓ基板が熱的に不安定で結晶欠
陥が多くかつ不均一のためである。In GaAs integrated circuits, the most important thing is to equalize the threshold voltage (hereinafter abbreviated as VT) of the FET which is a component.
Due to the non-uniformity of the 7 circuits, disadvantages arise, such as the GaAs integrated circuit not operating, or even if it does operate, the high speed and low power consumption that are the characteristics of the GaAs integrated circuit cannot be achieved. The non-uniformity of VT is mostly applied to semi-insulating GaAs substrates. That is, this is because the semi-insulating S substrate is thermally unstable, has many crystal defects, and is non-uniform.
発明の目的
本発明は上記の従来の問題に鑑み、均一な７丁を得るだ
めの化合物半導体基板を提供することを目的と、するも
のである。OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a compound semiconductor substrate capable of obtaining a uniform semiconductor substrate.
発明の構成
本発明の化合物半導体基板はポロンを含有する層を有す
るものである。また本発明の化合物半導体基板の製造方
法は化合物半導体基板にＢ（ポロン）をイオン注入して
Ｂ注入層を形成し、熱処理することによシ結晶欠陥、残
留不純物等をＢ注入層に集め、結晶欠陥、残留不純物の
減少した領域にｎ型半導体層を形成し、均一な７丁を得
ることを可能にするものである。Constitution of the Invention The compound semiconductor substrate of the present invention has a layer containing poron. Further, in the method for manufacturing a compound semiconductor substrate of the present invention, B (poron) is ion-implanted into a compound semiconductor substrate to form a B-implanted layer, and crystal defects, residual impurities, etc. are collected in the B-implanted layer by heat treatment. An n-type semiconductor layer is formed in a region where crystal defects and residual impurities are reduced, making it possible to obtain a uniform 7-layer structure.
実施例の説明
第１図は本発明の一実施例にかかるＦＥＴ （電界効果
トランジヌタ）の製造工程を示す図である。DESCRIPTION OF EMBODIMENTS FIG. 1 is a diagram showing a manufacturing process of an FET (field effect transistor) according to an embodiment of the present invention.
半絶縁性Ｇａ Ａｓ基板１にイオン注入法でポロンイオ
ン申）２を３５０ Ｋｅ Ｖ テ１０” Ｏｍ、、−２
注入シ、Ｂ注入層３を形成する（第１図（ａ））。砒素
雰囲気中で９００℃で３０分間熱熱処理、Ｂ含有層４を
形成する（第１図（ｂ））。シリコン窒化膜（Ｓ１３Ｎ
４膜）６をイオン注入のマヌクとして用い、シリコン（
Ｓｉ）イオン６を注入し、熱処理し、ｎ型半導体層７を
形成する（第１図（Ｃ））。ｎ型半導体層７にオーミッ
ク電極となるソース電極８、ドレイン電極９及びショッ
トキ接触となるゲート電極１゜を形成してＦＥＴを形成
する（第１図（ｄ））。Poron ions (2) were added to the semi-insulating GaAs substrate 1 by ion implantation at 350 Ke V te 10" Om, -2
Then, a B injection layer 3 is formed (FIG. 1(a)). Heat treatment is performed at 900° C. for 30 minutes in an arsenic atmosphere to form a B-containing layer 4 (FIG. 1(b)). Silicon nitride film (S13N
4 film) 6 as a manuk for ion implantation, silicon (
Si) ions 6 are implanted and heat treated to form an n-type semiconductor layer 7 (FIG. 1(C)). A source electrode 8 serving as an ohmic electrode, a drain electrode 9 and a gate electrode 1° serving as a Schottky contact are formed on the n-type semiconductor layer 7 to form an FET (FIG. 1(d)).
ＬＥＧ法（Ｌｉｑｕｉｄ Ｅｎｃａｐｓｕｌａｔｅｄ
Ｃｚｏｃｈｒａｌｓｋｉ ）によシ製造した面方位（１
００）の半絶縁性ＧａＡｓ基板を用い本発明の第１図に
示した方法及びＢ注大層を形成しない従来方法で形成し
たＦＩＣＴの７丁を測定した。デプレッション型Ｆ Ｅ
Ｔ （Ｄ−ＦＥＴ）。LEG method (Liquid Encapsulated
Czochralski)
Seven FICTs were measured using a semi-insulating GaAs substrate (00), which was formed by the method shown in FIG. Depression type F E
T (D-FET).
エンハンスメント型ＦＥＴ （Ｋ−ＦＥＴ）のｎ型半導
体層の形成条件としてＳｉのイオン注入の加速電圧とし
て１５０Ｋｅｙ、９ｏＫθＶで注入した。As conditions for forming an n-type semiconductor layer of an enhancement type FET (K-FET), Si ion implantation was performed at an acceleration voltage of 150 Key and 9oKθV.
次表に従来例と本発明のＶＴの平均値、標準偏差を示す
。The following table shows the average value and standard deviation of VT of the conventional example and the present invention.
表；ｖＴの平均値及び標準偏差
表から明らかな様に本発明を用いることによシ標準偏差
が減少し、従来方法に比−して７丁のバラツキが減少す
る。又相互コンダクタンス（！？ｍ）は本発明のＦＥＴ
は従来例に比してＤ−ＦＩＣＴで約１６％向上、Ｅ−Ｆ
ＩＣＴで約２５％向上した。Table: As is clear from the table of average values and standard deviations of vT, by using the present invention, the standard deviation is reduced, and the variation among the 7 guns is reduced compared to the conventional method. Also, the mutual conductance (!?m) of the FET of the present invention
is improved by about 16% with D-FICT compared to the conventional example, and E-F
ICT improved by about 25%.
本発明の半絶縁性Ｇａ Ａｓを用いることで、７丁のバ
ラツキが少なく、 μが向上する理由はけつきシしない
が、Ｂ注入領域が高濃度欠陥領域で、熱処理によｆｉＢ
注入領域に周囲の結晶欠陥、残留不純物が集まるいわゆ
るゲッタリング効果によるのではないかと考えられる。By using the semi-insulating GaAs of the present invention, there is less variation among the 7 pieces and μ is improved. The reason for this is not to be overstated, but the B implanted region is a high concentration defect region and the fiB is improved by heat treatment.
It is thought that this is due to the so-called gettering effect in which surrounding crystal defects and residual impurities gather in the implanted region.
又Ｂは電気的に中性でＧａ ＡＳ結晶中の格子結合Ｂ
−Ａｓの結合エネルギが格子結合（ｒａ −Ａｓの結合
エネルギよシも大きい 。Also, B is electrically neutral and the lattice bond B in the Ga AS crystal.
The binding energy of -As is larger than that of lattice bonding (ra).
ことも影響していると思われる。It seems that this also has an influence.
第２図〜第４図は本発明の他の実施例の模式的な構造断
面図を示し、第２図はｎ型半導体層７の側壁とＢ含有層
４が接した構造でありよシ効果的に半導体層７の結晶性
を良くすることができる。2 to 4 show schematic structural cross-sectional views of other embodiments of the present invention, and FIG. 2 shows a structure in which the side wall of the n-type semiconductor layer 7 and the B-containing layer 4 are in contact with each other. Therefore, the crystallinity of the semiconductor layer 7 can be improved.
第３図はｎ型半導体層７の底面、側壁とＢ含有層４が接
している構造である。第４図はｎ型半導体層の底面、側
壁の近傍にＢ含有層４が形成されている。FIG. 3 shows a structure in which the bottom and side walls of the n-type semiconductor layer 7 are in contact with the B-containing layer 4. In FIG. 4, a B-containing layer 4 is formed near the bottom and side walls of the n-type semiconductor layer.
なお実施例では化合物半導体として半絶縁性Ｇａ Ａｓ
について説明したが、ＩｎＰ、 ＧａＡｓＰ等の化合
物半導体に適用できることは勿論である。In the examples, semi-insulating GaAs was used as the compound semiconductor.
Although the present invention has been described above, it is of course applicable to compound semiconductors such as InP and GaAsP.
発明の効果
以上実施例で説明した様に、本発明の化合物半導体基板
およびその製造方法は、ポロンを含有する層を有する（
形成する）ものであるため、例えばＰ″ＥＴに適用した
場合ＦＥＴの７丁の均一化、１ｍが向上するという効果
を得ることが出来る工業上値れたものである。Effects of the Invention As explained in the Examples above, the compound semiconductor substrate and the manufacturing method thereof of the present invention have a layer containing poron (
For example, when applied to a P″ET, it is industrially valuable because it can achieve the effect of making the FET 7 uniform and improving the length of 1 m.
第１図（ＩＬ）〜（ｄ）は本発明の一実施例にがかるＦ
ＥＴの製造工程時の断面図、第２図、第３図、第４図は
それぞれ本発明の他の実施例にがかるＦＥＴの断面図で
ある。
１・・・・・・半絶縁性Ｇａ Ａｓ基板、２・・・・・
・Ｂイオン、３・・・・・・Ｂ注入層、４・・・・・・
Ｂ含有層、了・・・・・・ｎ型半導体装置
第１図
第４図FIGS. 1(IL) to (d) show an F according to an embodiment of the present invention.
2, 3, and 4 are cross-sectional views of FETs according to other embodiments of the present invention, respectively. 1... Semi-insulating Ga As substrate, 2...
・B ion, 3...B injection layer, 4...
B-containing layer, end...n-type semiconductor device Fig. 1 Fig. 4
Claims (1)
合物半導体基板。 に）） ｎ型半導体領域を有し、その側壁、底面の少な
くともいずれかの面がボロンを含有する層の近傍にある
ことを特徴とする特許請求の範囲第１項に記載の化合物
半導体基板。 （３）半絶縁性化合物半導体基板にボロンをイオン注入
する工程と、前記基板を熱処理する工程とによシボロン
を含有する層を形成することを特徴とする化合物半導体
基板の製造方法。[Scope of Claims] (1) A compound semiconductor substrate characterized by having a layer containing boron. 2)) The compound semiconductor substrate according to claim 1, wherein the compound semiconductor substrate has an n-type semiconductor region, and at least one of a side wall and a bottom surface of the n-type semiconductor region is located in the vicinity of a layer containing boron. (3) A method for manufacturing a compound semiconductor substrate, which comprises forming a layer containing boron by a step of ion-implanting boron into a semi-insulating compound semiconductor substrate and a step of heat-treating the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22145182A JPS59111373A (en) | 1982-12-16 | 1982-12-16 | Compound semiconductor substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22145182A JPS59111373A (en) | 1982-12-16 | 1982-12-16 | Compound semiconductor substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59111373A true JPS59111373A (en) | 1984-06-27 |
Family
ID=16766931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22145182A Pending JPS59111373A (en) | 1982-12-16 | 1982-12-16 | Compound semiconductor substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59111373A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61199667A (en) * | 1985-02-28 | 1986-09-04 | Oki Electric Ind Co Ltd | Gaas field-effect transistor |
| EP0415660A2 (en) * | 1989-08-28 | 1991-03-06 | Motorola, Inc. | FET having a high trap concentration interface layer and method of fabrication |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132272A (en) * | 1974-09-13 | 1976-03-18 | Hitachi Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS5618430A (en) * | 1979-07-25 | 1981-02-21 | Fujitsu Ltd | Manufacture of semiconductor element |
| JPS5688322A (en) * | 1979-12-20 | 1981-07-17 | Sony Corp | Processing method for semiconductor substrate |
| JPS57196582A (en) * | 1981-05-27 | 1982-12-02 | Matsushita Electric Ind Co Ltd | Field-effect transistor |
| JPS58148462A (en) * | 1982-02-26 | 1983-09-03 | Mitsubishi Electric Corp | Manufacture of compound semiconductor memory element |
-
1982
- 1982-12-16 JP JP22145182A patent/JPS59111373A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132272A (en) * | 1974-09-13 | 1976-03-18 | Hitachi Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS5618430A (en) * | 1979-07-25 | 1981-02-21 | Fujitsu Ltd | Manufacture of semiconductor element |
| JPS5688322A (en) * | 1979-12-20 | 1981-07-17 | Sony Corp | Processing method for semiconductor substrate |
| JPS57196582A (en) * | 1981-05-27 | 1982-12-02 | Matsushita Electric Ind Co Ltd | Field-effect transistor |
| JPS58148462A (en) * | 1982-02-26 | 1983-09-03 | Mitsubishi Electric Corp | Manufacture of compound semiconductor memory element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61199667A (en) * | 1985-02-28 | 1986-09-04 | Oki Electric Ind Co Ltd | Gaas field-effect transistor |
| EP0415660A2 (en) * | 1989-08-28 | 1991-03-06 | Motorola, Inc. | FET having a high trap concentration interface layer and method of fabrication |
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