CA2822663C - Device having reduced bias temperature instability (bti) - Google Patents

Device having reduced bias temperature instability (bti) Download PDF

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Publication number
CA2822663C
CA2822663C CA2822663A CA2822663A CA2822663C CA 2822663 C CA2822663 C CA 2822663C CA 2822663 A CA2822663 A CA 2822663A CA 2822663 A CA2822663 A CA 2822663A CA 2822663 C CA2822663 C CA 2822663C
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layer
type
source
source electrode
disposed
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CA2822663A
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English (en)
French (fr)
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CA2822663A1 (en
Inventor
Joseph Darryl Michael
Stephen Daley Arthur
Tammy Lynn Johnson
David Alan Lilienfeld
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General Electric Co
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General Electric Co
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0115—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CA2822663A 2012-08-06 2013-08-01 Device having reduced bias temperature instability (bti) Active CA2822663C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/567,791 US9257283B2 (en) 2012-08-06 2012-08-06 Device having reduced bias temperature instability (BTI)
US13/567,791 2012-08-06

Publications (2)

Publication Number Publication Date
CA2822663A1 CA2822663A1 (en) 2014-02-06
CA2822663C true CA2822663C (en) 2020-09-01

Family

ID=48948276

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2822663A Active CA2822663C (en) 2012-08-06 2013-08-01 Device having reduced bias temperature instability (bti)

Country Status (6)

Country Link
US (1) US9257283B2 (enExample)
EP (1) EP2696366B1 (enExample)
JP (1) JP2014033200A (enExample)
CN (1) CN103578933B (enExample)
BR (1) BR102013019891B1 (enExample)
CA (1) CA2822663C (enExample)

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US10367089B2 (en) 2011-03-28 2019-07-30 General Electric Company Semiconductor device and method for reduced bias threshold instability
US9576868B2 (en) * 2012-07-30 2017-02-21 General Electric Company Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices
JP6480860B2 (ja) * 2013-03-29 2019-03-13 富士電機株式会社 半導体装置および半導体装置の製造方法
US8994118B2 (en) 2013-04-04 2015-03-31 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same
US9425153B2 (en) 2013-04-04 2016-08-23 Monolith Semiconductor Inc. Semiconductor devices comprising getter layers and methods of making and using the same
US9035395B2 (en) 2013-04-04 2015-05-19 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same
JP6582537B2 (ja) * 2015-05-13 2019-10-02 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2017168602A (ja) * 2016-03-15 2017-09-21 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6772495B2 (ja) * 2016-03-16 2020-10-21 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7062946B2 (ja) 2017-12-25 2022-05-09 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2022047649A1 (en) * 2020-09-02 2022-03-10 Yangtze Memory Technologies Co., Ltd. Pad-out structure for xtacking architecture

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US6544853B1 (en) 2002-01-18 2003-04-08 Infineon Technologies Ag Reduction of negative bias temperature instability using fluorine implantation
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JP5777455B2 (ja) * 2011-09-08 2015-09-09 株式会社東芝 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
CN103578933B (zh) 2018-03-30
BR102013019891B1 (pt) 2020-12-01
JP2014033200A (ja) 2014-02-20
US9257283B2 (en) 2016-02-09
EP2696366A3 (en) 2014-11-12
CA2822663A1 (en) 2014-02-06
BR102013019891A8 (pt) 2015-12-08
US20140034963A1 (en) 2014-02-06
EP2696366A2 (en) 2014-02-12
BR102013019891A2 (pt) 2015-11-10
CN103578933A (zh) 2014-02-12
EP2696366B1 (en) 2018-06-27

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