CA2285627A1 - Procede de production des sillons plats - Google Patents
Procede de production des sillons plats Download PDFInfo
- Publication number
- CA2285627A1 CA2285627A1 CA002285627A CA2285627A CA2285627A1 CA 2285627 A1 CA2285627 A1 CA 2285627A1 CA 002285627 A CA002285627 A CA 002285627A CA 2285627 A CA2285627 A CA 2285627A CA 2285627 A1 CA2285627 A1 CA 2285627A1
- Authority
- CA
- Canada
- Prior art keywords
- trench
- layer
- insulating
- semiconductor material
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
La présente invention concerne un procédé d'amélioration de la topographie sur des structures de sillon dans lesquelles l'apport d'un matériau polysemiconducteur supplémentaire, par exemple du polysilicium 20, du nitrate ou un oxyde, dans les régions des bords de sillon, et si nécessaire, l'oxydation ultérieure du matériau supplémentaire, empêchent l'apparition de régions de tension mécanique élevée.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9701154-8 | 1997-03-26 | ||
SE9701154A SE520115C2 (sv) | 1997-03-26 | 1997-03-26 | Diken med plan ovansida |
PCT/SE1998/000528 WO1998043293A1 (fr) | 1997-03-26 | 1998-03-23 | Procede de production des sillons plats |
Publications (1)
Publication Number | Publication Date |
---|---|
CA2285627A1 true CA2285627A1 (fr) | 1998-10-01 |
Family
ID=20406360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002285627A Abandoned CA2285627A1 (fr) | 1997-03-26 | 1998-03-23 | Procede de production des sillons plats |
Country Status (9)
Country | Link |
---|---|
EP (1) | EP1018156A1 (fr) |
JP (1) | JP2001519097A (fr) |
KR (1) | KR100374455B1 (fr) |
CN (1) | CN1110848C (fr) |
AU (1) | AU6753998A (fr) |
CA (1) | CA2285627A1 (fr) |
SE (1) | SE520115C2 (fr) |
TW (1) | TW356579B (fr) |
WO (1) | WO1998043293A1 (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6498383B2 (en) * | 2001-05-23 | 2002-12-24 | International Business Machines Corporation | Oxynitride shallow trench isolation and method of formation |
US6461936B1 (en) * | 2002-01-04 | 2002-10-08 | Infineon Technologies Ag | Double pullback method of filling an isolation trench |
JP2008028357A (ja) | 2006-07-24 | 2008-02-07 | Hynix Semiconductor Inc | 半導体素子及びその製造方法 |
JP4717122B2 (ja) * | 2009-01-13 | 2011-07-06 | 三菱電機株式会社 | 薄膜太陽電池の製造方法 |
CN102468176B (zh) * | 2010-11-19 | 2013-12-18 | 上海华虹Nec电子有限公司 | 超级结器件制造纵向区的方法 |
CN103822735A (zh) * | 2012-11-16 | 2014-05-28 | 无锡华润上华半导体有限公司 | 一种压力传感器用晶片结构及该晶片结构的加工方法 |
CN107507773B (zh) * | 2016-06-14 | 2021-09-17 | 格科微电子(上海)有限公司 | 优化cmos图像传感器晶体管结构的方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2207281B (en) * | 1987-07-24 | 1992-02-05 | Plessey Co Plc | A method of providing refilled trenches |
US5175122A (en) * | 1991-06-28 | 1992-12-29 | Digital Equipment Corporation | Planarization process for trench isolation in integrated circuit manufacture |
US5561073A (en) * | 1992-03-13 | 1996-10-01 | Jerome; Rick C. | Method of fabricating an isolation trench for analog bipolar devices in harsh environments |
US5627092A (en) * | 1994-09-26 | 1997-05-06 | Siemens Aktiengesellschaft | Deep trench dram process on SOI for low leakage DRAM cell |
US5683945A (en) * | 1996-05-16 | 1997-11-04 | Siemens Aktiengesellschaft | Uniform trench fill recess by means of isotropic etching |
-
1997
- 1997-03-26 SE SE9701154A patent/SE520115C2/sv not_active IP Right Cessation
- 1997-04-18 TW TW086105057A patent/TW356579B/zh active
-
1998
- 1998-03-23 CA CA002285627A patent/CA2285627A1/fr not_active Abandoned
- 1998-03-23 EP EP98912851A patent/EP1018156A1/fr not_active Withdrawn
- 1998-03-23 WO PCT/SE1998/000528 patent/WO1998043293A1/fr active IP Right Grant
- 1998-03-23 CN CN98805442A patent/CN1110848C/zh not_active Expired - Fee Related
- 1998-03-23 AU AU67539/98A patent/AU6753998A/en not_active Abandoned
- 1998-03-23 JP JP54556198A patent/JP2001519097A/ja not_active Abandoned
- 1998-03-23 KR KR10-1999-7008655A patent/KR100374455B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO1998043293A1 (fr) | 1998-10-01 |
EP1018156A1 (fr) | 2000-07-12 |
JP2001519097A (ja) | 2001-10-16 |
AU6753998A (en) | 1998-10-20 |
SE9701154L (sv) | 1998-09-27 |
SE9701154D0 (sv) | 1997-03-26 |
TW356579B (en) | 1999-04-21 |
CN1257609A (zh) | 2000-06-21 |
SE520115C2 (sv) | 2003-05-27 |
CN1110848C (zh) | 2003-06-04 |
KR100374455B1 (ko) | 2003-03-04 |
KR20010005591A (ko) | 2001-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FZDE | Dead |