KR970018364A - 반도체 장치의 소자분리 방법 - Google Patents

반도체 장치의 소자분리 방법 Download PDF

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Publication number
KR970018364A
KR970018364A KR1019950030084A KR19950030084A KR970018364A KR 970018364 A KR970018364 A KR 970018364A KR 1019950030084 A KR1019950030084 A KR 1019950030084A KR 19950030084 A KR19950030084 A KR 19950030084A KR 970018364 A KR970018364 A KR 970018364A
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South Korea
Prior art keywords
trench
film
psg film
heat treatment
insulating
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KR1019950030084A
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English (en)
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KR0183738B1 (ko
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김윤기
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김광호
삼성전자 주식회사
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Priority to KR1019950030084A priority Critical patent/KR0183738B1/ko
Publication of KR970018364A publication Critical patent/KR970018364A/ko
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Publication of KR0183738B1 publication Critical patent/KR0183738B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

신규한 반도체장치의 소자분리방법이 개시되어 있다. 반도체기판의 소정깊이로 식각하여 트렌치를 형성한 후, 결과물 상에 제1절연막으로서 PSG막을 침적한다. 1000℃이상의 고온에서 열처리를 실시하여 PSG막을 리플로우시킨 후, 결과물 상에 제2절연막을 침적한다. 화학기계폴리싱(CMP)방법으로 제2절연막을 식각하여 트렌치를 필링시킨다. 고온열처리로 PSG막을 리플로우시킴으로써, 트렌치의 단차를 감소시켜 보이드의 형성을 방지할 수 있다.

Description

반도체 장치의 소자분리 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 베2E도는 본 발명에 의한 반도체장치의 소자분리방법을 설명하기 위한 단면도들.

Claims (8)

  1. 반도체기판을 소정깊이로 식각하여 트렌치를 형성하는 단계; 상기 결과물 상에 제1절연막으로서 PSG막을 침적하는 단계; 1000℃ 이상의 고온에서 열처리를 실시하여 상기 PSG막을 리플로우시키는 단계; 상기 결과물 상에 제2절연막을 침적시하는 단계; 및 화학기계플리싱(CMP) 방법으로 상기 제2절연막을 식각하여 상기 트렌치를 필링시키는 단계를 구비하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  2. 제1항에 있어서, 상기 PSG막은 상기 트렌치 폭의 1/2보다 작은 두께라 형성하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  3. 제1항에 있어서, 상기 고온 열처리의 온도는 1000℃∼1200℃의 범위 내에 있는 것을 특징으로 하는 반도체장치의 소자분리방법.
  4. 제1항에 있어서, 상기 제2절연막을 침적하는 단계 전에, 상기 트렌치를 제외한 반도체기판 상에 잔류하고 있는 상기 PSG막을 에치백방법으로 제거하는 단계를 더 구비하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  5. 제1항에 있어서, 상기 PSG막을 침척하는 단계 전에, 상기 트렌치의 측벽에 절연물질로 이루어진 스페이서를 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  6. 제1항에 있어서, 상기 CMP 방법을 과도하게 실시하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  7. 제1 에 있어서, 상기 CMP 방법을 실시한 후 에치백 방법을 더 실시하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  8. 제1항에 있어서, 상기 제2절연막은 USG막으로 형성하는 것을 특징으로 하는 반도체장치의 소자분리방법.
KR1019950030084A 1995-09-14 1995-09-14 반도체장치의 소자분리방법 KR0183738B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950030084A KR0183738B1 (ko) 1995-09-14 1995-09-14 반도체장치의 소자분리방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030084A KR0183738B1 (ko) 1995-09-14 1995-09-14 반도체장치의 소자분리방법

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KR970018364A true KR970018364A (ko) 1997-04-30
KR0183738B1 KR0183738B1 (ko) 1999-04-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020055938A (ko) * 2000-12-29 2002-07-10 박종섭 반도체 소자의 소자 분리막 형성 방법
KR100607770B1 (ko) * 2002-12-30 2006-08-01 동부일렉트로닉스 주식회사 Ｓｔｉ 제조 방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010084524A (ko) * 2000-02-26 2001-09-06 박종섭 반도체소자의 격리영역 형성방법
KR100518536B1 (ko) * 2002-08-07 2005-10-04 삼성전자주식회사 반도체 소자의 표면 평탄화 방법과 그에 따라 제조된반도체 소자
KR100744943B1 (ko) * 2005-12-14 2007-08-01 동부일렉트로닉스 주식회사 트랜치 소자분리막 형성방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020055938A (ko) * 2000-12-29 2002-07-10 박종섭 반도체 소자의 소자 분리막 형성 방법
KR100607770B1 (ko) * 2002-12-30 2006-08-01 동부일렉트로닉스 주식회사 Ｓｔｉ 제조 방법

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KR0183738B1 (ko) 1999-04-15

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