SE9701154D0 - Planer trenches - Google Patents

Planer trenches

Info

Publication number
SE9701154D0
SE9701154D0 SE9701154A SE9701154A SE9701154D0 SE 9701154 D0 SE9701154 D0 SE 9701154D0 SE 9701154 A SE9701154 A SE 9701154A SE 9701154 A SE9701154 A SE 9701154A SE 9701154 D0 SE9701154 D0 SE 9701154D0
Authority
SE
Sweden
Prior art keywords
trenches
plan
regions
extra
polysilicon
Prior art date
Application number
SE9701154A
Other languages
English (en)
Other versions
SE520115C2 (sv
SE9701154L (sv
Inventor
Anders Karl Sivert Soederbaerg
Nils Ola Oegren
Ernst Haakan Sjoedin
Olof Mikael Zackrisson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9701154A priority Critical patent/SE520115C2/sv
Publication of SE9701154D0 publication Critical patent/SE9701154D0/sv
Priority to TW086105057A priority patent/TW356579B/zh
Priority to CN98805442A priority patent/CN1110848C/zh
Priority to CA002285627A priority patent/CA2285627A1/en
Priority to KR10-1999-7008655A priority patent/KR100374455B1/ko
Priority to PCT/SE1998/000528 priority patent/WO1998043293A1/en
Priority to EP98912851A priority patent/EP1018156A1/en
Priority to JP54556198A priority patent/JP2001519097A/ja
Priority to AU67539/98A priority patent/AU6753998A/en
Publication of SE9701154L publication Critical patent/SE9701154L/sv
Publication of SE520115C2 publication Critical patent/SE520115C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
SE9701154A 1997-03-26 1997-03-26 Diken med plan ovansida SE520115C2 (sv)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SE9701154A SE520115C2 (sv) 1997-03-26 1997-03-26 Diken med plan ovansida
TW086105057A TW356579B (en) 1997-03-26 1997-04-18 Planar trenches
AU67539/98A AU6753998A (en) 1997-03-26 1998-03-23 Method for producing planar trenches
KR10-1999-7008655A KR100374455B1 (ko) 1997-03-26 1998-03-23 평면 트렌치의 제조 방법
CA002285627A CA2285627A1 (en) 1997-03-26 1998-03-23 Method for producing planar trenches
CN98805442A CN1110848C (zh) 1997-03-26 1998-03-23 在半导体衬底中制造平面绝缘沟槽的方法
PCT/SE1998/000528 WO1998043293A1 (en) 1997-03-26 1998-03-23 Method for producing planar trenches
EP98912851A EP1018156A1 (en) 1997-03-26 1998-03-23 Method for producing planar trenches
JP54556198A JP2001519097A (ja) 1997-03-26 1998-03-23 プレーナトレンチの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9701154A SE520115C2 (sv) 1997-03-26 1997-03-26 Diken med plan ovansida

Publications (3)

Publication Number Publication Date
SE9701154D0 true SE9701154D0 (sv) 1997-03-26
SE9701154L SE9701154L (sv) 1998-09-27
SE520115C2 SE520115C2 (sv) 2003-05-27

Family

ID=20406360

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9701154A SE520115C2 (sv) 1997-03-26 1997-03-26 Diken med plan ovansida

Country Status (9)

Country Link
EP (1) EP1018156A1 (sv)
JP (1) JP2001519097A (sv)
KR (1) KR100374455B1 (sv)
CN (1) CN1110848C (sv)
AU (1) AU6753998A (sv)
CA (1) CA2285627A1 (sv)
SE (1) SE520115C2 (sv)
TW (1) TW356579B (sv)
WO (1) WO1998043293A1 (sv)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498383B2 (en) * 2001-05-23 2002-12-24 International Business Machines Corporation Oxynitride shallow trench isolation and method of formation
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
JP2008028357A (ja) * 2006-07-24 2008-02-07 Hynix Semiconductor Inc 半導体素子及びその製造方法
JP4717122B2 (ja) * 2009-01-13 2011-07-06 三菱電機株式会社 薄膜太陽電池の製造方法
CN102468176B (zh) * 2010-11-19 2013-12-18 上海华虹Nec电子有限公司 超级结器件制造纵向区的方法
CN103822735A (zh) * 2012-11-16 2014-05-28 无锡华润上华半导体有限公司 一种压力传感器用晶片结构及该晶片结构的加工方法
CN107507773B (zh) * 2016-06-14 2021-09-17 格科微电子（上海）有限公司 优化cmos图像传感器晶体管结构的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture
US5561073A (en) * 1992-03-13 1996-10-01 Jerome; Rick C. Method of fabricating an isolation trench for analog bipolar devices in harsh environments
US5627092A (en) * 1994-09-26 1997-05-06 Siemens Aktiengesellschaft Deep trench dram process on SOI for low leakage DRAM cell
US5683945A (en) * 1996-05-16 1997-11-04 Siemens Aktiengesellschaft Uniform trench fill recess by means of isotropic etching

Also Published As

Publication number Publication date
TW356579B (en) 1999-04-21
KR20010005591A (ko) 2001-01-15
KR100374455B1 (ko) 2003-03-04
EP1018156A1 (en) 2000-07-12
JP2001519097A (ja) 2001-10-16
CN1257609A (zh) 2000-06-21
WO1998043293A1 (en) 1998-10-01
SE520115C2 (sv) 2003-05-27
SE9701154L (sv) 1998-09-27
CN1110848C (zh) 2003-06-04
AU6753998A (en) 1998-10-20
CA2285627A1 (en) 1998-10-01

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Legal Events

Date Code Title Description
NUG Patent has lapsed